JP2003532307A - S-parameter microscopic analysis for semiconductor devices - Google Patents

Abstract

(57) [Summary] A method using bias-dependent S-parameter measurement as one form of microscopic analysis (FIG. 5). Microscopic analysis can be used to elucidate the details of the internal charge and electric field structure of a semiconductor device. As with other forms of microscopic analysis, S-parameter microscopic analysis focuses on pseudo "images" and contrasts them in the "images." In essence, images are collected in raw form as S-parameter measurements and extracted as small signal models. The model is used to form a charge control map (32) by a selective method similar to the focusing method. The focusing method is performed by an algorithm that uniquely determines small signal parameters, and contrasted by utilizing the measured bias-dependent activity to determine the boundaries between charge and electric field.

Description

Detailed Description of the Invention

Citation Regarding Related Applications This application is related to US patent application Ser. No. 60 / 200,30, filed April 28, 2000.
It is a continuation application of No. 7, and claims its priority.

This application is co-pending patent application No. 09 / 680,339 filed October 5, 2000 by the same applicant as this application, "METHOD FOR UNI" by inventor Roger Tsai.
QUE DETERMINATION OF FET EQUIVALENT CIRCUIT MODEL PARAMETERS "(a method for uniquely determining FET equivalent circuit model parameters). This application is also related to the following co-pending patent applications by the same applicant as this application. These were all filed on April 28, 2000. Patent Application No. 60 / 200,810:
"EMBEDDING PARASITIC MODEL FOR PI-FET LAYOUTS" by inventor Roger Tsai (
Embedding a parasitic model for PI-FET layout), Patent Application No. 60/200,
No. 648: "SEMI-PHYSICAL MODELING OF HEMT DC-TO-H" by inventor Roger Tsai
IGH FREQUENCY ELECTROTHERMAL CHARACTERISTICS "(HEMT / DC-semi-physical modeling of high frequency thermoelectric properties), Patent Application No. 60 / 200,290: Inventor Roge
r Tsai `` SEMI-PHYSICAL MODELING OF HEMT HIGH FREQUENCY NOISE EQUIVA
LENT CIRCUIT MODELS (semi-physical modeling of HEMT high frequency noise equivalent circuit model), Patent Application No. 60 / 200,666: "SEMI-PHY" by inventor Roger Tsai
SICAL MODELING OF HEMT HIGH FREQUENCY SMALL SIGNAL EQUIVALENT CIRCUIT MO
DELS "(semi-physical modeling of HEMT high frequency small signal equivalent circuit model), Patent Application No. 60 / 200,622:" HY "by inventors Roger Tsai and Yaochung Chen
BRID SEMI-PHYSICAL AND DATA FITTING HEMT MODOELING APPROACH FOR LARGE SI
GNAL AND NON-LINEAR MICROWAVE / MILLIMETER WAVE CIRCUIT CAD "(Hybrid Semi-Physical and Data-Compatible HEMT Modeling Method for Large Signal and Non-Linear Microwave / Millimeter Wave Circuit CAD), and Patent Application No. 60 / 200,302: Inventor
"PM ² : PROCESS PERTURBATION TO MEASURED-MODELED METHOD F" by Roger Tsai
OR SEMICONDUCTOR DEVICE TECHNOLOGY MODELING "(PM ² : Measurement for Semiconductor Device Technology Modeling-Process Perturbation to Model Method).

[0003] Background of the Invention 1. FIELD OF THE INVENTION The present invention relates to methods of modeling semiconductor device technology, and more particularly to methods of modeling semiconductor device technology such as field effect transistors (FETs). The high electron transfer transistor (HEMT) is one of them. The modeling process of semiconductor device technology involves directly characterizing how the device operates internally. This special method is based on the S-parameter microscope (
Analysis) to determine electrical properties corresponding to the internal structure of the semiconductor device, such as the magnitude, state, and location of internal charges and electric fields, and to enable device performance prediction. A semiconductor device technology model allows the electrical performance of any device made by a particular technology to be predicted based on only physically relevant parameters. By making this possible,
It is possible to predict the performance of circuits built using these devices.

2. 2. Description of the Prior Art The ability to accurately predict product yield for integrated circuits such as microwave monolithic integrated circuits (MMICs) is a valuable asset in semiconductor manufacturing. Yield prediction enables improved allocation of limited manufacturing resources, identification of yield issues, and reduced manufacturing costs. In the production of GaAs MMICs, the yield problem regarding RF operation arises from the situation that products must be produced for new markets under reduced design cost and time-to-market cycles. The probability of doing it has increased. These risks are exacerbated by pushing RF operating specifications to the limits of semiconductor device technology in response to today's increasingly competitive environment.

In addressing the cause of the low yield of MMIC RF, the cause cannot be identified and the problem may progress unknowingly. That is, RF yield problems may arise as a result of the inconvenience of being scattered but scattered throughout the manufacturing process. FIG. 1 shows the main mechanism involved in the yield reduction in the MMIC manufacturing process. As shown, four of the seven possible mechanisms are strongly involved in RF yield reduction. Factors such as unrealistic operating specifications, poor manufacturing design, and process variability reduce RF yields individually or collectively, thus increasing long-term manufacturing costs and design-to-manufacturing. There is a risk of extending the cycle time of.

Various methods are used to predict the RF yield. For example, both statistical and empirical modeling methods are known. Statistical modeling uses device models and circuit simulations, while empirical methods use measured data.
Such statistical models include Monte Carlo statistical models, correlation statistical models, boundary models, and database models. The Monte Carlo statistical model allows Gaussian statistics to vary the parameters of the device model independently of each other, while the correlation statistical model provides more realistic statistics whose variation is constrained by the correlation between the model parameters. It is known to represent. Long term model databases are typically created for process control monitoring purposes, but can also be used for yield prediction. For example, "A Product Engineeri by M. King et al.
ng Exercise in 6-Sigma Manufacturability: Redesign of pHEMT Wideband LNA
"(Product Design Exercise in 6-Sigma Productivity: Redesign of pHEMT Broadband LNA), 1999 GaAs MANTECH Technical Digest , pp.91-94 (April 1999).

[0007]   The boundary model represents the process corner performance.
It is a set of models. Boundary models are new to predicted process variations.
It is known to be ideal for quickly assessing the robustness of a design. how many
Manufacturers directly assess robustness through "process corner experiment"
It is known to have developed a method. For example, G. Garcia, et al.'S "GaAs Fa
bs Approach to Design-for-Manufacturability "(design method for productivity), 1999 GaAs MANTECH Technical Digest , pp.99-102 (April 1999)
Has been. However, the boundary method is the basis of yield calculation, which is the RF performance distribution.
It cannot be used to determine (RF performance distribution). did
Therefore, this method is not suitable for RF yield prediction.

The long-term model database is a powerful tool for MMIC process control monitoring, and a large amount of small signal equivalent circuit model extraction for a single fixed device structure measured under a standard set of bias conditions. Typically consists of a sample of The database model accurately captures true process variations through uniform sampling. Unfortunately, such models are limited to applications that are closely based on the original measurements. For example, it is problematic to develop a database model with high precision to represent devices with different bias conditions and layouts. This judgment is based on the above-mentioned "A Product Engineering Exercise in 6-Sigma Manufacturability".
: Redesign of a pHEMT Wide-Band LNA ”, as described schematically in" Redesign of a pHEMT Wide-Band LNA ". In other situations, database results can be used, for example, low noise or low signal results from small signal models. Applying to predict is virtually impossible or a bad idea.

Monte Carlo statistics make it easy to perform PR yield simulations.
However, the predictions obtained by this method are relatively inaccurate and are typically used for worst-case yield analysis. Specifically, FIGS. 2A and 2B show examples of low-accuracy yield prediction performed by Monte Carlo and the correlation statistical model. They are,
2 shows simulated noise and gain statistics as well as actual noise and gain statistics for a 22-26 GHz GaAs pHEMT LNA. As shown, squares and circles represent data points simulated by the correlation statistics and Monte Carlo statistical models, respectively, and dashed lines represent measured data points.

The correlation statistical model provides a better method than the Monte Carlo method, but the results obtained from this method may also be less accurate. Correlation statistical models have the additional drawback of requiring a large amount of model databases to obtain correlations.
This often results in method constraints and compromises long-term model databases.

As mentioned above, empirical prediction is also known to be used to predict RF yield. Such empirical prediction methods use known process-dependent RF yield characteristics of another circuit to predict the long-term RF yield of one circuit.
This method can be thought of as yield mapping, and has critical RF operating parameters and measurement device process control monitoring (PCM).
nitor) Use a linear mapping transformation between data. This transformation is known to be used to map PCM data into circuit operating space. PCM
All parameter distributions are converted to RF operation distributions. An example of such conversion is shown in FIG. FIG. 3 shows the conversion of the device PCM into the MMIC RF operating space. To apply this yield map design to another circuit, an offset is included to account for the differences associated with the design. With such empirical methods, it is known that the predictions made for noise figure and small signal gain performance are accurate, but not for power. As an example, 35 GHz GaAs pHE
A comparison of the predicted and measured noise figure performance for MT LNAs is shown in FIG.
Shown in. Here, the predicted data are shown by lines and the measured data are shown by squares.

[0012] One of the drawbacks of yield mapping is that it can be used with R before it is designed.
That is, the F motion cannot be predicted with high accuracy. Rather, before the start of production (pre-produ
As the design-dependent offset is determined by the feedback from the ction run), the prediction must be made accurate.

In order to accurately model the characteristics of the semiconductor device, the length of the linear conductance region, the magnitude of the saturation electric field, and the effective transition distance of the saturated carrier (transit d
It is necessary to obtain a phenomenon associated with the internal structure of the device, such as an instance). It is known that finite element device simulations are used to calculate the internal charge / field structure of a device. Unfortunately, such device simulations are generally inaccurate and can only yield results that are very different from the measured device statistics. Therefore, there is a shortage of analytical techniques that can accurately model semiconductor devices by elucidating and measuring the electrical characteristics associated with the internal structure of semiconductor devices.

[0014] Briefly Summary of the Invention, the present invention is, as a form of microscopic analysis, to a method of using a bias-dependent S- parameter measurements. Microscopic analysis can be used to reveal details of the internal charge and electric field structure of semiconductor devices. Similar to other forms of microscopic analysis, S-parameter microscopic analysis focuses on a pseudo "image" and contrasts on that "image." In essence, the images are collected in raw form as S-parameter measurements and extracted as a small signal model. The model is
It is used to form the charge control map by a selective method similar to focusing. Bias-dependent activity measured by performing the focusing method using an algorithm that uniquely determines small-signal parameters.
To determine the boundary between the electric charge and the electric field. Therefore, the present system can provide a model that accurately describes the internal electrical structure of a semiconductor device.

These and other advantages of the invention will be readily appreciated by reference to the following specification and attached drawings.

DETAILED DESCRIPTION The present invention relates to S-parameter microscopic analysis (SPM) that allows qualitative investigation of the magnitude and location of charge and electric field distributions within the structure of semiconductor devices. The method utilizes bias-dependent S-parameter measurements as a form of microscopic analysis to perform a qualitative analysis of previously unknown internal charge and electric field structures of semiconductor structures. A pseudo image is collected in the form of S-parameter measurements extracted as a small signal model to form a charge control map. Finite element device simulation has heretofore been used to calculate the internal charge / electric field of semiconductor devices, but such methods are known to be relatively inaccurate. According to the present invention, S-parameter microscopic analysis provides a relatively accurate method for determining internal charges and electric fields within semiconductor devices. By modeling the internal charge and the electric field with high accuracy, it becomes possible to model all the external electrical characteristics of the semiconductor device including the high frequency operation thereof with relatively high accuracy. As such, the system is suitable for creating device technology models and enables design for high frequency MMIC yield analysis prediction and manufacturing analysis.

S-parameter microscopic analysis, like other microscopic analysis techniques, takes advantage of measurements of energy reflected by and reflected from the sample by the SPM. More specifically, SPM is based on transmitted and reflected microwave and millimeter wave electromagnetic power, or S-parameters. Therefore, S-parameter microscopy analysis is similar to the combined operation of scanning and transmission electron microscopy (SEM and TEM). The scattered RF energy is similar to the reflection and transmission of electron beams in SEM and TEM. However, S
Instead of using electron detectors as in EM and TEM, S-parameter microscopy analyzes use a reflectometer in a network analyzer to measure the signal. The S-parameter microscopic analysis, like other microscopic analysis techniques, utilizes the measured values of both scattering phenomena as data and includes a mechanism for narrowing the measured values in order to increase the resolution, comparing multiple parts of the measured values. However, a mechanism for determining details is included as shown in Table 1 below.

[0018]

[Table 1]

Results : Detailed "images" of the internal charge and electric field structure of the device. The images discussed here in connection with S-parameter microscopic analysis are independent of the actual images and provide insights and quantitative details about the internal workings of the device. Used to obtain. More specifically, S-parameter microscopic analysis does not provide a visual image as in conventional microscopic analysis configurations. Rather, it is better to say that the S-parameter microscopic analysis image resembles a map based on a set of non-intuitive measurements obtained by calculation.

FIG. 5 shows a conceptual diagram of an S-parameter microscope according to the present invention, generally identified by reference numeral 20. The S-parameter microscope 20 includes SEM and TEM.
It is similar to a microscope that combines the principles of. The SEM measures reflection and the TEM measures transmission, whereas the two-port S-parameter microscope 20 measures both reflected and transmitted power. As a result, the data obtained from the 2-port S-parameter microscope contains information about the intrinsic and extrinsic charge structures of the device. More specifically, as is known in the art, S
The EM provides a relatively detailed image of the surface of the sample by reflected electrons, while the TEM provides an image of the internal structure by transmitted electrons. The reflected signal is used to form the external details of the sample and the transmitted electrons provide information about the internal structure of the device. In accordance with an important aspect of the present invention, S-parameter microscopic analysis utilizes the process of measuring reflected and transmitted signals and provides an "image" similar to the charge structure of a semiconductor device. As used herein, the internal and external electrical structures of a semiconductor device are commonly referred to as the intrinsic device region 22 and the extrinsic parasitic access region 24.
These are shown in FIG. Also contributing to the internal electrical structure of the device are parasitic components associated with its electrodes and interconnects, not shown. These are so-called layout parasitics.

Referring to FIG. 5, ports 26 and 28 are emulated by S-parameter measurements. S-parameter measurements for a particular semiconductor device, generally designated by the reference numeral 30, are processed in accordance with the present invention to yield a charge control map shown within a circle 32. This is similar to images in other microscopic analysis techniques. These charge control maps 32, described in more detail below, are represented in the form of an equivalent circuit model. As shown in FIG. 7, the model uses linear circuit elements to represent the magnitude / state of the charge / electric field within the semiconductor device 30, ie, the so-called internal electrical structure. The location of the circuit elements within the model topology roughly approximates the physical location within the device structure, so the charge control map represents the internal electrical structure diagram of the device.

It is known that the interpretation of the exact location of the measured charge / electric field in a semiconductor device is ambiguous. This is because, when expressing the charge / electric field distribution structure, for example,
This is because an equivalent circuit model using a single linear element as shown in FIG. 8 is used. Although there is no precise way to distinguish physical boundaries between measurands, bias dependence makes it clear how to distinguish, separate, and contrast S-parameters. That is, it has been found that changing the bias conditions changes the magnitude of the charge and electric field in the device, moving the boundaries between them. This change is usually predictable and qualitatively well understood by most technologies. Thus, the charge control map can be readily used as a map to characterize physical changes in charge and electric field magnitude, location and separation.

Similar to other forms of microscopic analysis, the S-parameter microscope 20 according to the present invention also emulates a lens identified by reference numeral 40 (FIG. 5). The simulation of the lens 40 is performed by a method of extracting a unique equivalent circuit model. This also accurately simulates the measured S-parameters. More specifically, parameter extraction methods for equivalent circuit models that simulate S-parameters are relatively well known. However, if the only goal is to fit (fit) and measure the S-parameters with precision, then there are only a finite number of possible equivalent circuit parameter values. Therefore, according to an important aspect of the present invention, only a single, unique solution is extracted that accurately describes the physical charge control map of the device. This method of uniquely extracting the equivalent circuit model parameters acts as a lens that focuses on the charge control map solution. As described and illustrated herein, a filter based on an apparent layout parasitic embedding model allows a lens 40
Is then simulated. As discussed below, the layout parasitic embedding model consists of linear elements that simulate the effects of device electrodes and interconnects on their external electrical properties. PiFET embedded model 4
2 will be described below. This model effectively acts as a filter that removes the electrical structure that is responsible for the tentative charge control map solution of the associated ectoparasites. The charge control map solution obtained after filtering represents a well-defined "image" and shows only the unique electrical structure of the device. This improved imaging is needed to visualize the internal charge and electric field with the highest possible accuracy. The conventional extraction technique as shown in FIG. 10 cannot extract a non-unique equivalent circuit model,
Moreover, it is not possible to extract a unique charge control map, but unlike this, the S-parameter microscope 20 according to the present invention is designed to
The structure of the electric field can be modeled with relatively high accuracy.

One application example of the S-parameter microscope will be described in detail below. In this example, G has four gate fingers and a total gate perimeter of 200 μm formed in a Pi-FET layout as shown schematically in FIG.
The aAs HEMT device is used as an example. The GaAs HEMT 43 has a structure embedded in a coplanar inspection structure with a pitch of 100 μm so that the S-parameter measurement can be easily performed on the wafer.

First, as shown in FIGS. 12 and 13, the IV characteristics of the device are measured. That is, as shown in FIG. 12, the drain-source current Ids is plotted as a function of the drain-source voltage Vds at various gate voltages Vgs.
FIG. 13 shows that as a function of the gate voltage Vgs and the transconductance Gm (ie, the derivative of Ids with respect to Vgs) at different drain voltages Vds.
The drain-source current Ids is shown. These IV characteristics are typical of HEMT devices and most semiconductor devices and are a type of three terminal semiconductor device technology.

Table 2 shows the bias conditions for which the S-parameters were measured. Under each bias condition, the S-parameter was measured from 0.05 to 40 GHz. FIG. 14 shows 0.
S-parameters S11, S measured at frequencies of 05 to 40.0 GHz
12 is a Smith chart showing S12 and S22. FIG. 15 shows 0.05 to 4
6 is a graph showing magnitude as a function of angle for S-parameter S21 measured at a frequency of 0.0 GHz.

[0027]

[Table 2]

Using the small signal model shown in FIG. 8, small signal equivalent circuit values extracted under each bias condition were obtained for each S-parameter as shown in Table 3. The extraction method used will be described below.

[0029]

[Table 3]

[0030]

[0031]

The values in Table 3 represent solutions that are close to the charge control map and represent physically significant solutions of the FET electrical structure. However, the values shown in Table 3 are
Including an effect of xternal layout parasitics), and according to an important aspect of the present invention, these are subtracted using a model for embedded parasitics to obtain the most accurate charge control mapping for the unique device characteristics. In particular, the embedded model is applied and the extracted equivalent circuit model value is filtered to obtain a value that better represents the unique device characteristic. That is, in one example of the embodiment, the PiFET embedded parasitic model is used to subtract the capacitive contribution due to the influence of inter-electrode and off-mesa layout parasitics. This filter essentially subtracts the known quantity formed from the device layout dependent parameters Cgs, Cgd and Cds. No embedding of inductive parameters is required in this example. This is because these quantities are external and do not contribute to the intrinsic device charge control map.

As discussed above, a filtered lens is used to generate a unique charge control map. That is, FIGS. 15-18 show the parameter RS as a function of bias.
, RD, RI, CGS and CGD bias dependent charge control maps. More specifically, FIG. 15 shows a charge control map of the charge and electric field distribution in the on-mesa source access region shown by the source resistance R _s as a function of bias. FIG. 16 shows a charge control map of the charge and electric field distribution in the on-mesa drain access region represented by drain resistance R _d as a function of bias. FIG. 17 shows a charge control map for non-quasi static majority carrier transport as indicated by the intrinsic device charging resistance R _i as a function of gate bias for different drain bias points. FIG. 18 shows the gate capacitances CGS and CGD as a function of bias,
7 shows a charge control map of gate modulation charge and distribution under the gate.

Filters As described above, the S-parameter microscope 20 utilizes filters to obtain a well-defined charge control map to model the internal charge / electric field of a semiconductor device. The filter is shown in the context of a PiFET with multiple gate fingers, as shown in FIG.
0 and FIG. 21, the principle of the present invention can be applied to other semiconductor devices.

As shown in FIG. 20, a PiFET is a device in which the edges of the gate fingers and active area resemble the Greek letter π, as shown. With such a PiFET layout, for example, as shown in FIG. 21, a device cell having a large number of fingers and a large circumference can be easily constructed. In accordance with an important aspect of the invention, a single finger device cell is combined to model a multi-finger semiconductor device. Each single finger device cell is represented by four model hierarchies and they are assembled and integrated using a model for interconnection to represent any multi-finger device cell. This is shown in FIG. Four
The two models are: Off-mesa or boundary parasitic model, inter-electrode parasitic model, on-mesa parasitic model, and intrinsic model.

An off-mesa parasitic model is shown in FIG. This model represents the parasitics that exist outside the active FET area for each gate finger. In this model, the fringe capacitance (fringing capacitanc) of each gate finger outside the active device area is
e), and model the off-mesa gate finger resistance.

The inter-electrode parasitic model and the corresponding equivalent circuit are shown in FIGS. 24 to 26. This model shows the parasitics between the metal electrodes along each gate finger. As shown schematically in FIG. 25, the following fringe capacitance parasitics cause the gate-source air bridge
(air bridge), gate-source air bridge, gate-source ohmic, gate-drain ohmic, and source-drain ohmic.

The on-mesa parasitic model and the corresponding equivalent circuit are shown in FIGS. 27 and 28.
This model represents the parasitics around the active FET region along each gate finger and includes various capacitive fringe parasitics and resistive parasitics. That is, a gate-source side recess, a gate-drain side recess, and a gate-source ingress charge (gate-
Model source access charge / doped cap, and gate-drain ingress charge / doped cap capacitance fringe parasitics. In addition, gate metallization and ohmic contact resistive parasitics are also modeled.

The eigenmodel and the corresponding equivalent circuit are shown in FIGS. 29 and 30. The eigenmodel represents the physical phenomenon that governs the operational decisions of a FET. That is, the DC and current-voltage response can be determined by a physical phenomenon-based analytical equation that represents the magnitude and position of the intrinsic charge. This is generally known in the art, eg
Hughes et al., `` Nonlinear Charge Control In AlGaAs Modulation-Doped FET
s "(Nonlinear charge control in AlGaAs modulation doped FET), IEEE Trans. E
lectron Devices, Vol. ED-34, No. 8 (April 1987). The contents of which are incorporated herein by this reference. To model the performance of a small signal model, the derivative of the appropriate charge or current control equation is determined, RI, RJ, RDS, RGS, RGD, GM, TAU, CGS, CD.
We derive various terms such as S and CGD. Such control equations are generally known in the art and are disclosed in detail in the Hughes et al reference, which was previously mentioned and incorporated herein by reference. Current or voltage perturbation analysis can be used to model noise effects. H. Statz, et al. “No
ise Characteristics of Gallium Arsenide Field-Effect Transistors ", IEEE-Trans. Electron Devices , vol. Ed-21 No. 9 (September 1974), and A. Van Der Ziel. "Gate Nois
e in Field Effect Transistors at Moderately High Frequencies ", Gate noise in field-effect transistors at moderately high frequencies, Proc. IEEE , vol.
51 (March 1963).

An example of a parasitic model for use with the S-parameter microscopy analysis described above is shown in FIG. 31A.
38 to 38. Although specific embodiments of semiconductor devices are shown and described, the principles of the present invention are applicable to various semiconductor devices. Referring to FIG. 31A, a Pi-FET is shown. As shown, the PiFET has four gate fingers. In FIG. 31B, a 4-finger Pi-FET is modeled. That is, FIG. 31B shows an equivalent circuit model of the Pi-FET shown in FIG. 31A. This was accomplished by known CAD programs, such as LIBRA 6.1 manufactured by Agilent Technologies. As shown, the equivalent circuit model does not show all of the equivalent circuit elements and network connections that accompany the implementation of the parasitic embedding model, but rather the finished product. FIG. 31B is displayed in a symbolic diagram to demonstrate similarity to FIG. The actual technical information on the construction of the network and its equivalent circuit elements is usually given in schematic diagrams.

32-38 show the application of the parasitic model for use with S-parameter microscopic analysis. An important aspect of the present invention relates to modeling multi-gate finger devices as a single-gate finger device. When used here,
By single unit device cell is meant a device with a single gate finger. For example, the 4-finger Pi-FET shown in FIG. 31A is modeled as 4 unit device cells.

First, the 4-finger Pi-FET shown in FIG. 31A is modeled as a single-finger unit device cell 100 with an eigenmodel 102, as shown in FIGS. 32 and 33. That is, the Pi-FET specific FET model 104 is used instead of the block 102 that defines the first level embedding. As shown in FIG. 33,
The parameter value of the Pi-FET specific model is added together with the parameter value of the single finger unit device cell specific model. The intrinsic device model 104 may also be formed by S-parameter microscopic analysis, as discussed above. next,
As shown in FIG. 34, interconnect layout parasitic elements are added to the equivalent model. In this case, the model term is simply added to the value of the appropriate circuit element to form a single unit device cell that defines the second level embedding. Once a single unit device cell is stylized, this device is used to build a model of a multi-fingered device. In this case, a Pi-FET with four gate fingers
Are modeled as four single finger device unit cells as shown in FIG. The off-mesa layout parasitic elements are then connected to a multi-finger layout to define the third level embedding as shown in FIG. These off-mesa layout parasitic elements are generally identified by the reference numerals 108 and 110. These are implemented as new circuit elements connected to the main external nodes of the equivalent circuit structure. Subsequently, as shown generally in FIG. 40, fourth level embedding is performed. That is, the inductor model is connected to the source of each of the various unit device cells to represent a metal bridge interconnect, as generally shown in FIG. Finally, as shown in FIG. 39, the fifth level embedding is performed. Here, feed electrode models 114 and 116 are represented by lumped linear elements (
Modeled as capacitors and inductors and as dispersive elements (i.e., microstrip lines and junctions) to form the gate feed and drain connections shown in FIG. As shown, the dispersive element is a dispersive model of microstrip elements, as implemented in LIBRA 6.1.

Extraction Method for Uniquely Determining FET Equivalent Circuit Model The method for determining the FET equivalent circuit parameters discussed above is described with reference to FIGS. 39 to 44.
Shown in. This method is based on an equivalent circuit model, such as the source common FET common circuit model shown in FIG. Referring to FIG. 39A, step 1
A model is first generated at 22. The model shown in FIG. 8 is used as a small signal model of FET. According to an important aspect of this algorithm, the equivalent circuit parameters are based on the measured FET S-parameters. Measuring S-parameters for semiconductor devices is well known in the art. FIG. 42A shows 0.05 to 40
S-parameters S11, S12 and S22 measured at frequencies between GHz
2 is a Smith chart showing, as an example. FIG. 42B shows 0.05 to 40G.
6 represents a magnitude / angle chart of the S-parameter S21 measured at a frequency of Hz. After measuring the S-parameters as specified in step 124 (FIG. 39A), in step 126 it is checked whether the measurement is suitable. To do this, manually inspect the test results for anomalies or algorithmically determine the validity of the test set. If the measurement is appropriate, then in step 128 the measured value of the S-parameter is stored.

The space of the values of the trial start impedance points is selected, for example, as shown in Table 4. A direct model extraction algorithm known as the Minasian algorithm is then used to generate a temporary value of the equivalent circuit model parameter for each value of the starting feedback impedance. Such extraction algorithms are well known in the art and are described, for example, in "Broadband Determination of M. Berroth, et al.
The FET Small Equivalent Small Signal Circuit "(wideband judgment of FET small equivalent small signal circuit), IEEE-MTT , Vol. 38, No. 7 (July 1980). For each of the values, the model parameter values are determined, ie, referring to Figure 39A, each impedance point in Table 4 is
Processed by blocks 130, 132, etc., model parameter values are calculated for each of the impedance points to form an error metric. In addition, the error metric is used to create a unique small signal device model. This will be discussed below. The processing in each of the blocks 130 and 132 is similar. Therefore, only one block 130 will be discussed for the example impedance points shown in Table 4. In this example, an impedance point 17 is used that correlates with a source resistance R _s of 1.7Ω and a source inductance L _{s of} 0.0045 pH.

[0045]

[Table 4]

For the selected value R _s = 1.7Ω, the initial intrinsic equivalent circuit parameter and the initial parasitic equivalent circuit parameter are determined. For example, use the Minasian algorithm previously discussed and shown in Tables 5 and 6 as specified in steps 134 and 136. At step 138, the simulated circuit parameters are compared to the S-parameter measurements, for example as shown in FIGS. 43A and 43B. Each of processing blocks 130 and 132, etc., completes six cycles. Therefore, the system determines in step 140 whether the six cycles have been completed.

[0047]

[Table 5]

[0048]

[Table 6]

Each cycle of processing block 130 consists of direct extraction and subsequent optimization using a fixed number of optimization iterations, eg, 60. By fixing the number of extraction-optimization cycles together with the number of iterations of optimization, we define a fixed "distance" or computational time over which the model solution must be derived. Therefore, this algorithm incorporates a convergence rate requirement for the total error metric. On this occasion,
An environment in which each trial model solution competes with each other is set. To this end, it incorporates a "race" criterion by achieving the lowest fitting error for a fixed computation time. Here, “convergence speed” is set for each processing block 130, 132, etc.
Is implicitly calculated.

After the system determines in step 140 whether a race has taken place, the system proceeds to block 142 and optimizes the model parameters. Various commercial software programs are available. For example, LIBRA manufactured by HP-eesof
3.5 software can be used for both circuit simulation and optimization functions. The optimization is performed according to the constraints specified in Table 7, in addition to fixing the feedback resistance R _s to a fixed value.

[0051]

[Table 7]

By fixing the value of R _s , the segment of this algorithm constrains to get the trial model solution only for the starting trial feedback impedance point. Table 8 shows the intrinsic equivalent parameter values optimized using commercial software such as LIBRA 3.5. These values, along with the optimized parasitic values shown in Table 9, form the first optimized model solution for the first extraction-optimization cycle (i.e., one in six). The optimized model parameters are then fed back to function blocks 134 and 136 (FIG. 39A) and used for the new initial model solution. These values are compared with the S-parameter measurements shown in FIGS. 43A and 43B. The system repeats this cycle 6 times, as before.
After six extraction-optimization cycles, the final trial model solution for trial impedance point 17 is completed and its final fitting error for the measured data is obtained at the same time,
Create a new error metric 144. According to an important aspect, the extraction-optimization algorithm implicitly gives the final optimization fitting error at each point information about both the fitting error of the measured value to the model value and the convergence speed. To do this, we set fixed optimization time constraints and set up competing races between the various trial model solutions.

[0053]

[Table 8]

[0054]

[Table 9]

As shown generally in FIGS. 40 and 41, the implementation of the extraction optimization cycle at step 146 provides the best (and fastest) solving solution from all of the trial impedance points globally (for the final fitting error). Global) Minimum (g
Appears as a lobal minima). More specifically, referring to FIG. 40, a global minimum solution using the new error metric is determined near R _s = 1.7 ohms. Tables 10 and 11 summarize the final model equivalent circuit parameters for this global solution, including the intrinsic and parasitic parameters identified in step 148 (Fig. 39B).

[0056]

[Table 10]

[0057]

[Table 11]

To check the accuracy of the solution, the final model of the solution is compared to the S-parameter measurements, as shown in FIGS. 44A and 44B. As shown, there is a high correlation between the simulated model values and the S-parameter measurements, and the simulated model values provide a relatively accurate unique small-signal device model. It was confirmed to represent.

Obviously, many modifications and variations of the present invention are possible in light of the above teachings. Therefore, it will be appreciated that within the scope of the appended claims, the present invention may be practiced other than as specifically described above.

[Brief description of drawings]

FIG. 1 is a flow chart of a known MMIC yield reduction mechanism in a manufacturing process.

2A and 2B are noise figure simulations and cumulative yields for a 26 GHz MMIC using Monte Carlo and correlation statistical device models, respectively, with measured data shown as squares and Monte Monte. Carlo statistical data is shown by a circle, and the measured data shown in the figure is indicated by a broken line.

FIG. 3 is an example of a known mapping MMIC RF yield prediction method.

FIG. 4 is a schematic diagram of a 35GHZ GaAs pHEMT L using the method shown in FIG.
6 is a graph showing the relationship between measured noise figure and mapped noise figure for NA.

[Figure 5]   FIG. 5 shows an example of an S-parameter microscopic analysis according to the present invention.

[Figure 6]   FIG. 6 shows an example inner and outer regions of a HEMT device.

FIG. 7 is similar to FIG. 5, but shows the approximate location of the model element within the HEMT FET device shown in FIG.

[Figure 8]   FIG. 8 is a schematic diagram of a source common FET equivalent circuit model.

FIG. 9 is a diagram showing a specific application of the S-parameter microscope analysis shown in FIG.

10 is a diagram, similar to FIG. 5, demonstrating that known systems cannot accurately predict the internal charge and electric field structure of semiconductor devices.

FIG. 11 is a plan view of a 4-finger, 200 μm GaAs HEMT device.

FIG. 12 is a graph showing measured drain-source current I _ds as a function of drain-source voltage V _ds for the sample FET device shown in FIG. 11.

FIG. 13 is a graph showing drain-source current I _ds and transconductance G _m as a function of gate-source voltage Vgs for the sample FET device shown in FIG. 11.

FIG. 14 is a graph of 0.05 to 40.0 for the FET device shown in FIG.
3 is a Smith chart showing S11, S12, and S22 parameters measured at frequencies up to GHZ.

FIG. 15 is a diagram showing an example of the FET shown in FIG.
7 is a graph showing magnitude as a function of angle for S-parameter S21 at frequencies up to.

FIG. 16 shows an on-mesa shown as R _s as a functional bias in accordance with the present invention.
6 is a graph showing a charge control map of charge and electric field distribution in the source / access region.

FIG. 17 is a graph showing a charge control map of charge and electric field distribution in the on-mesa drain access region as R _d as a function of bias in accordance with the present invention.

FIG. 18 is a graph showing a charge control map for non-pseudo-quiescent majority carrier transport, shown as R _i as a function of bias, in accordance with the present invention.

FIG. 19 is a graph showing a charge control map for gate modulated charge and distribution under gate, shown in Cgs and Cgt as a function of bias, in accordance with the present invention.

FIG. 20 is a plan view of an example of a π-FET having two gate fingers.

FIG. 21 is a plan view of an example of a π-FET having four gate fingers.

FIG. 22   FIG. 22 is a diagram of a π-FET parasitic model according to the present invention.

FIG. 23 is a diagram of an off-mesa parasitic model for a π-FET according to the present invention.

FIG. 24 is a π-FE with four gate fingers as shown in FIG. 21.
FIG. 4 is a diagram of an interconnection and boundary parasitic model according to the present invention for T.

FIG. 25   FIG. 25 is a diagram of an inter-electrode parasitic model according to the present invention.

FIG. 26   FIG. 26 is a schematic diagram of the inter-electrode parasitic model shown in FIG.

FIG. 27   FIG. 27 is a diagram of an on-mesa parasitic model according to the present invention.

FIG. 28   FIG. 28 is a schematic diagram of the on-mesa parasitic model shown in FIG.

FIG. 29   FIG. 29 is a diagram of a unique model according to the present invention.

FIG. 30   FIG. 30 is a schematic diagram of the specific model shown in FIG.

FIG. 31A is an example of a device layout for a π-FET with four gate fingers. 31B is an equivalent circuit model of the π-FET shown in FIG. 31A.

FIG. 32 is an eigenmodel of a single finger unit device cell according to the present invention.

FIG. 33   FIG. 33 is similar to FIG. 32 and illustrates first level embedding according to the present invention.

FIG. 34   FIG. 34 is similar to FIG. 33 and shows second level embedding according to the present invention.

FIG. 35 is an equivalent circuit model of the π-FET shown in FIG. 31A according to the present invention.

FIG. 36   FIG. 36 is similar to FIG. 34 and shows a third level embedding according to the present invention.

FIG. 37   FIG. 37 is similar to FIG. 34 and shows a fourth level embedding according to the present invention.

FIG. 38   FIG. 38 is similar to FIG. 34 and shows a fifth level embedding according to the present invention.

39A and 39B show a parameter extraction modeling and part of the present invention.
It is a flow chart of an algorithm.

FIG. 40   FIG. 40 shows an error metric according to the present invention.

FIG. 41   FIG. 41 shows an error metric according to the present invention.

FIG. 42A is a Smith plot showing measured and initial model solutions for S-parameters S11, S12 and S22 at frequencies from 0.05 to 40.0.
It is a chart. FIG. 42B is a graph showing the angle-magnitude relationship for the initial modeled S-parameter S21 at frequencies of 0.05 to 40.0.

FIG. 43A shows S-parameters S11, S12 and S22 measured and simulated at frequencies of 0.05 to 40.0 in the first extraction optimization cycle.
Is a Smith chart showing. FIG. 43B shows the first model S-21 parameter measurements and the optimized first model S-21 at frequencies of 0.05 to 40.0 in the first extraction optimization cycle.
6 is a graph showing magnitude as a function of angle for parameters.

FIG. 44A shows the S− at frequencies of 0.05 to 40.0 for the final solution.
3 is a Smith chart showing the measurements as a function of the final model solution of the parameters S11, S12 and S22. FIG. 44B is a graph showing the magnitude as a function of angle for the S-parameter S21 of the final model solution at frequencies of 0.05 to 40.0.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE, TR), OA (BF , BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, G M, KE, LS, MW, MZ, SD, SL, SZ, TZ , UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, B Z, CA, CH, CN, CR, CU, CZ, DE, DK , DM, DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, J P, KE, KG, KP, KR, KZ, LC, LK, LR , LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, R O, RU, SD, SE, SG, SI, SK, SL, TJ , TM, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZW

Claims (10)

[Claims] 1. A method of determining internal charge and electric field in a semiconductor device, comprising: (a) measuring an S-parameter of the semiconductor device; and (b) generating a charge control map of the semiconductor device. And, including. 2. The method of claim 1, wherein the semiconductor device is a field effect transistor (FET) and step (a) comprises varying gate voltages Vgs.
At, measuring the drain-source current Ids as a function of the drain-source voltage Vds. 3. The method of claim 2, wherein step (a) comprises measuring the S-parameter over a predetermined frequency range for each of the gate voltages. 4. The method of claim 3, wherein step (b) includes the step of extracting a small signal equivalent circuit value for each S-parameter at each gate voltage. 5. The method of claim 4, further comprising: (d) generating an embedded model. 6. The method of claim 5, wherein the embedded model is used to filter the extracted values to obtain a charge control map. 7. The method of claim 6, wherein the embedded model is PiF.
A method that is an ET model. 8. The method of claim 7, wherein the PiFET model is used to subtract a predetermined capacitive contribution. 9. The method according to claim 8, wherein the PiFET model is used to subtract the capacitive contribution due to the influence of interelectrode parasitics. 10. The method of claim 9, wherein the PiFET model is used to subtract capacitive contributions due to the effects of off-mesa parasitics.