KR20020089608A - Static random access memory device capable of reducing power consumption - Google Patents

Abstract

PURPOSE: A static random access memory device for reducing power consumption is provided to reduce power consumption by minimizing the amount of discharge current of a plurality of bit lines to a plurality of memory cells. CONSTITUTION: A memory cell array(100) is formed with a plurality of memory cells(MC). The memory cells(MC) of each row are commonly connected with corresponding word lines(WL0 to WLi). The memory cells(MC) of each column are connected in parallel between corresponding bit line couples(BLO to BLj,BL0B to BLjB). Each memory cell(MC) has a structure of an SRAM cell. A row selection circuit(120) is used for selecting one of the word lines(WL0 to WLi) in response to row address information. A column selection circuit(140) is used for some of bit line couples(BLO to BLj,BL0B to BLjB) in response to column address information. The selected bit line couples are connected with a sense amplifier and write circuit(160). A bit line precharge circuit(180) is used for applying a precharge voltage to the bit line couples(BLO to BLj,BL0B to BLjB) in response to a bit line precharge signal(PRECLK). A regulator circuit(200) is used for controlling a supply voltage(VDD) and applying the precharge voltage to the bit line precharge circuit(180).

Description

STATIC RANDOM ACCESS MEMORY DEVICE CAPABLE OF REDUCING POWER CONSUMPTION}

The present invention relates to a semiconductor memory device, and more particularly, to a random access memory device capable of reducing power consumption.

In order to reduce the power consumption of semiconductor memory devices, in general, techniques for lowering the operating voltage of a single semiconductor memory device (or chip) or the operating voltage of a memory module inside the chip have been proposed. As the operating voltage is lowered, there is a problem in the interface between the semiconductor memory device and the external system and a problem due to the internal low voltage. The problem with interfacing external systems is that they require a separate regulator or interface circuit due to the difference in operating voltages between the memory device and the external system. Further implementation of such interface circuits causes an increase in area and power consumption. Problems due to internal low voltages are caused by processes and designs, which are caused by low threshold voltages caused by operating internal devices at low voltages, resulting in sub-dress leakage currents and reduced breakdown voltages. The reliability decreases and the stability decreases due to the weakening of the noise characteristics.

In order to improve the power consumption of a memory device, therefore, research has focused on reducing the power consumption of the memory itself instead of the method of lowering the operating voltage due to the above-mentioned problems. To reduce the power consumption of the memory device itself to date, methods for improving the amplifier structure of the memory output stage, using a low voltage swing bus, using a multi-divided module, memory How to reduce the area, and so on. In addition, a method of increasing the operation speed by reducing the bit line capacitance by disposing an output terminal of the memory data on both sides has been proposed.

Various techniques to reduce power consumption when precharging bit lines are provided in U.S. Patent No. 4,972,373 entitled "PRECHARGE SYSTEM IN A SRAM" (assigned to Samsung Semiconductor & Telecommunications Co., Ltd.), U.S. Patent No. 5,047,984 entitled "INTERNAL SYNCHRONOUS STATIC RAM" (assigned to NEC corporation), U.S. Patent No. 5,677,889, entitled "STATIC TYPE SEMICONDUCTOR DEVICE OPERABLE AT A LOW VOLTAGE WITH SMALL POWER CONSUMPTION" (assigned to Mitsubishi Denki Kabushiki Kaisha).

6 is a block diagram illustrating a semiconductor memory device according to the prior art. The semiconductor memory device is provided with a memory cell array 10, which is composed of memory cells MC arranged in rows and columns. The memory cells MC of each row are commonly connected to the corresponding word line WLm (m = 0-i). The memory cells MC in each column are arranged in parallel between the corresponding pair of bit lines BLn and BLnB (n = 0-j). Each memory cell is composed of, for example, a static random access memory cell consisting of six transistors, as shown in FIG. In Fig. 7, three signal lines, that is, bit lines BL and 2, complementary bit lines BLB and 3 and word lines 4 are connected to the memory cell. Two input transistors 6, 7 are controlled by word line 4 and are connected to bit lines 2, 3, respectively.

Referring again to FIG. 6, one of the word lines WLm is selected by the row select circuit 20 that operates in response to a row address. The bit line pairs BLn and BLnB are connected to the column select circuit 30, and in the write / read operation, some bit line pairs are selected by the column select circuit 30 according to the column address. The bit line pairs BL0, BL0B-BLj, BLjB so selected are connected to the sense amplification and writing circuit 40 via corresponding data line pairs. It is apparent to those skilled in the art that the sense amplification and writing circuit 40 is comprised of sense amplifiers and write drivers corresponding respectively to pairs of data lines.

A bit line precharge circuit 50 is connected to the bit line pairs BL0 and BL0B to BLj and BLjB, and the bit line precharge circuit 50 includes three PMOS transistors MP1, MP2 and MP3) are arranged. The PMOS transistors MP1 and MP2 have current paths respectively formed between the bit voltages BLn and BLnB corresponding to the power supply voltage. The PMOS transistor MP3 has a current path formed between the bit lines BLn and BLnB. The PMOS transistors MP1, MP2, and MP3 are commonly controlled to the bit line precharge signal PRECLK. That is, the PMOS transistors MP1, MP2, and MP3 are turned on / off at the same time according to the voltage level of the bit line precharge signal PRECLK.

In general, the power consumption of a memory cell array block accounts for about 85% of the power consumption of the entire chip. These causes are as follows. All bit line pairs BLn and BLnB are precharged by the bit line precharge circuit 50 using the power supply voltage VDD, whether or not it is selected. When the word line is selected, current on the precharged bit lines flows through current paths formed in the memory cell direction of the selected word line. At this time, in the state in which all the bit lines are precharged, the dynamic current (or discharge current) is generated in the direction of the memory cell at the power supply voltage VDD every clock cycle to consume power. This is because the PMOS transistors MP1, MP2, and MP3 constituting the bit line precharge circuit 50 are controlled by the bit line precharge signal PRECLK synchronized with the clock. Therefore, while the bit line precharge signal PRECLK is kept at a low level, a discharge current is generated, which causes power consumption.

An object of the present invention is to provide a semiconductor memory device capable of reducing the discharge current flowing from the bit line toward the memory cell.

1 is a block diagram showing a semiconductor memory device according to the present invention;

FIG. 2 is a cross-sectional view illustrating a cut-off voltage of the depletion type NMOS transistor illustrated in FIG. 1;

3 shows the average operating current consumption for a cut-off voltage;

4A to 4D are operation timing diagrams for explaining a read operation of the semiconductor memory device according to the present invention;

4E is a waveform diagram showing a bit line precharge current according to the prior art;

5 shows average operating current consumption according to the number of memory cells per pair of bit lines in the prior art and the present invention;

6 is a block diagram showing a semiconductor memory device according to the prior art; And

FIG. 7 is a circuit diagram illustrating the SRAM cell illustrated in FIG. 6.

Explanation of symbols on the main parts of the drawings

10, 100: memory cell array 20, 120: row selection circuit

30, 140: column selection circuit 40, 160: sense amplification and writing circuit

50, 180: bit line precharge circuit 200: regulator circuit

(Configuration)

According to a feature of the present invention for achieving the above object, a static random access memory device includes an array of memory cells arranged in rows and columns. Memory cells corresponding to each column are connected in parallel between each pair of bit lines, and memory cells corresponding to each row are arranged in corresponding word lines, respectively. A bit line precharge circuit is connected to the bit line pairs, and the bit line precharge circuit charges the bit line pairs to a predetermined precharge voltage in response to a bit line precharge signal. A regulator circuit is connected between the bit line precharge circuit and a power supply voltage, and the regulator circuit regulates the power supply voltage to supply the precharge voltage lower than the power supply voltage to the bit line precharge circuit.

In this embodiment, the regulator circuit is composed of depletion NMOS transistors corresponding to the pair of bit lines, each transistor being grounded with a current path formed between the power supply voltage and the bit line precharge circuit. Has a gate.

In this embodiment, the precharge voltage is a cut-off voltage of the depletion NMOS transistor.

(Action)

With this arrangement, the bit lines are charged to a voltage lower than the supply voltage.

(Example)

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a semiconductor memory device according to the present invention. The semiconductor memory device of the present invention is a static random access memory device (hereinafter referred to as " SRAM ") and includes a memory cell array 100 for storing data information. The memory cell array 100 includes a plurality of memory cells MC arranged in a matrix of rows and columns. Specifically, the memory cells MC of each row are commonly connected to the corresponding word line WLm (m = 0-i). The memory cells MC in each column are arranged in parallel between the corresponding pair of bit lines BLn and BLnB (n = 0-j). Each memory cell MC has, for example, an SRAM cell structure shown in FIG.

The row select circuit 120 is connected to the word lines WLm and selects any one of the word lines WL0-WLi in response to row address information. A column select circuit 140 is connected to one side of the bit line pairs BLO and BL0B to BLj and BLjB, and the column select circuit 140 selects some of the bit line pairs in response to column address information. . The bit line pairs so selected are connected to the sense amplification and writing circuit 160 via corresponding data line pairs. It is apparent to those of ordinary skill in the art that the sense amplification and writing circuit 160 consists of sense amplifiers and write drivers respectively coupled to data line pairs.

A bit line precharge circuit 180 is connected to the other side of the bit line pairs BLO and BL0B to BLj and BLjB, and the precharge circuit 180 controls all bits in response to the bit line precharge signal PRECLK. Line pairs (BLO, BL0B)-(BLj, BLjB) charge the precharge voltage. Here, the bit line precharge signal PRECLK is a signal synchronized with a clock signal. In the bit line precharge circuit 180, three PMOS transistors are arranged per pair of bit lines. For example, in the bit line pair BL0, BL0B, the PMOS transistors MP10, MP12 are the current paths and the bit formed between the regulator circuit 200 and the corresponding bit lines BL0, BL0B, respectively. It has gates connected to the line precharge signal PRECLK. The PMOS transistor MP14 has a current path formed between the bit lines BL0 and BL0B and a gate connected to the bit line precharge signal PRECLK.

The regulator circuit 200 is connected between a power supply voltage VDD and a bit line precharge circuit 180, and adjusts the power supply voltage VDD to bit-preset the precharge voltage lower than the power supply voltage VDD. Supply to charge circuit 180. The regulator circuit 200 is to reduce the dynamic current or discharge current flowing from the bit line toward the memory cell by lowering the voltage necessary to precharge the bit line to the power supply voltage. The regulator circuit 200 is composed of a plurality of depletion NMOS transistors DMN2, DMN4,..., DMN6, DMN8. For example, the depletion type NMOS transistor DMN2 has a current path formed between the power supply voltage VDD and the bit line precharge circuit 180, the gate of which is grounded.

According to the regulator circuit 200, the voltage for precharging the bit line, that is, the precharge voltage, becomes the cut-off voltage of the depletion type NMOS transistor. Referring to FIG. 2, which shows a cross-sectional view of a depletion type NMOS transistor, when the drain voltage is the supply voltage VDD (eg, 3.3V), the gate voltage is 0V, and the source is floating, the source is a depletion NMOS. It is at the cut-off voltage (Vcut-off) of the transistor. For this reason, the bit line voltage is adjusted to a cut-off voltage Vcut-off lower than the power supply voltage VDD. The cut-off voltage of the depletion type NMOS transistor is determined by the concentration of the depletion layer. For example, the higher the concentration of the depletion layer, the larger the cut-off voltage, and the lower the concentration of the depletion layer, the lower the cut-off voltage. The larger the cut-off voltage, the lower the bit line voltage drop. The lower the cut-off voltage, the larger the bit line voltage drop.

FIG. 3 showing the average operating current change with the cut-off voltage Vcut-off is measured under an operating temperature of 25 ° C., an operating frequency of 33 MHz and an operating voltage of 3.3 V. FIG. The lower the cut-off voltage Vcut-off of the depletion type NMOS transistor is, the lower the average operating current is, as shown in FIG. 3. This means that as the cut-off voltage or the bit line precharge voltage decreases, the discharge current flowing from the bit line toward the memory cell decreases. That is, power consumption due to the discharge current is reduced.

The bit line pairs BLn and BLnB are made by the bit line precharge circuit 180 using the cut-off voltage (about 2.2V) regulated by the regulator circuit 200, as shown in FIG. 4B. . Then, as the word line is selected (see FIG. 4A), each pair of bit lines BLn and BLnB is developed according to the data stored in the memory cell. Data of the selected memory cells is sensed by the column select circuit 140 via the selected bit line pairs and the sense amplifiers of the sense amplification and writing circuit (see FIG. 4C).

Compared with the conventional technique of precharging the bit line pairs BLn and BLnB to a power supply voltage (about 3.3 V), as shown in FIGS. 4D and 4E, in the present invention, the direction of the memory cell in the bit line is shown. It can be seen that the current flowing to the wall is reduced.

Figure 5 shows the bit line power consumption for the number of memory cells. The bit line power consumption for the number of memory cells is measured under an operating temperature of 25 ° C, an operating frequency of 33 MHz and an operating voltage of 3.3V. As the number of memory cells connected between the bit lines increases, the current consumption increases drastically in the prior art, while the current consumption slowly increases in the present invention.

In the above, the configuration and operation of the circuit according to the present invention has been shown in accordance with the above description and drawings, but this is only an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, by adjusting the voltage for precharging the bit line lower than the power supply voltage, the current flowing from the bit line to the memory cell direction is reduced, and power consumption is reduced.

Claims (8)

An array of memory cells arranged in rows and columns; Memory cells corresponding to each column are connected in parallel between each pair of bit lines and memory cells corresponding to each row are respectively arranged in corresponding word lines; A bit line precharge circuit connected to the bit line pairs and charging the bit line pairs to a predetermined precharge voltage in response to a bit line precharge signal; And And a regulator circuit coupled between the bit line precharge circuit and a power supply voltage, the regulator circuit configured to supply the precharge voltage lower than the power supply voltage to the bit line precharge circuit by adjusting the power supply voltage. The method of claim 1, The regulator circuit is composed of depletion NMOS transistors corresponding to the pair of bit lines, each transistor having a current path and a grounded gate formed between the power supply voltage and the bit line precharge circuit. . The method of claim 1, The precharge voltage is a cut-off voltage of the depletion type NMOS transistor. The method of claim 1, Wherein each memory cell is a static random access memory cell. An array of memory cells arranged in rows and columns; A row selection circuit for selecting any one of the rows in response to a row address; A column selection circuit for selecting some of the columns in response to a column address; A bit line precharge circuit coupled to said columns and charging said columns to a predetermined precharge voltage in response to a precharge signal; And And means for regulating the power supply voltage to supply the bit line precharge circuit such that the precharge voltage is lower than the power supply voltage and connected between a power supply voltage and the bit line precharge circuit. The method of claim 5, And each of the memory cells is composed of a static random access memory cell. The method of claim 5, The means for supplying the precharge voltage consists of a depletion type NMOS transistor corresponding to each of the columns, the depletion type NMOS transistor having a current path formed between the power supply voltage and the bit line precharge circuit and a grounded gate. Random access memory device. The method of claim 7, wherein And the precharge voltage is a cut-off voltage of the depletion type NMOS transistor.