KR20020081248A - A system and method for sending and receiving data signals over a clock signal line - Google Patents

Abstract

The system of the present invention includes a unique transmission device for transmitting clock and data signals over the same transmission line. The receiver sends the data signal back to the transmitter using the same transmission line. The transmitter includes a clock generator, a decoder and a line interface. The clock generator generates a clock signal including a falling edge of a variable position. The position of the falling edge is decoded by the receiver to extract data from the clock signal. The receiver includes a clock regenerator, a data decoder and a return channel encoder. The clock reproduction growth value monitors the transmission line, receives and filters the signals, and generates a clock signal of the receiving device from the signal on the transmission line. The return channel encoder generates signals and loads them on the transmission line. The signal is carried or superimposed on the clock and data signals provided by the transmitter.

Description

System and method for transmitting and receiving data signal through clock signal line {A SYSTEM AND METHOD FOR SENDING AND RECEIVING DATA SIGNALS OVER A CLOCK SIGNAL LINE}

Conventional systems and methods for data transmission between a transmitter and a receiver are various. Various serial links and other methods for transmitting data signals and clock signals are already well known. However, many of these systems and methods provide a single line or channel dedicated to clock signals and other signal transmissions or channels dedicated to data transmission. Such a system is described by Dong-Gyu Kim, Seong-Jun Ahn, Ki-Jung Ahn and Jeong-Duk Kyun, "A CMOS Serial Link For Fully Duplexed Data Communication" (IEEE Journal of Solid State Circuits, Vol. 30, No. 4, pp. 353-364, 1995, April).

Although the present invention will be described within the TMDS art, those skilled in the art will recognize that the present invention may be applied to other various data communication fields. In TMDS, four signal lines are provided, each of which is preferably a differential pair. One of the four signal lines is for a low speed clock signal, and the other three signal lines are for high speed data transmission.

One important point in any data communication system is to maximize the bandwidth provided by the data channels. However, most systems maintain synchronization between the transmitter and the receiver by including various control signals necessarily transmitted between the transmitter and the receiver to ensure proper operation. For example, in serial communications, about 20% of the bandwidth is typically used for framing and synchronization. One problem is that the bandwidth available for data transmission is reduced because the data signal line has to be used to transmit control signals between the transmitter and receiver. Another problem is the latency in transmitting control signals to the receiving side. In particular, in the transmission of video data, the majority of data must be transmitted in block units, and control signals cannot be transmitted while data is transmitted. For example, when data is transmitted from the control device to the flat panel, the data enable period corresponding to the blanking period in the CRT display used to transmit the control and synchronization signals after the data is transmitted ( data enable period). Only during this data enable period can control signals be transmitted under most protocols. Therefore, there is a waiting time for transmitting the control signals to the receiving device. Therefore, there is a need for a system that can provide control signal processing between a transmitting device and a receiving device while reducing the latency in transmitting control signals while not reducing the bandwidth available for data transmission.

Another problem with the prior art is that most systems do not provide a mechanism to send a signal back from the receiver to the transmitter. That is, there is no return channel for communication. Some systems provide additional signal lines, but the addition of such signal lines and the interface therefor introduces other problems that complicate the system, add physical lines that require redistribution and are inoperable. Another method is to add a second transmitter, a second receiver and signal lines. However, in order to use this method, since the original hardware equipment must be installed twice, there is a problem that it is too expensive. In addition, this doubled hardware configuration is unnecessarily excessive compared to the amount of data that must be transmitted between the transmitter and receiver, and in particular, video data from the transmitter to the receiver, such as communication between the graphics controller and the video display, can be lost. Too much for application to transfer.

Therefore, there is a need for a system and method for transmitting data signals between a transmitter and a receiver using a clock signal line.

Inventors: Kyu Dong Kim, Min Kyu Kim and Seung Ho Hwang

Cross-reference of related application

The present application is filed on September 9, 1999, US Patent No. 09 / 393,235 (Name: Apparatus and method for transmitting and receiving data signals over a clock signal line {System and Method for sending and receiving data signals over a clock signal line} Is part of the application. The above-mentioned US application was referred to in this specification as a utility model change of US Patent No. 60 / 099,770 (name: Embedded Back Channel For TMDS) filed by Kim Dong-kyu on September 10, 1998.

The present invention relates to the field of data communications, and more particularly, to the transmission of clock signals and data signals. In particular, the present invention relates to the transmission of clock and data signals over the same transmission line in a transition minimized differential signaling system (TMDS) system.

1 is a block diagram of a system including a combined clock and data signal line of the present invention;

2 is a block diagram of a transmitter portion showing a clock generator, a decoder and a line interface;

Fig. 3 is a block diagram showing a preferred embodiment of the clock generating apparatus constructed by the present invention.

4 is a timing diagram showing various clock signals generated by the clock generator of the present invention;

Fig. 5A is a block diagram showing a preferred embodiment of the line interface constructed by the present invention;

Fig. 5B is a circuit diagram showing a preferred embodiment of the line interface constituted by the present invention;

Fig. 6A is a block diagram showing the first embodiment of the transmitter-side decoder constructed in accordance with the present invention;

Fig. 6B is a block diagram showing a second embodiment of the transmitter-side decoder constructed in accordance with the present invention;

Fig. 7 is a block diagram showing a first embodiment of the receiver portion related to the present invention;

Fig. 8 is a block diagram showing the first embodiment of the clock regeneration device of the receiving device of the present invention;

9 is a block diagram showing a preferred embodiment of the data decoder of the receiving device of the present invention;

Fig. 10A is a block diagram showing a first embodiment of a return channel encoder of the receiving device of the present invention;

Fig. 10B is a block diagram showing a second and alternative embodiment of the return channel encoder of the receiving device of the present invention;

11A is a timing diagram showing signals on a transmission line for a return to zero (RZ) signaling scheme and clock and data signals generated by the transmission apparatus;

FIG. 11B is a timing diagram showing signals on a transmission line for the RZ signaling method, data signals transmitted by the receiver, and clock and data signals recovered by the receiver; FIG.

12A is a timing diagram showing signals on a transmission line for a non-return to zero (NRZ) signaling scheme and clock and data signals generated by the transmission apparatus;

Fig. 12B is a timing diagram showing signals on a transmission line for NRZ signaling, data signals transmitted by the receiving apparatus, and clock and data signals recovered by the receiving apparatus;

The present invention overcomes the disadvantages and limitations of the prior art with a unique data communication system. The system of the present invention includes a unique transmitter and receiver connected by a transmission line. The transmitter transmits both a clock signal and a data signal to the receiver through the transmission line. The receiving device transmits the data signal back to the transmitting device using the same transmission line.

The transmitter preferably comprises a clock generator, a decoder and a line interface. The clock generator generates a clock signal including a variable position falling edge. The position of the falling edge is decoded by the receiving device to extract data along with a clock signal. The line interface connects the output of the clock generator with the transmission line. The line interface also removes signals from the clock generator by connecting the transmission line to the decoder. The decoder receives and decodes a signal from the line interface to determine the data transmitted from the receiver to the transmitter via the same transmission line used to send clock and data from the transmitter to the receiver.

The receiving device preferably comprises a line interface and a clock regenerating device, a data decoder and a return channel encoder. The clock regenerator, data decoder and return channel encoder are connected to the transmission line by the line interface. The clock reproduction growth value monitors the transmission line, receives and filters the signals, and generates a clock signal from the signal on the transmission line at the receiving device. The data decoder is coupled to receive the signals on the transmission line to filter and decode these signals to produce data signals. This operation is preferably performed by determining the position of the falling edge of the clock signal and converting the position of the falling edge into bit values. In contrast, the return channel encoder generates signals and places them on the transmission line. These signals appear or overlap on clock and data signals provided by the transmitter.

Features and advantages of the present invention will be understood by the preferred embodiments of the present invention described below. Preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 shows a block diagram of a system 100 that includes the combined clock and data signal lines of the present invention. Preferably, the system 100 includes a transmitter 102, a clock transmission line 104, a receiver 106 and one or more data transmission lines 108. The transmitter 102 provides a clock signal as well as data signals to the receiver 106 via a clock transmission line 104. These data signals are added to the signals provided to the receiving device 106 via the high speed data transmission line 108. The receiver 106 receives signals on the transmission line 104 and generates clock and data signals from the signals to the receiver 106. The data signals on the clock transmission line 104 are again added to the data signals recovered by the receiving device 106 from the data transmission line 108. Transmitter 102 and receiver 106 include logic for transmitting and receiving data from data transmission line 108. This logic performs transition control, DC balancing, encoding / decoding in the usual way. For example, in addition to the components of the present invention for receiving and transmitting data and clock signals on a clock transmission line 104 to be described below, the transmitter 102 and receiver 106 are respectively silicon of Cupertino, California. It has a common data transfer logic for TMDS as provided by PanelLink in Image. For easier understanding, the logic and data transmission line 108 is omitted in the following description and drawings. Although shown as a single line, the clock transmission line 104 and the data transmission line 108 are each differential pairs of signal lines, and it is common knowledge in the art that a signal is transmitted on this differential pair of signal lines. Those who have will understand. Also, those skilled in the art will understand that the preferred embodiment for data transmission line 108 is three pairs of data lines.

Transmission

2 shows in more detail the preferred embodiment of the transmission device 102. The transmitter 102 includes a clock generator 200, a line interface 204, and a decoder 202.

The clock generator 200 has a first input, a second input, and an output. The clock generator 200 generates a clock signal encoded with data. The data is encoded into the clock signal by changing the modulation of the falling edge of the clock signal. That is, the position of the falling edge of the clock relative to the rising edge of the clock represents different data values. This is particularly advantageous because it preserves the rising edge of the clock for clock recovery. All activity for the bidirectional data link on clock transmission line 104 is concentrated on the falling edge of the clock from transmitter 102. Most of the invention will be described with respect to the falling edge of a clock having two different positions, while FIGS. 3 and 4 will be described with respect to the falling edge of a clock having five different positions. Each of the four positions among the five positions represents two bit values, and one position does not represent data. The first input of clock generator 200 is connected to line 214 to receive a clock signal from any other portion of transmitter 102 or from an oscillator or other conventional clock source. A second input of clock generator 200 is connected to line 216 to receive control / data signals. These control / data signals may or may not indicate data to be transmitted as part of the clock signal. The control / data signals are output from other portions of the transmitter 102 or from off chip control logic. The output of the clock generator 200 is provided on a line 210 connected to the input of the line interface 204. The output of the clock generator 200 provides a CGOut signal.

In the present invention, it is described that preserving the rising edge for the clock signal and performing all the bidirectional data transmissions is performed on the falling edge, but the opposite is that the falling edge is preserved for clock recovery and the change in the position of the rising edge is used for data encoding. Those skilled in the art will understand that the configuration is within the spirit and scope of the present invention.

Line interface 204 has input and output and bidirectional ports. The line interface 204 connects the clock generator 200 and the decoder 202 with the clock transmission line 104. An input of the line interface 204 connects the line 210 with the clock transmission line 104 to the CGOut. The signal appears on clock transmission line 104. The output of line interface 204 is connected to decoder 202 by line 212. Line interface 204 receives the signal on clock transmission line 104, removes the CGOut signal as described below with reference to FIGS. 5A and 5B, and transmits this filtered signal as an input to decoder 202. The bidirectional port of the line interface 204 is connected to the clock transmission line 104.

The decoder 202 receives and decodes the filtered signal from the transmission line 104 to generate data transmitted by the receiving device 106. The decoder 202 performs a function opposite to that of the encoder 704 (see Fig. 7) of the receiving device 106 as described later.

3 and 4 illustrate a preferred embodiment of the clock generator 200. As shown in FIG. It will be described that the clock generator 200 provides a clock signal having a falling edge having five possible positions to transmit two bits of data together with the clock signal or to transmit the clock signal without data, but it is conventional in the art. Those who have knowledge of will recognize that this is just one example. The clock generator 200 may be configured to transmit 1 to n bits of data per clock period according to the clock frequency and the number of possible positions of the falling edge of the clock signal. In general, the n positions of the falling edge cause a maximum of log ₂ n bits of data to be transmitted per clock period. The number of positions for the falling edge is such that the pulse width at the first position is greater than the logic-threshold crossing time of the rising edge (jitter due to the phase-locked loop at the receiver 106). May be considered). That is, a threshold for setup and hold time in logic must be sufficient to recognize the rising edge as the beginning of the clock cycle.

The clock generator 200 generates a clock signal having a dot clock frequency or a frequency used by an apparatus (not shown) connected to the receiver 106 for displaying data. The maximum symbol rate provided by the data transfer as part of the clock signal is equal to the dot clock frequency. For example, if the dot clock is 100 MHz, the symbol rate is 100 Msymbols / s. The actual data rate depends on the modulation method and the number of bits per symbol or clock that can be transmitted. When simple binary modulation is used, the bit rate is equal to the clock rate and provides additional 100 Mb / s for control signals.

Referring to FIG. 3, the clock generator 200 includes a monoviable multivibrator 306, a delayed synchronization loop 300, a multiplexer 302, a first NAND gate 304, and a second NAND gate 306. It includes. The clock generator 200 uses only a return to zero (RZ) signaling method for transmitting clock and data signals. NRZ (non-return to zero) signaling cannot be used for transmission from the transmitter 102. The clock signal is received via line 214 and provided as an input to a one-shot or single state multivibrator 306. The single state multivibrator 306 generates a signal having a pulse width narrower than that of the clock signal. This is advantageous for use in other parts of the clock generator 200. In another embodiment, the monostable multivibrator 306 may be replaced with a plurality of single-state multivibrators each connected in series with the output signal line 308 of the delay synchronization loop 300. This embodiment provides more flexibility in the design of delayed synchronization loop 300 by means of additional single-state multivibrators, as will be appreciated by those skilled in the art. Of the single state multivibrator 306 The output is connected to the input of the delay synchronization loop 300. The delay lock loop 300 is of a general type and provides a plurality of outputs in response to an input signal. Each output is identical to its input, with only a phase shift. The falling edge of the CGOut signal is modulated by the delay synchronization loop 300. The falling edge of the CGOut signal is selected from one of the phases provided by the delay synchronization loop 300. The phases selected from the delay locked loop 300 are preferably close to a 50% duty cycle. The delayed synchronization loop 300 provides five output signals, namely,? 0,? 1,? 2,? 3,? 4, and? N. The signal φ 0 is output as it is output from the monostable multivibrator 306. It is a signal. Each of the? 1,? 2,? 3,? 4, and? n signals is a phase shifted signal with respect to the previous? signal. The signal? 0 is applied to the first input of the first NAND gate 304. The output of the first NAND gate 304 is provided on line 210 as a CGOut signal. The first NAND gate 304 is cross-connected with the second NAND gate 306 to form a set-reset latch. The rising edge of the clock generating the falling edge on the signal and the? 0 signal causes the output of the first NAND gate 304 to be set high or appear. The remaining signals φ1, φ2, φ3, φ4, and φn from the delay synchronization loop 300 are applied to the data inputs of the multiplexer 302, respectively. The control input of multiplexer 302 is connected to line 216 to receive control / data signals. In response to the control / data signals on line 216, multiplexer 302 selects one of? 1,? 2,? 3,? 4, and? N signals from delayed synchronization loop 300 to select second NAND gate 306. Applies to the input. Accordingly, the falling edge of the selected signal among the delayed synchronization loop 300, φ1, φ2, φ3, φ4, and φn signals resets the latch and the falling edge of the output of the first NAND gate 304 and the line 210. Create Therefore, it can be seen that the position of the falling edge can be selected using the control / data signals for selecting one of the signals. For example, control signals as shown in Table 1 below can be used to control the position of the falling edge.

Control / Data Signals (216) Input of NAND Gate 306 Lower edge location Transmission data 000 φ1 T0 00 001 φ2 T1 01 100 φ3 T2 00 010 φ4 T3 10 011 φn T4 11

Those skilled in the art will understand how the clock generator 200 can be modified to generate different falling edge locations for the CGOut signal. Fig. 4 shows a timing diagram of signals? 0,? 1,? 2,? 3,? 4, and? N and possible CGOut signals. There are five possible CGOut signals. First, the clock signal has a falling edge at time T2 and does not transmit data. The remaining CGOut1 to CGOut4 signals have falling edges at T0, T1, T3, and T4, respectively, and each falling edge represents a different 2-bit value. Thus, the preferred embodiment can transmit two bits per clock from the transmitter 102 to the receiver 106 in addition to the clock signal. Since the receiving device 106 only uses rising edges to detect and define the clock period, the present invention uses this system to transmit data without any performance penalty. The clock generator 200 outputs the falling edges at times T2 and T3 for the receiver 106 to be described below in which only one bit data is transmitted per clock.

The ability of the present invention to utilize the clock transmission line 104 to transfer data from the transmitter 102 to the receiver 106 is particularly advantageous since the signal latency present in the prior art can be eliminated. According to the present invention as applied to the TMDS, the transmitter 102 does not have to wait for the low period of the next data enable DE available to transmit the signals. This greatly reduces the maximum transmission latency. The present invention can also be used for other serial links that require very short latency. For example, if a fixed bit position is assigned to each link (a fixed bandwidth for a fixed dot clock), synchronization overhead for the channels can be minimized. In this way, the latency of the links can be reduced to one frame period and cable flight time. Other bits of the payload may be used with variable bandwidth but may have a longer synchronization latency or delay.

Another advantage of the forward channel for transmitting data from the transmitter 102 to the receiver 106 is that it can be fully compatible with conventional TMDS designs and protocols. Thus, whether or not the receiving device 106 can receive data from the transmitting device 102, the clock signal is not affected by the addition of data. Further, the receiver 106 does not have a problem of recovering the clock even if data (data for the transmitter 102 or the receiver 106) is added to the signal on the transmission line 104 according to the present invention. Therefore, the transmitting device 102 of the present invention can still be used even if the receiving device does not have the capability to receive the data signal.

5A and 5B show a preferred embodiment of the line interface 204. The line interface includes a first amplifier 502 and a second amplifier 506, a differential amplifier 504 and a line terminator or pullup resistor 508. The line interface 204 is essentially a bidirectional bridge that allows the transmission of data while receiving data from the receiver 106. An input of the first amplifier 502 is connected to the line 210 to receive a CGOut signal. The output of the second amplifier 506 is connected to the clock transmission line 104 to apply an amplified CGOut signal. Clock transmission line 104 is connected to a high voltage by pull-up resistor 508 to form a line terminator. Pull-up resistor 508 may be connected to ground or 1/2 V _DD as would be understood by one of ordinary skill in the art for other embodiments of line terminators. The clock transmission line 104 is also connected to the input of the differential amplifier 504. The other input of the differential amplifier 504 is connected to the output of the second amplifier 506. The second amplifier 506 receives and amplifies the CGOut signal, which is amplified to the same or lower level than the first amplifier 502. The differential amplifier 504 extracts the CGOut signal from the signal received from the clock transmission line 104. Thus, the output of the differential amplifier 504 provided on the line 212 mainly includes signals that appear on the clock transmission line 104 by the receiver 106 and does not include the CGOut signal. It should be noted that the same circuitry with differently connected inputs and outputs may be used in the receiver 106 as described below with reference to FIG.

5B shows a circuit diagram of one exemplary embodiment of a line interface 204. For the sake of clarity and understanding, the connections to the signal lines 210 and 104 are shown with reference numerals. As will be appreciated by one of ordinary skill in the art, the signals utilize differential pairs denoted by the references "a" and "b". As will be appreciated by one of ordinary skill in the art, the transistors and other components that make up the second amplifier 506 and the differential amplifier 504 are grouped in boxes of dashed lines. The remaining transistors and other components constituting the first amplifier are not indicated by reference numerals. It should be noted that some transistors of the second amplifier 506 are for impedance matching, the gates of which are connected to the signal line 522 and are biased for impedance matching in a conventional manner. Several transistors of the differential amplifier 504 are also connected to the line 520 for biasing. In other embodiments, the outputs of the differential amplifier 504 may be connected to the line 520 to provide a single output signal, as will be understood by one of ordinary skill in the art. Furthermore, one of ordinary skill in the art will appreciate that in other embodiments various other conventional bidirectional buffers may be used in place of the circuits shown in FIGS. 5A and 5B.

6A and 6B show two different embodiments of the decoder 202. This embodiment of the decoder 202 is used by the encoder 704 (see FIG. 7) of the receiving device 106. As shown in FIG. Depends on the type of signal. Fig. 6A is a block diagram showing the first embodiment of the decoder 202a in the transmitting device 102 used when the receiving device 106 transmits data in the NRZ manner. As shown in Fig. 6A, when the receiving device 106 transmits data in the NRZ manner and toggles the data at the false falling edge (since the clock arbitrarily toggles the falling edge according to the present invention), the delay is at the transmitting device side. Since the relative position of the data transition is apparent on the receiver side because it is a function of the cable delay, we cannot predict where it will be. This ambiguous delay causes the decoder 202a to oversample the data provided from the clock transmission lines 104/212. Since the input data rate is the same as the output data rate, the present invention generates clocks of various phases from the signal on line 214. By using these clocks, the signal line 212 is sampled several times per data period to transition the data. If such a data transition is detected, it is used as a data boundary.

As shown in Fig. 6A, the first embodiment of the decoder 202a includes a delay synchronization loop 602, a sampling device 604, a data generating device 606, and a transition detector 608. Delayed synchronization loop 602 has an input coupled to receive a clock signal on line 214. The same delay synchronization loop may be used by the clock generator 200 and the decoder 202. The delay synchronization loop 602 is of a conventional type and provides a plurality of phase shifted clock signals. The outputs of the delayed synchronization loop 602 are each connected to the inputs of the sampling device 604. Sampling device 604 includes a control logic for generating a signal on the first output. This control logic controls when transition detector 608 samples and latches the signal on line 212. For example, the sampling device 604 may generate the control signal for all rising edges indicated on the input from the delay synchronization loop 602. The first output is coupled to one input of the transition detector 608. The sampling device 604 also provides, via the second output, transition signals output from the delay synchronization loop 602 and time signals representing time in a clock period. The second output of the sampling device 604 is connected to one input of the data generating device 606. Transition detector 608 is coupled with line 212 and has an input that receives a signal from receiver 106. Transition detector 608 detects a transition of signals on line 212. If there is a transition, transition detector 608 indicates an output. The data generating device 606 is connected to the sampling device 604 to input a signal representing a time in a clock cycle and is connected to the transition detector 608 to identify when a transition occurs. Using this information, the data generating device 606 outputs bit values corresponding to the time point at which the transition occurs. For example, if a transition occurs before the falling edge time of a clock having a 50% duty cycle, the data generator 606 may output 1. If a transition occurs after the falling edge time of the clock having a 50% duty cycle, the data generator 606 may output zero. This example assumes a data rate of 1 bit per clock cycle. One of ordinary skill in the art will understand how the data generator 606 can be changed depending on the number of bits per clock period transmitted by the receiver 106. The output of the data generator 606 is provided on the line 218 and used by the transmitter 102.

6B shows another embodiment of a decoder 202a. When the receiving device 106 transmits data in a return to zero (RZ) manner, the rising edge of the input clock is used as a data reference point, and the phase of the center of successive rising edges is generated to generate the input data at the reference point. Used to sample. Therefore, the decoder 202a includes only the delay lock loop 650 and the flip-flop 620. Delayed synchronization loop 650 provides a signal such as φ 3 with a rising edge at approximately the center of the clock period. This signal is applied to the clock input of flip-flop 620 to cause flip-flop 620 to latch near the center of the clock period. The data input of the flip-flop 620 is connected with the line 212 to input a data signal transmitted by the receiving device 106, and the output of the flip-flop 620 provides a data output and is connected with the line 218. do.

One of ordinary skill in the art will appreciate that the decoder 202 can be formed as an integrator-type receiver in which the decoder divides the clock period again and the integrator integrates the divided time periods and compares the integration results. Will understand. The signal is effectively integrated to determine the data values for comparison.

Receiver

Fig. 7 shows a preferred embodiment of the receiving device 106 constructed in accordance with the present invention. The receiver 106 includes a line interface 706, a clock regenerator 700, a data decoder 702, a delay compensator 708 and a return channel encoder 704.

Line interface 706 is the same as described in Figures 5A and 5B. However, for the receiver 106 the line interface 706 is completely optional and the receiver 106 can operate without the line interface. Line interface 706 buffers the signals and filters them for better use in recovery. Line interface 706 has one input, one output, and a bidirectional port. The bidirectional port is connected to the clock transmission line 104. The input of the line interface 706 is connected with the line 720 to input the output of the return channel encoder 704. An output of line interface 706 is coupled to line 722 to provide input signals to clock regenerator 700 and data decoder 702. For ease of understanding, reference numerals for line interface 706 have been added to FIG. 5A.

Clock regenerator 700 has one input and one output. The input of clock regenerator 700 is connected via line 722 to receive signals on clock transmission line 104 from line interface 706. The clock regenerator 700 monitors the transmission line 104, receives the signals, and filters the received signals to generate a clock signal of the receiver 106. The output of clock regenerator 700 is coupled to line 710 and provides a clock signal for receiver 106 for use in recovering data from data channel 108. The clock regeneration device 700 regenerates the clock signal of the reception device 106 using only rising edges of the signals on the signal transmission line 104. This allows the falling edge position and voltage level to be used for other data transfers. A preferred embodiment of clock regeneration device 700 is an amplifier capable of providing an amplified form of signal to other digital logic that receives the clock. 8 illustrates another embodiment of a clock regeneration device 700. In Fig. 8, the clock regeneration device 700 is a phase locked loop 800 having an input connected to the transmission line 104 and an output providing a clock as a square wave. The phase locked loop 800 is of a conventional type and includes a phase detector 802, an amplifier and a filter 804, and a voltage controlled oscillator 806. These components 802, 804, 806 are connected in a conventional manner with the input of a phase detector 802 coupled to the transmission line 104 and the output of a voltage controlled oscillator providing a clock signal and fed back to the phase detector 802. . One of ordinary skill in the art only needs to detect rising edges on transmission line 104 and generate a clock signal therefrom, so that various various embodiments of phase locked loop can be used for clock regeneration device 700. Will understand. Other embodiments of clock regeneration device 700 may also use delayed synchronization loops.

Like the clock regenerator 700, the data decoder 702 has an input coupled via line 722 to receive signals on the transmission line 104 from the line interface 706. The data decoder 702 filters and decodes the signals to generate data signals output on the line 712. Data decoder 702 has another input coupled to line 710 to receive the clock signal recovered from clock regenerator 700. This is done by determining the position of the falling edge of the clock signal and converting this falling edge position into bit values. Data transmitted from the transmitter 102 to the receiver 106 is valid at the falling edge of the clock. 9 shows a preferred embodiment of a data decoder 702. The preferred embodiment of the data decoder 702 is very similar to the second embodiment of the decoder 202b of the transmitter 102. The data decoder 702 differs only in connection with other components as shown in FIG. The data decoder 702 includes a delay locked loop 650 and a flip flop 620. The clock input of the delay synchronization loop 650 is connected to the line 710 to input a regenerated clock signal. The data input of flip-flop 620 is connected to line 722 to input filtered data signals from transmission line 104. The output of flip-flop 620 provides a data output and is coupled with line 712. The operation of the data decoder is as described in FIG. 6B.

Delay compensator 708 is coupled to line 710 to input the recovered clock signal. The delay compensator 708 adjusts the recovered clock signal to compensate for the propagation delay on the transmission line 104 and the propagation delay in recovering the clock so that the signal used to adjust the time to send data back to the transmitter 102 is The clock transmission line 104 has a timing that matches the original clock signal on the transmission device side. The output of the delay compensator 708 provides an adjusted clock signal that is used by the return channel encoder 704. In a preferred embodiment, the delay compensator 708 is a phase locked loop with a delay circuit in the feedback loop between the voltage controlled oscillator and the phase detector, as will be appreciated by those skilled in the art. This configuration provides a negative delay so that the clock signal for the return channel signals is advanced to match the timing of the CGOut signal of the transmitter 102 by electronic delay.

Return channel encoder 704 generates signals and provides them on transmission line 104 via line 720 and line interface 706. Return channel encoder 704 has a data input coupled to line 714 to receive control and data signals for data to be transmitted on the return channel. Return channel encoder 704 also has a clock input connected by line 724 to the output of delay compensator 708 to input a modified clock signal for the appearance of data and timing of data state changes. These signals appear or overlap on clock and data signals provided by the transmitter 102. Return channel encoder 704 sends data back to transmitter 102 at the falling edge of the clock to prevent return channel 704 from causing jitter on the clock signal. In particular, return channel encoder 704 minimizes transition activity around the rising edge of the clock by fixing the polarity around the rising edge of the clock. This is done by including a delayed synchronization loop in the return channel encoder 704. The return channel encoder 704 reduces the interference and influence on the transmission of clock and data signals by the transmitter 102 by loading the data into a clock pair in the form of a voltage signal rather than the transmission line 104 or edge position.

10A shows a first embodiment of a return channel encoder 70a. The first embodiment of return channel encoder 704 provides the minimum functionality for transmission. For example, return channel encoder 704a may be a 1 bit link. This has a low data rate and does not allow DC balancing, but is advantageous because there is no latency in obtaining data (once the data is in the transmitter, there is no latency by decoding) and the operation is simple. The first embodiment of the return channel encoder 704a includes a rising edge detector 1002, a delay circuit 1004, and a latch 1008. Rising edge detector 1002 has an input coupled to line 724 that accepts a signal for timing a data output change. After the rising edge detector 1002 detects the rising edge, the rising edge detector 1002 outputs the output when the rising edge is input. The output of the rising edge detector 1002 is connected to the input of the delay circuit 1004. The delay circuit delays the signal output of the rising edge detector 1002 by 1/2 clock period. Thus, when the clock has a 50% duty cycle, the output of delay circuit 1004 is at the time of the ideal falling edge. The output of delay circuit 1004 is used to control or latch latch 1008. The data thus changes state at the ideal falling edge of the input timing signal on line 724. Latch 1008 has one data input and one data output. The data input is connected to line 714 to input data, and the data output is connected to line 720 for outputting data by line interface 706. One of ordinary skill in the art will understand how to configure other return channel encoders that send back more than one bit per clock cycle to the transmitter 102.

Also, those skilled in the art will understand that the rising edge detector 1002 and the delay circuit 1004 may be replaced with a delay synchronous loop or a phase synchronous loop as described below with reference to FIG. 10B. Figure 10B shows a second embodiment of return channel encoder 704b. The second embodiment of the return channel encoder 704b includes a delay lock loop 650 and a flip-flop 620. Its operation is the same as that of Fig. 6B, and has been described above. The input of the delay locked loop 650 is connected to line 724 and the data input of flip-flop 620 is connected to line 714. Data output of flip-flop 720 provides data output on line 720.

The channel return encoders 704a, 704b of the first or second embodiment may include an encoder that encodes the data before transmitting the data on the return channel. Adding a 4 bit / 5 bit encoder or a 9 bit / 10 bit encoder is advantageous as this encoder increases the amount of data that can be transmitted per clock period. However, the design of the transmitter and receiver is more complicated and there is a waiting time in using the data.

11A, 11B, 12A and 12B show timing diagrams of the main signals of the present invention. The timing diagram is 1) CGOut signal on line 210 on clock transmission line 104, 2) signal on clock transmission line 104, 3) regenerated clock signal on line 710, 4) line 712 Recovered data signal, 5) a return channel signal carried on the clock transmission line 104 by the return channel encoder 704. 11A shows signals of the transmitter 102 using a return to zero (RZ) scheme. Fig. 11B shows signals on the transmission line and signals of the receiving device 106 using the RZ method. In contrast, FIGS. 12A and 12B show a signal relationship for a non-return zero (NRZ) scheme. 12A shows a signal at the transmitter 12, and FIG. 12B shows a signal at the receiver 106. FIG.

The timing diagrams illustrate various features of the combined clock and bidirectional data links of the present invention. First, transition activity and polarity activity by the transmitter 102 or receiver 106 are minimized or eliminated near the rising edge of the CGOut signal. Secondly, data transmission from the transmitter 102 to the receiver 106 takes place via the falling edge of the clock signal. Third, the data transmission from the receiver 106 to the transmitter 102 is by adjusting the current or voltage level, and no change occurs near the rising edge of the clock signal from the transmitter 102. Fourth, the output of the data signal by the receiving device 106 does not affect the edges of the signals output from the transmitting device 102.

Clock multiplication

One of the important advantages of the present invention is that it is not necessary to change any part of the present invention in operating the present invention when the clock is multiplied or not multiplied. In some cases, the transmitter 102 and receiver 106 have the ability to increase the data rate by increasing the clock rate through clock multiplication (transmitting multiple clock signals during one period of the clock signal). . In this case, the transmitter 102 inquires whether the receiver 106 can handle clock multiplication. Receiver 106 informs transmitter 102 that it can handle any level of clock multiplication. The transmitter then transmits the highest possible clock multiplication level. In clock multiplication, the transmitter 102 only transmits the multiplied clock, but the receiver 106 divides the multiplied clock into the original pixel clock so that the main data channel can use this clock. For any data link, the phase information for the clock is also important and can be transmitted over the data link provided in the present invention. In the transmitter 102, DLL / PLL is used to multiply the clock by an integer multiple of the input clock. For some transmission lines, only multiplications are allowed because jitter information is important. However, if this is not important, you can use a multiple of the appropriate multiple to secure the bandwidth.

As described above, although the technical idea of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (26)

A clock generator having a first input coupled to input a clock signal and a second input and output coupled to input a control signal representing a data value to be transmitted, and modulating a falling edge of the output signal to represent different data values; Apparatus for transmitting clock signals and data signals through a signal line comprising. The method of claim 1, And a data decoder having an input connected to said signal line and an output for providing data from said signal line, said data decoder extracting data signals. The method of claim 2, Loading a signal on the signal line or extracting signals from the signal line, and further comprising a line interface having an input connected to the output of the clock generator, an output connected to the input of the decoder, and a bidirectional port connected to the signal line; An apparatus for transmitting clock signals and data signals through a signal line. The method of claim 3, The line interface includes a first amplifier connecting the output of the clock generator to the signal line, a differential amplifier having a first input connected to the signal line, and a second amplifier connected to the second input of the differential amplifier. 2. An apparatus for transmitting clock signals and data signals over a signal line, comprising: two amplifiers, wherein the output of the differential amplifier provides the output of the line interface. The method of claim 1, The clock generator is A delay synchronization loop having an input connected to input a clock signal, outputs for outputting signals shifted in phase from the input signal, A multiplexer having a plurality of inputs respectively coupled to the outputs of the delayed synchronization loop, an output for selecting one of the plurality of input signals for output; And a latch having a first input coupled to one output of the delayed synchronization loop and a second input coupled to the output of the multiplexer. The method of claim 5, And a single state multivibrator having an input for receiving a clock signal and an output coupled with the input of said delayed synchronization loop. The method of claim 5, And the latch further comprises a pair of cross-connected NAND gates. The method of claim 2, The decoder A delay synchronization loop having an input connected to input a clock signal, a plurality of outputs for outputting phase shifted signals from the input signal, A sampling device having a plurality of inputs and first and second outputs connected to the outputs of the delayed synchronization loop, respectively, for controlling when signals are sampled and indicating a time at which signals are sampled; A transition detector for determining when a transition occurs to a signal, the transition detector having a data input connected to the signal line and a control input connected to a first output of the sampling device; A data generation device having a first input connected to a first input of the sampling device, a second input and an output connected to an output of the transition detector, and generating bit values corresponding to a time point at which a transition occurs in the signal line; An apparatus for transmitting clock signals and data signals through a signal line further comprising. The method of claim 2, The decoder A delay synchronization loop having an input connected to input a clock signal, a plurality of outputs for outputting signals shifted in phase from the input signal, And a flip-flop having a control input coupled to one of the plurality of outputs of the delayed synchronization loop and a data input and an output coupled to the signal line. Device for. The method of claim 1, The transmitter is connected to the receiver by the signal line, and the receiver is A clock regenerator having an input coupled to said signal line and an output for recovering a clock signal from said signal line; And a second decoder having a first input connected to the signal line, a second input connected to an output of the clock regenerator, and an output for providing data from the signal line, and extracting data signals. A device for transmitting clock signals and data signals. The method of claim 10, And a clock reproduction growth value of the receiving device is an amplifier. The method of claim 10, And a clock reproduction growth value of the receiving device is a phase locked loop. The method of claim 10, The second decoder A delay synchronization loop having an input connected to an output of the clock regenerator, and a plurality of outputs for outputting phase shifted signals from the input signal; A sampling device having a plurality of inputs and first and second outputs connected to the outputs of the delayed synchronization loop, respectively, for controlling when signals are sampled and indicating a time at which signals are sampled; A transition detector for determining when a transition occurs to a signal, the transition detector having a data input connected to the signal line and a control input connected to a first output of the sampling device; A data generation device having a first input connected to a first input of the sampling device, a second input and an output connected to an output of the transition detector, and generating bit values corresponding to a time point at which a transition occurs in the signal line; An apparatus for transmitting clock signals and data signals through a signal line further comprising. The method of claim 10, The second decoder A delay synchronization loop having an input connected to an output of the clock regenerator and a plurality of outputs for outputting signals shifted in phase from an input signal; And a flip-flop having a control input coupled to one of the plurality of outputs of the delayed synchronization loop and a data input and an output coupled to the signal line. Device for. The method of claim 10, Loading a signal on the signal line or extracting signals from the signal line, and further comprising a second line interface having an input, an output connected to the input of the second decoder and a clock regenerator, and a bidirectional port connected to the signal line; An apparatus for transmitting clock signals and data signals through a signal line. The method of claim 10, And a delay compensator having an input connected to the output of the clock regenerator and an output for adjusting the recovered clock signal to compensate for propagation delay. . The method of claim 16, And a return channel encoder having a first input connected to input data for transmission, a second input connected to an output of the delay compensator, and an output connected to the signal line, and transmitting signals to the signal line. An apparatus for transmitting clock signals and data signals through signal lines. The method of claim 17, The return channel encoder A delay synchronous loop having an input connected to the output of the delay compensator and a plurality of outputs for outputting signals shifted in phase from the input signal; And a flip-flop having a control input coupled to one of the plurality of outputs of the delayed synchronization loop and a data input and an output coupled to the signal line. Device for. A clock regenerator having an output and an input coupled to the signal line, for recovering a clock signal from the signal line; A data decoder having a first input coupled to the signal line, a second input coupled to an output of the clock regenerator, and an output providing data from the signal line; The data decoder A delay synchronization loop having an input connected to an output of the clock regenerator, and a plurality of outputs for outputting phase shifted signals from an input signal; And a flip-flop having a control input connected to one of the plurality of outputs of the delayed synchronization loop, a data input connected to the signal line, and an output for providing data from the signal line. Receiver connected to the. The method of claim 19, And a line interface having a signal on the signal line or extracting signals from the signal line, the line interface having an input and an output connected to an input of the second decoder and a clock regenerator and a bidirectional port connected to the signal line. Receiver connected to the transmitter via the signal line. The method of claim 20, And a delay compensator having an input connected to an output of the clock regenerator and an output for adjusting a recovered clock signal to compensate for propagation delay. The method of claim 21, And a return channel encoder having a first input connected to input data for transmission, a second input connected to an output of the delay compensator, and an output connected to the signal line, and transmitting signals to the signal line. Receiver connected to the transmitter via the signal line. The method of claim 22, The return channel encoder An input coupled to the output of the delay compensator, a rising edge detector having an output, A delay circuit having an input coupled with an output of the rising edge detector and an output; And a latch having a control input connected to an output of the delay circuit, a data input for inputting data, and a data output connected to an input of the line interface. The method of claim 22, The return channel encoder A delay synchronous loop having an input connected to the output of the delay compensator and a plurality of outputs for outputting phase delayed signals from the input signal; And a flip-flop having a control input coupled to one of the plurality of outputs of the delayed synchronization loop, a data input coupled to the signal line, and an output. Receiving an input and an output, the signal being input to a clock regenerator for recovering the clock signal from the signal line; Receiving a signal as a data input of a data decoder for extracting data from the signal inputted through the data input, having a control input, a data input, and a data output; Transferring a clock signal from an output of the clock regenerator to a control input of the data decoder, Delivering the clock signal to an input of a delay compensator having an input and an output from the output of the clock regenerator and adjusting a clock signal from the clock regenerator to compensate for propagation delay; and A control input coupled to input the output of the delay compensator, a data input for receiving data, and transmission of data from the data output of a return channel encoder having a data output through the signal line; A method for receiving and transmitting signals using a device. The method of claim 25, Receiving a signal using a receiver connected to the signal line further comprising the step of receiving a signal to an input connected to the signal line and an input of a line interface having an output before receiving a signal to the input of the clock regeneration device And how to transmit.