KR20020081154A - Method for Etching With High Selectivity To Photoresist - Google Patents
Method for Etching With High Selectivity To Photoresist Download PDFInfo
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- KR20020081154A KR20020081154A KR1020020044096A KR20020044096A KR20020081154A KR 20020081154 A KR20020081154 A KR 20020081154A KR 1020020044096 A KR1020020044096 A KR 1020020044096A KR 20020044096 A KR20020044096 A KR 20020044096A KR 20020081154 A KR20020081154 A KR 20020081154A
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- etching
- photoresist
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 229920002120 photoresistant polymer Polymers 0.000 title claims abstract description 19
- 238000005530 etching Methods 0.000 title claims description 36
- 239000007789 gas Substances 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 150000004767 nitrides Chemical class 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 5
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 4
- 239000011737 fluorine Substances 0.000 claims abstract description 4
- 239000000203 mixture Substances 0.000 claims abstract description 4
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims abstract description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 3
- 239000001301 oxygen Substances 0.000 claims abstract description 3
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 claims description 6
- 230000009977 dual effect Effects 0.000 abstract description 4
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 5
- 229910003481 amorphous carbon Inorganic materials 0.000 description 5
- 229910052799 carbon Inorganic materials 0.000 description 5
- MHESUICHGPWXRV-UHFFFAOYSA-N methanediolate silicon(4+) Chemical compound C([O-])[O-].[Si+4].C([O-])[O-] MHESUICHGPWXRV-UHFFFAOYSA-N 0.000 description 5
- 238000004380 ashing Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 125000000962 organic group Chemical group 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 고선택비를 갖는 에칭방법에 관한 것으로, 특히 미세화가 진행된반도체 디바이스의 듀얼 다마신 공정에 의한 콘택트 홀 및 배선 구조의 형성시에 사용되는 저유전율의 층간 절연막의 드라이 에칭 기술에 의한 포토레지스트에 대해 고선택비를 갖는 에칭방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an etching method having a high selectivity, and in particular, a photo by a dry etching technique of a low dielectric constant interlayer insulating film used in the formation of contact holes and wiring structures by a dual damascene process of a semiconductor device which has been miniaturized. The present invention relates to an etching method having a high selectivity to a resist.
반도체 집적회로의 고집적화에 따른 배선폭이나 배선 간격이 대단히 좁아지고 있으며, 배선 길이도 상당히 길어지고 있다. 그 결과, 배선 저항이나 배선간 용량이 증대하고, 이것에 의한 배선 지연이나 소비전력의 증대가 무시할 수 없게 되어왔다. 이와 같은 고집적화에 따른 디바이스 성능에의 영향을 저감하는 방법의 한가지로서, 배선 사이의 절연막을 저유전율화하는 방법이 연구 개발되고 있다.Wiring widths and wiring spacings are very narrow due to high integration of semiconductor integrated circuits, and wiring lengths are also considerably longer. As a result, wiring resistance and inter-wire capacitance have increased, and thus the increase in wiring delay and power consumption has not been negligible. As one of the methods for reducing the influence on the device performance due to such high integration, a method of reducing the dielectric constant of the insulating film between wirings has been researched and developed.
상기한 저유전율 재료로서는, 통상적으로 TEOS 또는 보로포스파 실리카 글래스(BPSG)가 증착되는 플라즈마 CVD 공정으로 이산화실리콘 산화물이 성장하는 실리카산화물로 이루어진다. 이러한 실리카산화물중 하나는 산화막(SiO2)에 불소를 함유한 FSG막이나 유기 OSG(Organo Silicate Glass)막, 유기 절연막 또는 다공질 산화물등을 들 수 있다. 최근, 층간 절연물로 사용되는 저유전율(k) 물질이 개발되고 있다. 이러한 저유전율 물질은 수평 또는 수직으로 인접한 라인사이의 용량성 결합을 감소시킬 수 있어 크로스 토크 전력소비 및 신호 상승 시간을 감소시킨다.As the low dielectric constant material described above, a silica oxide in which silicon dioxide oxide grows is usually formed by a plasma CVD process in which TEOS or Borophospha silica glass (BPSG) is deposited. One of such silica oxides includes an FSG film containing fluorine in an oxide film (SiO 2 ), an organic OSG (Organo Silicate Glass) film, an organic insulating film, or a porous oxide. Recently, low dielectric constant (k) materials used as interlayer insulators have been developed. These low dielectric constant materials can reduce capacitive coupling between horizontally or vertically adjacent lines, reducing cross talk power consumption and signal rise time.
그러나, 상기 다공성 산화물 등의 저유전율막을 디바이스에 도입하는데 있어서는, 양호한 콘택트 홀 및 배선 구조를 얻기 위하여 다공성 산화물는 실리콘 산화물, 예컨대 실리콘 카보나이트(SiC) 또는 실리콘 니트라이드(SiN)에 대하여 매우큰 에칭 선택비를 가져야 한다.However, in introducing a low dielectric constant film such as the porous oxide into the device, the porous oxide has a very large etching selectivity with respect to silicon oxide, such as silicon carbonite (SiC) or silicon nitride (SiN), in order to obtain good contact hole and wiring structure. Should have
따라서, 본 발명의 목적은 반도체 디바이스의 제조시 콘택트 홀을 형성할 경우 형상이 안정될 수 있도록 에칭 가스를 함유하는 탄소를 조성 중 적어도 일부로 하는 OSG의 가스가 점유되는 드라이 에칭 방법에 의해 달성된 포토레지스트에 대해 고선택비의 에칭이 가능한 반도체 장치의 제조 방법을 제공하는 데에 있다.Accordingly, an object of the present invention is achieved by a dry etching method in which a gas of OSG containing at least part of a composition containing carbon containing an etching gas is occupied so that the shape can be stabilized when forming a contact hole in the manufacture of a semiconductor device. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device capable of etching a high selectivity to a resist.
도 1 내지 도 13은 본 발명의 제1 실시 형태에 따른 에칭 방법에 의해 반도체 장치의 제조 방법을 나타내는 반도체 장치의 단면도.1 to 13 are cross-sectional views of a semiconductor device, showing the method for manufacturing the semiconductor device by the etching method according to the first embodiment of the present invention.
<도면의 주요 부분에 대한 간단한 설명><Brief description of the main parts of the drawing>
1 : 실리콘 기판1: silicon substrate
10: 실리콘 카보나이트(SiC) 20 : 비정질 카본(a-C)10: silicon carbonite (SiC) 20: amorphous carbon (a-C)
30 : 다공성 산화물 34 : 측벽30 porous oxide 34 sidewall
35 : 콘택트 홀 38 : 포토레지스트35 contact hole 38 photoresist
39: 마스크 40 : 탄탈 니트라이드39: mask 40: tantalum nitride
상기한 목적을 달성하기 위하여 상기와 같은 본 발명은 실리콘 및 포토레지스트에 대해 산화물 및 니트라이드에 대해 선택적으로 에칭하는 에칭방법에 있어서,In order to achieve the above object, the present invention as described above in the etching method for selectively etching the oxide and nitride with respect to silicon and photoresist,
산화물 및 니트라이드 층이 적층되고 상기 산화물 및 니트라이드 및 실리콘에 패턴 레지스트 층이 중첩된 기판을 에칭 실에 배치하는 공정;Disposing a substrate in which an oxide and nitride layer is stacked and the pattern resist layer is superimposed on the oxide and nitride and silicon in an etching chamber;
상기 에칭실에 C4F6로 구성된 그룹에서 선택된 낮은 선택비를 가진 유기실리카글래스(OSG), 제 1의 플루오르, 제 2의 산소, 제 3의 디플로로 메탄, 및 제 4의 카본 모노 산화물을 함유한 에칭 가스 혼합물을 유입하는 공정; 및,In the etching chamber, an organic silica glass (OSG) having a low selectivity selected from the group consisting of C 4 F 6 , a first fluorine, a second oxygen, a third dichloromethane, and a fourth carbon mono oxide Flowing in the etching gas mixture containing the; And,
상기 산화물 및 니트라이드 층이 상기 실리콘 및 포토레지스트에 대해 선택하여 에칭하도록 상기 에칭 가스를 여기시키는 공정을 포함한다.Exciting the etching gas such that the oxide and nitride layer is selectively etched against the silicon and photoresist.
도 1 내지 도 13은 본 발명의 포토레지스트에 대해 고선택비를 갖는 에칭방법에 대한 제1 실시 형태에 관한 포토레지스트에 대해 고선택비를 갖는 에칭방법에 대해 설명하기 위한 것으로, 드라이 에칭 또는 애싱 장치(도시 안됨)장치에서 처리영역의 에칭실에서 이루어지는 형태에 관한 포토레지스트에 대해 고선택비를 갖는 에칭방법에 대해서 설명한다. 상기 설명한 바와 같이 배선사이의 절연막을 저유전율화하는 방법은 도 1 내지 및 도 13에 도시된 것과 같은 구조를 갖는다.1 to 13 are views for explaining an etching method having a high selectivity with respect to the photoresist according to the first embodiment of the etching method having a high selectivity with respect to the photoresist of the present invention, dry etching or ashing An etching method having a high selectivity with respect to a photoresist in the form of an apparatus (not shown) in an etching chamber of a processing region will be described. As described above, the method for lowering the dielectric constant between wirings has a structure as shown in FIGS. 1 to 13.
먼저, 도 1에 있어서, 실리콘 기판(1)에 하층 배선이 되는 금속 배선(2)을 형성한 후, 금속 배선(2) 위에 배리어층으로서 실리콘 카보나이트(SiC) 또는 실리콘 니트라이드(SiN)(10)를 증착하고, 이 실리콘 카보나이트(SiC) 또는 실리콘 니트라이드(SiN)(10)상부에 플라즈마증가형 화학증기 증착법(PECVD)에 의해서 증착될수 있는 층간 절연막이 되는 비정질 카본(amorphous carbon;a-C)이나 스핀-온 카본(Spin-on carbon)(20)을 증착한다.First, in FIG. 1, after forming the metal wiring 2 which becomes an underlayer wiring in the silicon substrate 1, silicon carbonite (SiC) or silicon nitride (SiN) 10 as a barrier layer on the metal wiring 2 is formed. Amorphous carbon (aC) which forms an interlayer insulating film which can be deposited on the silicon carbonite (SiC) or silicon nitride (SiN) 10 by plasma enhanced chemical vapor deposition (PECVD). Spin-on carbon 20 is deposited.
이어서, 상기 비정질 카본(a-C) 또는 스핀-온 카본(20)에 대하여 패턴을 떠서 다공성 산화물(30)을 증착한(도 2 참조)다음, 포토리소그래피 기술에 의해 하층 배선(10)을 도통시키기 위한 콘택트 홀(35)을 형성하고, 플라즈마 식각하여 패턴을 형성한다(도 3 참조).Subsequently, a pattern is deposited on the amorphous carbon (aC) or the spin-on carbon 20 to deposit the porous oxide 30 (see FIG. 2), and then the conductive layer 10 is made to conduct the lower wiring 10 by photolithography. The contact hole 35 is formed, and a plasma is etched to form a pattern (see FIG. 3).
다음에, 도 4에 있어서, 미세한 홈을 형성하는 트랜치 에칭(trench etching) 동안에 컨택트 홀(35) 또는 비아 바닥을 보호하도록 PR(Photo Resist)층(38)를 충전시킨다.Next, in FIG. 4, the PR (Photo Resist) layer 38 is filled to protect the contact holes 35 or via bottom during trench etching to form fine grooves.
한편, 본 발명의 도 3 및 도 4에서 나타낸 바와 같이, 먼저 에칭 가스로서 C4F6/O2/CH3F/Ar의 혼합가스를 이용한 듀얼 다마신(Dual Damascene)법에 의해 다공성 산화물(30)을 에칭한다. 이 혼합가스인 에칭제는, 도 4에 도시된 바와 같이 에칭전에 맹렬하게 형성되는 컨택트 홀(35)의 에칭 선택비를 크케하면서 퇴적하는 데에 유리하다. 여기서, 포토레지스트 및 실리콘 카바이트에 대해 선택비가 큰 유기실리카 글래스(Organic Silica Glass; OSG)를 에치 스탑구조로 사용하여 에칭한다. OSG 물질은 CH4/N2/O2/CF4또는 H2/N2/O2/CF4중에서 선택된다.On the other hand, as shown in Figures 3 and 4 of the present invention, the porous oxide (Dual Damascene) method using a mixed gas of C 4 F 6 / O 2 / CH 3 F / Ar as the etching gas first ( 30) is etched. This mixed gas etchant is advantageous for depositing while increasing the etching selectivity of the contact holes 35 which are formed violently before etching as shown in FIG. Here, etching is performed using an organic silica glass (OSG) having a high selectivity for photoresist and silicon carbide as an etch stop structure. The OSG material is selected from CH 4 / N 2 / O 2 / CF 4 or H 2 / N 2 / O 2 / CF 4 .
여기서, 다공성 산화물(30)에는 폴리머코팅이 지배적으로 형성된다. 이 폴리머 코팅(30)은 모두 카본에 기초한 폴리머이므로 다공성 산화물(30)에 대하여 에칭 첨가제로 될 수 있다.Here, the polymer coating is predominantly formed on the porous oxide 30. Since this polymer coating 30 is all carbon based polymer, it can be an etching additive for the porous oxide 30.
또한, 본 발명은 컨택홀의 공정을 설명한 것으로, 니트라이드에 대해 비교적 높은 선택비를 가지며, 애스펙트 비율이 큰 옥사싱드로 에칭홀을 형성한다.In addition, the present invention has described the process of the contact hole, forming an etching hole with an oxinged having a relatively high selectivity to the nitride, and a large aspect ratio.
다음에, PR층(38)의 트랜치 깊이를 조절하기 위해 도 5에서와 같이, 트랜치에 대해 PR층(38)을 에칭 백한다. 또한 또다른 트랜치를 형성하기 위해 에칭 마스크(39)를 적층하고(도 6 참조), 포토리소그래피 공정에 의 하여 다공성 산화물(30)을 에칭하고(도 7 참조), 에칭 마스크(39)를 사용하여 포토레지스트(30) 및 실리콘 카바나이트(10)를 제거하고(도 8 참조), 그 후, 탄탈 니트라이드(TaN)층(40)를 증착한다(도 9 참조). 그 다음, 베이크하여 Cu(50)를 배리어로써 전기 화학적 도금법(ECP)에 의해 상기 Cu(50)를 증착하고(도 10), 상기 Cu(50)와 TaN(40)의 요철면을 평탄화하도록 CMP(화학 기계적 폴리싱)처리한다(도 11 참조).Next, to adjust the trench depth of the PR layer 38, the PR layer 38 is etched back to the trench, as in FIG. In addition, the etching mask 39 is stacked (see FIG. 6) to form another trench, the porous oxide 30 is etched by the photolithography process (see FIG. 7), and the etching mask 39 is used. The photoresist 30 and silicon carbanite 10 are removed (see FIG. 8), and then a tantalum nitride (TaN) layer 40 is deposited (see FIG. 9). Then, bake to deposit the Cu 50 by electrochemical plating (ECP) as a barrier (Cu 50) (FIG. 10), and CMP to planarize the uneven surface of the Cu 50 and TaN 40. (Chemical mechanical polishing) treatment (see FIG. 11).
다음, 고온 애싱설비에서 다공성 산화물(30)속의 C-폴리머와 비정질 카본을 제거하기 위해 O3또는 O2애싱 공정(또는 에칭 공정)을 행한다(도 12 참조). 도 12를 참조하면, 층간 절연막으로 사용되는 비정질 카본(a-C)이나 스핀-온 카본(SOC)(20)가 제거된 부분(60)을 예시하고 있음을 알 수 있다.Next, an O 3 or O 2 ashing process (or an etching process) is performed to remove the C-polymer and the amorphous carbon in the porous oxide 30 in the high temperature ashing facility (see FIG. 12). Referring to FIG. 12, it can be seen that the portion 60 in which amorphous carbon (aC) or spin-on carbon (SOC) 20 used as an interlayer insulating film is removed is illustrated.
다음, 도 12의 애싱(에칭)후에 진공 상태하에서 배리어로서 또다른 실리콘 카보나이트(SiC)층(70)를 후증착한다.Next, after the ashing (etching) of FIG. 12, another silicon carbonite (SiC) layer 70 is post-deposited under a vacuum.
상기와 같이, 본 발명의 포토레지스트에 대해 고선택비를 갖는 에칭방법에 의하면, OSG를 에칭 가스 중 적어도 일부에 이용하여 듀얼 다마신을 행함으로써, 콘택트 홀의 에칭을 행하여 콘택트 홀의 형상을 안정되고 신뢰성이 우수하게 형성할 수 있다.As described above, according to the etching method having a high selectivity with respect to the photoresist of the present invention, the contact hole is etched by performing dual damascene using OSG in at least a part of the etching gas, thereby making the shape of the contact hole stable and reliable. This can be formed excellently.
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