KR20020080619A - Receiving device and method for time/frequency synchronizing system using satellites - Google Patents

Abstract

PURPOSE: A receiving apparatus of a time/frequency synchronization system utilizing a satellite and a method for the same are provided to implement a kernel component system of time synchronization system and utilize a tool for continuously testing the performance of the system by receiving and demodulating the time/frequency information received from the satellite in the time/frequency synchronization system utilizing the satellite. CONSTITUTION: A receiving apparatus of a time/frequency synchronization system utilizing a satellite includes a base band converter(11) for down converting a base band signal in response to a reference clock transferred through a phase lock loop(PLL) and for analog/digital(A/D) converting the down converted base band signal in response to a local oscillation frequency after a receiving signal with an intermediate frequency(IF) inputted from outside is low noise amplified and filtered, a base band demodulator(12) for performing an initial searcher, a tracker and a data demodulation in response to the local oscillation frequency to time synchronize a base band digital signal transmitted from the base band converter(11) under the control of a digital signal processor(13) and the digital signal processor(13) for controlling the base band demodulator(12) to automatically convert into a searching mode after booting if a power is applied or a receiver is reset.

Description

Receiving device and method for time / frequency synchronizing system using satellites}

The present invention relates to an apparatus and method for receiving a time / frequency synchronization system using a satellite, and more particularly, to demodulate time / frequency information necessary for a system by receiving time and frequency necessary for synchronization of a wired / wireless communication network from a satellite. will be.

Conventional technology relies on the Global Positioning System (GPS), a low orbit military satellite in the United States, which basically transmits time-synchronized signals to the ground by GPS satellites with absolute time and frequency synchronization. The ground base station then uses this signal to synchronize time and frequency.

Therefore, in the present technical field, a received signal of a 70 MHz intermediate frequency (IF), which is a carrier downconverted signal from a stationary satellite, is converted to a baseband for time / frequency synchronization and transmitted to a baseband. After synchronizing time, there is a need for a method for extracting baseband data and providing time / frequency information required for a system.

The present invention has been proposed to meet the above-described requirements, and a device for receiving a time / frequency synchronization system for extracting time and frequency information received from a satellite and providing time and frequency information to each communication system, and its The purpose is to provide a method.

1 is a block diagram of an embodiment of a receiving apparatus of a time / frequency synchronization system according to the present invention;

2 is a detailed block diagram of an embodiment of a baseband demodulator in a receiving apparatus of a time / frequency synchronization system according to the present invention.

3 is a diagram illustrating an embodiment of a data type conversion process for the baseband demodulator of FIG.

4 is an embodiment state transition diagram of an initial searcher for the baseband demodulator of FIG.

5 is a detailed block diagram of an embodiment of an initial searcher for the baseband demodulator of FIG.

6 is an exemplary state transition diagram of a sync tracking module for the baseband demodulator of FIG.

FIG. 7 is an embodiment DLL structure diagram of a synchronization tracking module for the baseband demodulator of FIG. 2. FIG.

8 is a detailed block diagram of an embodiment of a data demodulation module for the baseband demodulator of FIG.

* Explanation of symbols for the main parts of the drawings

11 baseband converter 12 baseband demodulator

13: digital signal processing 14, 16, 17: local oscillator

15: PLL

The present invention for achieving the above object is a phase synchronization loop (PLL) after low noise amplification and filtering of a received signal of an intermediate frequency (IF) band input from the outside in a receiving apparatus of a time / frequency synchronization system using satellites. Baseband converting means for downconverting the baseband signal according to a reference clock transmitted through the C-substrate and converting the downconverted baseband signal according to a local oscillation frequency; Under the control of the digital signal processing means, a baseband digital signal transmitted from the baseband converting means, based on the local oscillation frequency for time synchronization, an initial searcher, synchronization tracking, and a basis for performing data demodulation Band demodulation means; And the digital signal processing means for controlling the baseband demodulation means to automatically switch to a search mode after booting when the power is applied or the receiver is reset.

In addition, the present invention provides a phase synchronization loop (PLL) after low noise amplification and filtering of a received signal of an intermediate frequency (IF) band inputted from the outside in a reception method of a time / frequency synchronization system using satellites. A first step of downconverting to a baseband signal in accordance with a reference clock delivered through; A second step of analog-to-digital (A / D) converting the downconverted baseband signal according to a local oscillation frequency; And a third step of performing initial synchronization, synchronization tracking, and data demodulation on the baseband signal digitally converted by the baseband demodulator according to the local oscillation frequency for time synchronization.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of an embodiment of a receiving apparatus of a time / frequency synchronization system according to the present invention.

As shown in FIG. 1, the receiving apparatus of the time / frequency synchronization system according to the present invention, after low noise amplification and filtering of a received signal of an intermediate frequency (IF) band input from the outside, performs a phase locked loop (PLL: Phase). Downconverts the baseband signal according to the reference clock transmitted through the locked loop, and converts the downconverted baseband signal according to the local oscillation frequency of the local oscillator (16.352MHz) (16). The baseband conversion unit 11 for digital conversion and the baseband digital signal transmitted from the baseband conversion unit 11 under the control of the digital signal processing unit 13 for local time synchronization. The baseband demodulator 12 performs initial synchronization, synchronization tracking, and data demodulation according to the local oscillation frequency of the baseband demodulator 12, and the baseband demodulator 12 switches to the search mode automatically after booting when power is applied or the receiver is reset. And a digital signal processing unit 13 that control.

Here, the baseband converter 11 may include an IF filter 111 for filtering an intermediate frequency (IF) signal input from the outside and an IF amplifier for amplifying an IF signal transmitted through the IF filter 111. And a quadrature demodulator for converting the 70 MHz band IF signal into baseband in phase (I) and quadrature (Q) signals according to a reference clock of 140 MHz delivered through a phase locked loop (PLL). Low pass filtering unit 114 and 115 for low pass filtering the in-phase (I) and quadrature (Q) signals converted to baseband through the orthogonal demodulator 14, respectively, and a low pass filtering unit. An analog / digital (A / D) converter 116 for analog-to-digital (A / D) conversion of the in-phase (I) and quadrature (Q) signals filtered through 114, 115.

Here, the IF amplifier 112 is composed of a low noise amplifier and an automatic gain control amplifier for automatic gain control (AGC).

The operation of the receiver of the time / frequency synchronization system of the present invention having the structure as described above will be described in detail as follows.

The time / frequency synchronization system according to the present invention receives an IF signal in a 70 MHz band, obtains time synchronization, demodulates a data signal, and generates 1 pps (pulse per second) and 1 MHz clock signals.

That is, in more detail, the IF signal is amplified through the IF amplifier 112 through the IF filtering unit 111 in the 70 MHz band, and then transmitted to the quadrature demodulator 113.

On the other hand, the quadrature demodulator 113, which receives the reference clock of 140 MHz through the PLL 15, converts the IF signal of the 70 MHz band into the baseband I and Q signals, respectively. At this time, the local oscillator 14 provided as an input of the PLL 15 may control the output clock frequency by voltage variation, and the input variable voltage is adjusted by an automatic frequency control (AFC) algorithm.

Subsequently, the baseband converted I and Q signals are converted into digital samples through an analog / digital (A / D) converter 116 and input to the baseband demodulator 12. The clock used for A / D conversion is 16.352MHz, which is 32 times the chip change rate of PN (Pseudo Noise) code, and is used as the main clock of the baseband demodulator 12 implemented inside the field programmable gate array (FPGA). do. The baseband demodulator 12 for baseband demodulation is implemented in the FPGA, and an initial searcher, a synchronization tracking module, and a data demodulation module are implemented to achieve time synchronization with a signal sent from a transmitter. .

In addition, the FPGA includes a hardware structure for baseband demodulation, and algorithm control is performed by a digital signal processing unit (DSP). The digital signal processor 13 automatically switches the state of the baseband demodulator 12 to the search mode when power is applied or the receiver is reset. Accordingly, the baseband demodulator 12, which has been switched to the search mode, drives the initial searcher inside the FPGA, and then switches to the synchronous tracking mode where the search result for one period of the PN code is read and the synchronization tracking and data demodulation are performed. . Subsequently, in the synchronization tracking mode, the synchronization tracking module and the data demodulation module inside the FPGA are driven, and the demodulated data in the PN period unit from the FPGA is demodulated in bit units, and then a 1 second boundary is determined. .

2 is a structural diagram of an embodiment of a baseband demodulator in a receiving apparatus of a time / frequency synchronization system according to the present invention.

As shown in FIG. 2, the signal input to the baseband demodulator 12 includes a main system clock, a 16.352 MHz clock, a hardware reset, a baseband digital input signal, and the like. The output signals include 1pps and 1MHz. A clock signal and a data bit string demodulated in units of PN periods. In addition, the baseband demodulator 12 is connected to a DSP address bus and a data bus for interfacing with the digital signal processor 13.

However, since the configuration and operation of the baseband demodulator as described above are only known techniques in the art, detailed description thereof will be omitted herein. However, a method of implementing an initial searcher, a synchronization tracking module, and a data demodulation module for time synchronization with a signal transmitted from the baseband converter 11 will be described in detail.

3 is a diagram illustrating an embodiment of a data type conversion process for the baseband demodulator of FIG. 2.

As shown in FIG. 3, the baseband-converted analog signal is converted into a digital signal, and the analog-to-digital (A / D) conversion clock is 16.352 Msps (Mega samples per sec), which is 32 times the chip change rate. At this time, the A / D converted digital sample interval is 61.1546 nsec. Digital samples input at a change rate of 16.352 Msps are 6-bit data, of which only the upper 5 bits are used for internal correlation. At this time, the input digital signal is converted into a 2's complement type to be used internally in an offset binary form, which is an output form of the A / D converter, and then a DC (Direct Current) offset is converted. To eliminate it, convert it into the form of 2x + 1 (x: input sample) and use a 6-bit 2's complement signal for internal computation.

The A / D converted digital sample is passed through a decimator, decimated at a chip change rate of 0.511 Msps, and input to a searcher module and a synchronization tracking data demodulation module. The decimator extracts on-time and late-time samples according to the sampling time fed back from the synchronization tracking module. The on-time samples are extracted according to the sampling time fed back from the synchronization tracking module, and the rate-time samples are extracted after 16 samples (1/2 PN chips) after the sampling time.

4 is an exemplary state transition diagram of an initial searcher for the baseband demodulator of FIG.

As shown in FIG. 4, the PN code generator used in the searcher module receives an “PN seed”, a PN clock, a “start epoch” indicating a start time of the PN code, and the like. (pn1_on) and a half-chip late rate-time PN code (pn1_late). The PN code generator in the searcher module generates a PN code from a given "PN seed", delays the offset by one chip after the generation of one period of PN code, and then generates another period of PN code. Perform on PN offset. Information on the start offset of the generated PN code (pn_offset (8: 0)) is transmitted to the correlator together with the signals "pn1_on_start" and "pn1_late_start" indicating the start of one cycle of the PN code. The operational state transition of the entire searcher module is the same as the state transition of the PN code generator. The PN code generator maintains an initial state until a start command is received from the digital signal processor 13. When the start command ("start epoch =" 0 ") is generated from the digital signal processor 13, the PN code is generated. When the PN code is generated for one period, the PN code is continuously generated while increasing the offset by one.

When the PN code generator for all possible offsets is finished, the PN code generator returns to the initial state and waits for a start command from the digital signal processor 13.

5 is a structural diagram of an embodiment of an initial searcher for the baseband demodulator of FIG.

As shown in Fig. 5, the correlator in the searcher module has an on-time correlator and a rate-time correlator, and the internal operation is the same except that each PN phase differs by 1/2 chip. The overall structure is a serial searcher structure that sequentially performs all correlations for all possible PN offsets (511 offsets) with two correlators with a difference of half a chip. The on-time correlator performs a correlation between the on-time I and Q signals i_on (5: 0) and q_on (5: 0), which are input signals of the searcher module, and the on-time PN code (pn1_on). The correlation energy for the period is calculated to align the correlation energy (corr_eng (15: 0)) with the correlation energy corr_eng (15: 0) and the offset information (pn_offset (9: 0)) of the PN code on which the correlation is performed. The offset information of the output PN code is 9 bits of the input PN offset information as the Most Significant Bit (MSB), and one bit of the Least Significant Bit (LSB) is on (0) and the rate is transmitted. Correlation energy calculates the result of correlation operation for one period of PN code in the form of sum of square of I signal and square of Q signal. If you implement to facilitate the implementation as shown in [Equation 1].

The late-time correlator correlates between the rate I and Q signals i_late (5: 0), q_late (5: 0), which are input signals of the searcher module, and the rate-time PN code. Computation of the correlation energy for one period by performing the operation, along with the signal output_done indicating the completion of the correlation operation (corr_eng (15: 0)) and the offset information (pn_offset (9) of the PN code on which the correlation operation was performed Pass: 0)) to the sorter. The operations performed internally are the same as on-time correlators.

6 is a state transition diagram of an embodiment of a synchronization tracking module for the baseband demodulator of FIG.

As shown in FIG. 6, the synchronization tracking module includes a PN code generator, a delay-locked loop (DLL), a data demodulation module, and the like for synchronization tracking.

The synchronization tracking module is in an idle state until the start command (start_epoch = '0') from the digital signal processor 13 is in an idle state. When the start command is set from the digital signal processor 13, the initial state is initialized. Transition to). In the initial state, the " seed " of the PN code, the initial start offset of the PN code, etc. are given from the digital signal processing unit 13, the start point of the PN code is moved to the value " pn_offset " . When the start point of the PN code is moved to the set "pn_offset" value, the transition to the traffic state (traffic state), the synchronization tracking and data demodulation process is performed in the traffic state. In the traffic state, the baseband demodulator 12 continuously performs synchronization tracking according to the output of the DLL when there is no separate command from the digital signal processor 13, and performs a function for data demodulation. Whether or not the DLL inside the baseband demodulator 12 tracks the correct offset value (in-lock) can be determined by the digital signal processor 13, and if it is determined that it is lost-lock, the offset After reassigning or transitioning to an idle state for the first time, the digital signal processing unit 13 may implement an algorithm that starts from an initial searching process.

FIG. 7 is a diagram illustrating a delay-locked loop (DLL) structure of a synchronization tracking module for the baseband demodulator of FIG. 2.

As shown in FIG. 7, the synchronization tracking module delays one chip with respect to the late-time I signal input from the data input module, thereby correlating the early signal with the late signal. Compute an error signal from the difference between the two values. The loop filter is implemented as a primary filter and a secondary filter, and can be selected and driven by the digital signal processor 13. The cumulative number of times and the gain value of the loop filter are also controlled by the digital signal processor 13. The value passed through the loop filter is input to the quantizer, which determines the amount of variation in the PN clock for the error signal. Depending on the output of the quantizer, the NCO (Numerically Controlled Oscillator) "advances" or "retards" the PN clock. As the PN clock is changed by the NCO, the sampling time of the data input module is also changed. The correlation cumulative number (num_acc1) was set to "0x1FF (= 511)". When correlation accumulation proceeds for 511 chips, the difference between the late correlation cumulative value and the early correlation cumulative value together with the "output_done" signal is obtained. Output (corr_eng) to loop fiters.

8 is a structural diagram of an embodiment of a data demodulation module for the baseband demodulator of FIG.

As shown in Fig. 8, when the baseband demodulator is operated in the synchronous tracking mode, the data demodulation module demodulates the data carried in the Q channel while the DLL module adjusts the time reference. The data demodulation module is designed to perform correction for the phase error included in the data signal by using the phase information extracted from the pilot signal during data demodulation.

The correlation values for the pilot and data signal components for phase correction are shown in Equation 2 below.

Demodulation of the data compensating for the phase component is shown in Equation 3 below.

The data demodulation module performs a hard decision on the data in units of PN periods and hands it over to the digital signal processor 13, and the digital signal processor 13 determines a bit boundary from a bit string of units in the PN periods. The digital signal processor 13 compares the bit transitions in PN period units and sets 30 PN period data bit units in a buffer and compares them in units of 10 to determine the bit boundary when the bit transitions in the unit of 10 bit streams are less than or equal to a predetermined threshold Decide.

Then, when the bit boundary is determined, the digital signal processor 13 extracts the data bit string of the transmitting end in units of 100 bps by determining data bits from the PN period data of 10 units in a majority vote manner. Using the extracted frame data, the digital signal processor 13 extracts a time mark (time encoder tail) to determine a boundary for one second, and sets the boundary value to the baseband demodulator 12. The baseband demodulator 12 then generates a 1pps signal by counting the PN period based on this threshold.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

In the present invention as described above, by receiving and demodulating time / frequency information received from a satellite in a time / frequency synchronization system using a satellite, the core component system of the time synchronization system can be implemented, and the performance of the system is continuously tested. It can also be used as a tool to do it.

Claims (12)

In the receiving device of the time / frequency synchronization system using a satellite, After low-noise amplification and filtering of the received signal of the IF band input from the outside, down-converted to the baseband signal according to the reference clock transmitted through the phase-locked loop (PLL), and converts the down-converted baseband signal Baseband conversion means for analog / digital (A / D) conversion in accordance with the local oscillation frequency; Under the control of the digital signal processing means, a baseband digital signal transmitted from the baseband converting means, based on the local oscillation frequency for time synchronization, an initial searcher, synchronization tracking, and a basis for performing data demodulation Band demodulation means; And The digital signal processing means for controlling the baseband demodulation means to automatically switch to a searching mode after booting when power is applied or the receiver is reset. Receiving apparatus of the time / frequency synchronization system using a satellite comprising a. The method of claim 1, In the search mode, After driving the initial searcher module inside the baseband demodulating means, the search result for one period of the pseudo noise (PN) code is switched to the synchronization tracking mode for performing synchronization tracking and data demodulation, In the synchronous tracking mode, a process of driving the synchronous tracking module and the data demodulation module inside the baseband demodulation means, demodulating the data bit by bit in units of PN periods from the baseband demodulation means, and determining a 1 second boundary. Receiving apparatus of a time / frequency synchronization system using a satellite, characterized in that performed. The method according to claim 1 or 2, The baseband conversion means, A first filtering unit for filtering an intermediate frequency (IF) signal input from the outside; An amplifier for amplifying the IF signal transmitted through the first filtering means; An orthogonal demodulator for converting an IF signal into baseband in-phase (I) and quadrature (Q) signals according to a reference clock transmitted through the phase locked loop (PLL); Second and third filtering units for low-pass filtering I and Q signals converted to baseband through the orthogonal demodulation unit, respectively; And An analog / digital (A / D) converter for converting the I and Q signals filtered through the second and third filtering units according to the local oscillation frequency. Receiving apparatus of the time / frequency synchronization system using a satellite comprising a. The method of claim 3, wherein The baseband demodulation means, After converting the digital signal input from the baseband conversion means into an offset binary form, which is an output form of the A / D converter, into a two's complement form to be used internally, 2x + 1 ( x: 6-bit two's complement signal is used for internal calculation by converting to the form of an input sample, and the digital sample, which is converted to A / D and input, passes through a decimator, and the initial value is changed according to the rate of chip change. A search module is input to the searcher module, the sync tracking module, and the data demodulation module, and the decimator is on-time and rate-time according to a sampling time fed back from the sync tracking module. time) extracts a sample, extracts an on-time sample according to the sampling time fed back from the synchronization tracking module, and extracts a rate-time sample 16 samples after the sampling time. Receiver of the time / frequency synchronization system using satellites. The method of claim 4, wherein The initial searcher module, On-time PN code (pn1_on) and rate-time PN code synchronized with the PN clock with the PN code generator receiving the "PN seed", the PN clock, and the "start epoch" indicating the starting point of the PN code. (pn1_late), generating a PN code from the given " PN seed ", after generating a PN code of one period, delaying the offset by one chip, and generating another PN code. By performing on possible PN offsets, information about the starting offset of the generated PN code (pn_offset (8: 0)) is passed to the correlator along with the "pn1_on_start" and "pn1_late_start" signals indicating the start of one cycle of the PN code. Receiving apparatus of the time / frequency synchronization system using a satellite. The method of claim 4, wherein The initial searcher module, The PN code generator maintains an initial state until the start command is received from the digital signal processor DSP. When the start command ("start epoch = '0') occurs from the digital signal processor, the PN code generator starts generating the PN code. After the generation of the PN code for a predetermined period, the PN code is continuously generated by increasing the offset by one. When the PN code generation for all possible offsets is completed, the PN code generator is returned to the initial state and the PN code is returned from the digital signal processor. Receiving apparatus for a time / frequency synchronization system using a satellite, characterized in that waiting for the start command. The method of claim 4, wherein The sync tracking module, PN code generator for synchronization tracking, DLL (Delay-Locked Loop), data demodulation module, etc., and idle until the start command (start_epoch = '0') from the digital signal processor If the start command is set from the digital signal processor, the system transitions to an initial state. If the start state is set from the digital signal processor, it sets the "seed" of the PN code, the initial start offset of the PN code, and the like. Is moved to the "pn_offset" value, and then the generation of the PN code starts, and when the start point of the PN code is moved to the set "pn_offset" value, the state transitions to the traffic state. In the traffic state, the baseband demodulation means performs synchronization tracking according to the output of the DLL when there is no separate command from the digital signal processor. Continuously performed, and data demodulation receiver of the time / frequency synchronization system using a satellite, characterized in that for performing a function on. The method of claim 7, wherein The DLL (Delay-Locked Loop), Delay one chip for the late-time I signal input from the data input module to calculate a correlation between the early and late signals, resulting in an error from the difference between the two values. By calculating an error signal, by implementing a loop filter as a primary filter and a secondary filter, the digital signal processor can select and drive the accumulated signal and the gain value of the loop filter. Also, the digital signal processor controls the digital signal processor, and when the value passed through the loop filter is input to a quantizer, the quantizer determines an amount of changing the PN clock with respect to an error signal, and the NCO according to the output of the quantizer. As the PN clock is "advancing" or "retarding" in a (Numerically Controlled Oscillator) and the PN clock is changed by the NCO, the sampling time of the data input module is also changed. Receiving apparatus of a time / frequency synchronization system using a satellite characterized in that the movement. The method of claim 4, wherein The data demodulation module, When the baseband demodulation means is operated in the synchronous tracking mode, the DLL demodulates the data carried in the Q channel while adjusting the time reference, and the phase included in the data signal using the phase information extracted from the pilot signal during data demodulation. And a correction for the error, and performing a hard decision on the data in units of PN periods to pass the data to the digital signal processor. The method of claim 4, wherein The digital signal processing means, A bit boundary is determined from a bit string of PN period units, the bit transitions of the PN period units are compared, and a first predetermined PN period data bit unit is placed in a buffer, and the second predetermined unit is compared by a second predetermined unit. The bit boundary is determined when the bit transition in the bit string unit is equal to or less than a predetermined threshold. When the bit boundary is determined, the data bit is determined by a majority vote method from the PN period data of the second predetermined unit to determine a data bit. Extract a data bit string of the transmitting end of the transmitter, extract a time mark using the extracted frame data, and determine a boundary for one second, and when the boundary value is set in the baseband demodulation means, the baseband The demodulation means generates a 1pps signal by counting the PN period based on this boundary value, so that time / frequency dynamics using satellites can be obtained. Receiving device of existing system. In the reception method of a time / frequency synchronization system using a satellite, A first step of performing a low noise amplification and filtering on a received signal of an intermediate frequency (IF) band inputted from the outside by the baseband converter, and then down converting the received signal into a baseband signal according to a reference clock transmitted through a phase locked loop (PLL); A second step of analog-to-digital (A / D) converting the downconverted baseband signal according to a local oscillation frequency; And A third step of performing initial synchronization, synchronization tracking, and data demodulation on the digitally converted baseband signal according to the local oscillation frequency for time synchronization Receiving method of a time / frequency synchronization system using a satellite comprising a. The method of claim 11, The baseband demodulation unit, Under the control of the digital signal processor, when the power is applied or the receiver is reset, the system automatically switches to the search mode after booting. In the search mode, after driving an initial searcher module inside the baseband demodulator, a synchronization tracking for performing synchronization tracking and data demodulation by looking at a search result for one period of a pseudo noise (PN) code. Mode, In the sync tracking mode, a process of driving a sync tracking module and a data demodulation module inside the baseband demodulator, demodulating data bit by bit in units of PN periods from the baseband demodulator, and determining a 1 second boundary Receiving a time / frequency synchronization system using a satellite, characterized in that performing.