KR20020058484A - Semidonductor device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to reduce total size of a device and to improve integration degree by dividing a memory part and a logic part. CONSTITUTION: The semiconductor device comprises a first semiconductor substrate(30) of a logic part and a second semiconductor substrate(40) of a memory part. The first semiconductor substrate(30) of the logic part further includes a bonding pad(A) and a first contact pad(B). The second semiconductor substrate(40) of the memory part further includes a second contact pad(47a) electrically connected to the first contact pad(B). Also, The size of the second semiconductor substrate(40) is relatively small compared to the size of the first semiconductor substrate(30).

Description

Semiconductor device and manufacturing method therefor {SEMIDONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a semiconductor memory device including a memory part and a logic part, and a method of manufacturing the same.

In general, a memory device and a logic device are formed on one semiconductor substrate, and in particular, as a memory device, a floating gate (FG), a selective gate (SG), and a control gate (Control gate) are formed. When using a flash memory cell having a stack gate structure of a program gate (CG), a gate electrode of a logic element is formed using a conductive layer for a program gate.

1 is a schematic view of a memory / logic composite semiconductor device manufactured according to the prior art, in which a flash memory EEPROM and a logic device are formed on a same semiconductor substrate. A logic element is formed using a pyromium manufacturing method.

As shown in FIG. 1, after forming the field oxide film 12 to isolate the memory region X and the logic region Y on the first semiconductor substrate 11, the memory of the semiconductor substrate 11 is formed. The first polysilicon for the floating gate FG of the flash memory and the second polysilicon for the program gate are formed on the region X, and then the first and second polysilicon are selectively etched to form the program gate 14. ) And the floating gate 13 are formed at the same time.

At this time, the second polysilicon selectively etched on the logic region Y is left to be used as the gate electrode 14a of the logic element, and although not shown in the drawing, between the floating gate 13 and the program gate 14. An oxide film is formed.

After the program gate 14 is formed, impurity ions are implanted into the entire surface of the first semiconductor substrate 11 to form the source / drain 15a of the memory region X and the source / drain 15b of the logic region Y. Form.

Next, after the first interlayer insulating film 16 is formed on the entire surface of the first semiconductor substrate 11 including the memory area X and the logic area Y, the first interlayer insulating film 16 is planarized. Next, the planarized first interlayer insulating layer 16 is selectively etched to form contact holes for metal wiring through which predetermined source / drain 15a and 15b of the memory region X and the logic region Y are exposed. Next, a first metal wiring 17 connected to each of the sources / drains 15a and 15b is formed through the contact hole.

Subsequently, after the second interlayer insulating film 18 is formed on the first metal wiring 17, the second interlayer insulating film 18 is selectively etched to form the first metal wiring 17 and the subsequent second metal wiring. Forming a first via hole for connection, forming a second metal wiring 19 connected to the first metal wiring 17 through the first via hole, and then forming a third via on the front surface including the second metal wiring 19 An interlayer insulating film 20 is formed.

Subsequently, the third interlayer insulating film 20 is selectively etched to form a second via hole for connecting the second metal wiring 19 to the subsequent third metal wiring, and then the second metal wiring ( A third metal wiring 21 connected to 19 is formed.

Subsequently, after the protective film 22 is formed on the entire surface including the third metal wiring 21, the protective film 22 is selectively etched to expose the bonding pad region 23 for the semiconductor package.

In the above-described method of manufacturing a memory / logic composite semiconductor device, since the memory portion and the logic portion are formed on the same semiconductor substrate, when the size of the memory portion increases, the size of the entire element also increases as the size of the entire element increases. There is a problem in developing various applications such as a microcontroller unit (MCU) equipped with a built-in video controller, static random access memory (SRAM), and flash-electrically programmable programmable read-only memory (EEPROM). Because it is applied based on the process, it is impossible to use logic manufacturing techniques for implementing logic parts, which limits the use of various techniques for optimization such as a high speed logic controller.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and the memory portion and the logic portion are formed on different semiconductor substrates, and then stacked up and down to reduce the overall size of the device and to optimize each portion. It is an object of the present invention to provide a method for manufacturing a memory / logic composite semiconductor device.

1 is a device cross-sectional view showing a memory / logic composite semiconductor device manufactured according to the prior art;

2A through 2E are cross-sectional views illustrating a manufacturing process of a memory / logic composite semiconductor device according to an embodiment of the present invention.

3 is a view illustrating a bonding pattern formed on a first semiconductor substrate according to an embodiment of the present invention;

4 illustrates a second bonding pad formed on a second semiconductor substrate according to an embodiment of the present invention;

5 is a plan view of a memory / logic composite semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

30: first semiconductor substrate 39a: bonding pattern

40: second semiconductor substrate 47a: second bonding pad

50: wire bonding 301, 401: protective film

A: bonding pad B: first bonding pad

C: line pattern

A semiconductor device of the present invention for achieving the above object includes a first semiconductor substrate of a logic portion including a bonding pad and a first bonding pad, and a second bonding pad electrically connected to the first bonding pad. And a second semiconductor substrate of a memory portion relatively smaller in size than the first semiconductor substrate.

In the method of manufacturing a semiconductor device of the present invention, forming a first multi-layer metal wiring on a first semiconductor substrate on which a logic portion of the process is completed, selectively etching the uppermost metal wiring of the first multi-layer metal wiring to bond the pad and the first 1. A method of forming a bonding pad, forming a second multilayer metal wiring on a second semiconductor substrate on which a process of a memory part is completed, and selectively etching an uppermost metal wiring of the second multilayer metal wiring to form a second bonding pad. And forming a laminated semiconductor substrate having a rear surface of the second semiconductor substrate facing upward by connecting the first bonding pad and the second bonding pad to each other, and wire bonding the bonding pad to the bonding pad. It is characterized by.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A through 2E are cross-sectional views illustrating a method of manufacturing a memory / logic composite semiconductor device according to an exemplary embodiment of the present invention, FIG. 3 is a plan view of a bonding pattern 39a formed on a first semiconductor substrate, and FIG. 4. Is a plan view of a second bonding pad 47a formed on a second semiconductor substrate.

As shown in FIG. 2A, after the gate oxide film 31 is formed on the first semiconductor substrate 30 for forming the logic device, first polysilicon is deposited on the gate oxide film 31. Next, the first polysilicon is selectively etched to form a plurality of gate electrodes 32. The plurality of gate electrodes 32 may include gate electrodes on a cell region and a peripheral region.

Next, after the source / drain 33 is formed on the first semiconductor substrate 30 by the implantation of high concentration impurity ions using the gate electrode 32 as a mask, the first interlayer insulating film is formed on the entire surface including the gate electrode 32. 34 is formed.

Next, the first interlayer insulating film 34 is selectively etched to form a metal wiring contact hole, and a first metal wiring 35 connected to the source / drain 33 through the contact hole is formed.

Next, after forming the second interlayer insulating film 36 on the first metal wiring 35, the second interlayer insulating film 36 is selectively etched to form the first metal wiring 35 and the subsequent second metal wiring. A first via hole for connecting is formed.

Next, after forming the second metal wiring 37 connected to the first metal wiring 35 through the first via hole and configuring a subsequent logic device, the third interlayer insulating film is formed on the second metal wiring 37. 38 is formed, and the third interlayer insulating film 38 is selectively etched to form a second via hole for connecting the second metal wiring 37 and the subsequent third metal wiring. Next, a third metal wire 39 is formed to be connected to the second metal wire 37 through the second via hole.

As shown in FIG. 2B, the third metal wiring 39 is selectively etched to form a bonding pattern 39a for joining two semiconductor substrates forming a logic region and a subsequent memory region.

In this case, referring to FIG. 3, the bonding pattern 39a selectively etches the third metal wiring 39 formed on the first semiconductor substrate 30 to form a metal between the square bonding pad A and the two semiconductor substrates. The first bonding pads B to which the wirings are bonded are formed, and the bonding pads A and the first bonding pads B are connected by line patterns C having different widths.

As shown in FIG. 3, the bonding pad A is a portion to be wire bonded to package the device, and the size of the square is 50 μm to 90 μm, and the size of the first bonding pad B is square. 10 micrometers-30 micrometers, the line pattern C which connects the bonding pad A and the 1st bonding pad B has a length of 100 micrometers-300 micrometers, and the width is 5 micrometers-20 micrometers.

Next, to insulate and protect the third metal wiring pattern 39a on the front surface including the third metal wiring pattern 39a including the bonding pad A, the first bonding pad B, and the line pattern C. The protective film 301 is deposited.

The protective layer 301 is selectively etched to expose the bonding pads A and the first bonding pads B of the third metal wiring pattern 39a. At this time, when the third metal wiring pattern 39a is exposed, the open portion of the protective film 301 may be bonded to the bonding pad A, the first bonding pad B, and the line pattern of the third metal wiring pattern 39a. 5 micrometers-10 micrometers larger than the size of C).

Secondly, a manufacturing process of the memory device is performed. As shown in FIG. 2C, the floating gate 41 and the program gate 42 are formed on the second semiconductor substrate 40 using the same method as a conventional technique. To form. At this time, a gate oxide film (not shown) is formed between the floating gate 41 and the second semiconductor substrate 40 and between the floating gate 41 and the program gate 42.

Next, the source / drain 43 is formed on the second semiconductor substrate 40 under the floating gate 41 of the stacked structure, and the first interlayer insulating layer 44 is formed on the entire surface of the second semiconductor substrate 40. do.

Next, the first interlayer insulating layer 44 is selectively etched to form a contact hole through which a predetermined portion of the source / drain 43 is exposed, and the first metal wiring connected to the source / drain 43 through the contact hole. Form 45.

Next, a second interlayer insulating film 46 is formed on the first metal wiring 45, and the second interlayer insulating film 46 is selectively etched to connect the first metal wiring 45 and the subsequent second metal wiring. A first via hole is formed to make.

Next, a second metal wiring 47 connected to the first metal wiring 45 through the first via hole is formed.

As shown in FIG. 2D, the second metal wire 47 is selectively etched to form a second bonding pad 47a for bonding the second semiconductor substrate 40 (see FIG. 4).

At this time, the second bonding pad 47a is formed in a square shape, as shown in FIG. 4, and its size is 10 μm to 30 μm.

Next, after forming the protective film 401 to insulate and protect the selectively etched second metal wiring 48, the protective film 401 is selectively etched to expose the second bonding pad 47a. At this time, the open width of the protective film 401 exposing the second bonding pad 47a is larger than the second bonding pad 47a.

As shown in FIG. 2E, the first semiconductor substrate 30 and the second semiconductor substrate 40 are polished to have a thickness of 150 μm to 500 μm using a grind device, and then the first semiconductor substrate. The second semiconductor substrate 40 is stacked on the 30 to form a laminated semiconductor substrate, with the rear surface of the second semiconductor substrate 40 facing upward. In this case, the width of the second semiconductor substrate 40 is 200 μm smaller than that of the first semiconductor substrate 30, and the first bonding pad B of the third metal wiring patterns 39 a of the first semiconductor substrate 30 is smaller than that of the first semiconductor substrate 30. ) And the second bonding pad 47a of the second semiconductor substrate 40 are connected.

Next, a first process in which the first semiconductor substrate 30 and the second semiconductor substrate 40 are thermally processed at 400 ° C. to 500 ° C. to form the third metal wiring 39 on the first semiconductor substrate 30 is performed. The bonding pads B and the second bonding pads 47a formed of the second metal wires 47 of the second semiconductor substrate 40 are electrically connected to each other.

Next, a wire bonding 50 for packaging the semiconductor device is applied to the bonding pad A formed of the third metal wiring 39 on the first semiconductor substrate 30.

5 is a plan view of a memory / logic composite semiconductor device according to an exemplary embodiment of the present invention, in which a first semiconductor substrate 30 is larger than a second semiconductor substrate 40 and a bonding pattern of the first semiconductor substrate 30. The first bonding pad C of 39a and the second bonding pad 47a of the second semiconductor substrate 40 are electrically connected.

The embodiment of the present invention described above is applicable to a manufacturing process of a highly integrated memory device using not only embedded DRAM, SRAM, and flash memory included in a logic device, but also a stacking technology of a semiconductor substrate.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, in the method of manufacturing the memory / logic composite semiconductor device of the present invention, the memory device and the logic device are separated and formed on different semiconductor substrates, and then stacked up and down to reduce the size of the entire device. Since the logic device is formed using the manufacturing process, it is possible to manufacture a high speed logic device and a high density memory device.

Claims (13)

In a semiconductor device, A first semiconductor substrate in a logic portion including a bonding pad and a first bonding pad; And And a second semiconductor substrate of a memory portion, the second bonding pad being electrically connected to the first bonding pad and having a smaller size than the first semiconductor substrate. The method of claim 1, And the bonding pads and the first bonding pads have a square shape having different sizes, and are connected by a line metal pattern to have a dogbone shape. The method of claim 2, The semiconductor device, characterized in that the square size of the bonding pad is 50㎛ ~ 90㎛. The method of claim 2, A semiconductor device, characterized in that the square size of the first bonding pad is 10㎛ ~ 30㎛. The method of claim 2, A line-shaped metal pattern has a length of 100 µm to 300 µm and a width of 5 µm to 20 µm. The method of claim 1, The size of the second bonding pad is a semiconductor device, characterized in that 10㎛ ~ 30㎛. The method of claim 1, And the first semiconductor substrate and the second semiconductor substrate are stacked with the rear surface of the second semiconductor substrate facing upwards, and the total thickness of the semiconductor substrate is 150 µm to 500 µm. The method of claim 1, And the second semiconductor substrate has a size relatively smaller than that of the first semiconductor substrate. In the manufacturing method of a semiconductor device, Forming a first multilayer metal wiring on the first semiconductor substrate on which the processing of the logic portion is completed; Selectively etching an uppermost metal wiring of the first multilayer metal wiring to form a bonding pad and a first bonding pad; Forming a second multilayer metal wiring on the second semiconductor substrate on which the processing of the memory portion is completed; Selectively etching an uppermost metal wiring of the second multilayer metal wiring to form a second bonding pad; Connecting the first bonding pad and the second bonding pad to form a stacked semiconductor substrate having a rear surface of the second semiconductor substrate facing upward; And Wire bonding to the bonding pads Method of manufacturing a semiconductor device comprising the. The method of claim 9, The step of connecting the first bonding pad and the second bonding pad, A method for manufacturing a semiconductor device, comprising performing a thermal step of 400 ° C to 500 ° C. The method of claim 9, Forming the bonding pad and the first bonding pad, Selectively etching an uppermost metal wiring of the first multilayer metal wiring to form a metal wiring pattern; Forming a protective film on the metallization pattern; And Selectively etching the passivation layer to expose the bonding pads and the first bonding pads of the metallization pattern; Method of manufacturing a semiconductor device comprising the. The method of claim 9, And the bonding pads and the first bonding pads are formed in a square shape, and the bonding pads and the first bonding pads are formed in a dogbone shape connected by a line metal pattern. The method of claim 9, Forming the second bonding pad, Selectively etching an uppermost metal wiring of the second multilayer metal wiring to form a metal wiring pattern; Forming a protective film on the metallization pattern; And Selectively etching the passivation layer to expose the first bonding pads of the metallization pattern; Method of manufacturing a semiconductor device comprising the.