KR20020057764A - Method for metal-filling and semiconductor device therefor - Google Patents

Method for metal-filling and semiconductor device therefor Download PDF

Info

Publication number
KR20020057764A
KR20020057764A KR1020010000839A KR20010000839A KR20020057764A KR 20020057764 A KR20020057764 A KR 20020057764A KR 1020010000839 A KR1020010000839 A KR 1020010000839A KR 20010000839 A KR20010000839 A KR 20010000839A KR 20020057764 A KR20020057764 A KR 20020057764A
Authority
KR
South Korea
Prior art keywords
layer
hole
seed
filling
metal
Prior art date
Application number
KR1020010000839A
Other languages
Korean (ko)
Inventor
박지순
Original Assignee
윤종용
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 윤종용, 삼성전자 주식회사 filed Critical 윤종용
Priority to KR1020010000839A priority Critical patent/KR20020057764A/en
Publication of KR20020057764A publication Critical patent/KR20020057764A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for filling a metal into a hole and a semiconductor device formed thereby are provided to reduce an overhang of an entrance of a hole and improve a fill margin by depositing a seed layer. CONSTITUTION: A lower metal layer(210) and an insulating layer(220) including a hole are formed on a semiconductor substrate(200). A barrier layer(230) is formed on an inner wall of the hole and the insulating layer(220). A seed layer(240) is formed on the barrier layer(230). An overhang of an entrance of the hole is reduced by etching a surface of the seed layer(240). The surface of the seed layer(240) is etched by using a radio frequency sputtering etch method. The hole is buried by copper. An upper metal layer(280) is formed on the seed layer(240). The upper metal layer(280) is planarized by performing a chemical mechanical polishing process.

Description

홀의 금속-필링 방법 및 이에 의해 형성된 반도체 소자{Method for metal-filling and semiconductor device therefor}Method for metal-filling holes and semiconductor devices formed thereby

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자의 필 마진(fill margin)을 향상시킬 수 있는 홀의 금속-필링 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a metal-filling method of a hole capable of improving a fill margin of a semiconductor device.

소자와 소자의 연결을 위해서는 절연막 내에 홀을 형성하고 금속으로 홀을 채우는 기술이 적용되고 있다. 예를 들면, 금속 배선, 콘택 형성용 플러그 등에 홀 필링 기술이 사용되고 있다. 반도체 소자의 집적도가 증가함에 따라 금속 배선 형성 방법으로 다마신 공정을 이용하고 있다. 한편, 좁은 배선으로 인해 증가하는 배선 저항을 감소시키고자 하는 요구에 의하여 점차 반도체 소자에 구리 배선을 이용하는 시도가 늘고 있다. 구리는 비저항이 낮고 전자 이동 특성이 우수하여 배선의 단면적이 감소하여도 반도체 메모리 소자의 동작속도를 저하시키지 않고 그의 신뢰성을 유지할 수 있다. 일반적으로 구리 배선 방법은 다마신공정을 이용하여 홀을식각한 후 스퍼터링으로 장벽층과 시드 막을 증착한다. 다음 전기도금 공정을 이용하여 바텀-업 필(bottom-up fill) 방식 또는 컨포멀 필(conformal fill) 방식으로 홀을 구리로 채우고 화학적 기계적 연마(CMP:Chemical Mechanical Polishing)를 진행하여 구리 배선을 형성한다. 그러나, 홀의 종횡비가 높아짐에 따라 스퍼터링을 이용한 시드막 형성 시 홀 입구에 오버-행(over-hang)이 발생하고 구리로 매립된 홀 내에 보이드가 형성되는 문제점이 있었다. 이를 해결하기 위해 스퍼터링 방식 대신 화학 기상 증착법을 이용하여 시드막을 형성시키는 기술이 제안되었다.In order to connect a device with a device, a technology of forming a hole in an insulating film and filling a hole with a metal is applied. For example, hole filling techniques are used for metal wiring, contact forming plugs, and the like. As the degree of integration of semiconductor devices increases, a damascene process is used as a method of forming metal wirings. On the other hand, there is an increasing number of attempts to use copper wiring for semiconductor devices due to the demand for reducing wiring resistance due to narrow wiring. Copper has a low specific resistance and excellent electron transfer characteristics, so that the reliability of the copper can be maintained without reducing the operation speed of the semiconductor memory device even if the cross-sectional area of the wiring is reduced. In general, a copper wiring method uses a damascene process to etch a hole and then deposit a barrier layer and a seed film by sputtering. Next, the copper plating process is performed by filling the hole with copper using bottom-up fill or conformal fill using an electroplating process and performing chemical mechanical polishing (CMP). do. However, as the aspect ratio of the holes increases, there is a problem in that over-hang occurs in the hole inlet and voids are formed in the holes filled with copper when forming the seed film using sputtering. To solve this problem, a technique of forming a seed film using chemical vapor deposition instead of sputtering has been proposed.

도 1a 및 도 1b는 종래 기술에 따라 화학 기상 증착법을 이용하여 구리 배선을 형성하는 방법을 설명하기 위한 단면도이다.1A and 1B are cross-sectional views illustrating a method of forming a copper wiring by using a chemical vapor deposition method according to the prior art.

도 1a에서, 반도체 기판(100)상에 구리로 이루어진 하부 금속층(110) 및 홀을 포함한 절연층(120)을 순차적으로 형성한다. 상기 홀의 내벽 및 절연층(120) 상에 장벽층(130)을 형성한다. 장벽층(130) 상에 화학 기상 증착법을 이용하여 구리 시드막(140)을 형성한다. 참조 번호 150으로 표시된 바와 같이 시드막(140)은 표면 균일도가 불량하다.In FIG. 1A, an insulating layer 120 including holes and a lower metal layer 110 made of copper are sequentially formed on the semiconductor substrate 100. The barrier layer 130 is formed on the inner wall of the hole and the insulating layer 120. The copper seed layer 140 is formed on the barrier layer 130 using chemical vapor deposition. As indicated by the reference numeral 150, the seed film 140 has poor surface uniformity.

도 1b에서, 구리로 홀을 매립하면서 시드막(140) 상에 상부 금속층(160)을 형성한다. CMP(Chemical Mechanical Polishing)를 하여 상부 금속층(160)을 평탄화한다.In FIG. 1B, the upper metal layer 160 is formed on the seed layer 140 while filling the holes with copper. Chemical mechanical polishing (CMP) is performed to planarize the upper metal layer 160.

상술한 바와 같은 화학 기상 증착법을 이용하여 시드막(140)을 형성하는 경우에는, 시드막(140)의 스텝 커버리지 특성이 우수하여 스퍼터링 방식 대비 필 마진이 크게 향상된다. 그러나, 화학 기상 증착법을 이용한 시드막(140)의 증착은 표면 균일도가 불량하여 홀이 매립된 후 홀 중앙에 틈(170)을 발생시키는 문제점이 있다. 따라서, 반도체 메모리 소자의 양호한 전기적 특성을 얻을 수 없다. 예를 들면, 홀 중앙에 존재하는 틈으로 인해 배선저항이 증가되어 반도체 메모리 소자의 동작 속도가 감소된다.When the seed film 140 is formed by using the chemical vapor deposition method as described above, the step coverage of the seed film 140 is excellent, and the fill margin is greatly improved compared to the sputtering method. However, the deposition of the seed film 140 using the chemical vapor deposition method has a problem in that a gap 170 is generated in the center of the hole after the hole is filled due to poor surface uniformity. Therefore, good electrical characteristics of the semiconductor memory device cannot be obtained. For example, a gap in the center of the hole increases wiring resistance, thereby reducing the operating speed of the semiconductor memory device.

따라서, 본 발명이 이루고자 하는 기술적 과제는 금속으로 홀을 매립할 때 홀 내에 존재할 수 있는 틈의 형성을 억제하고 화학 기상 증착법을 이용한 시드막의 증착으로 개선된 홀 입구의 오버-행을 더욱 감소시켜서 필 능력을 향상시킬 수 있는 홀의 금속-필 방법 및 이에 의해 형성된 반도체 소자를 제공하는데 있다.Therefore, the technical problem to be achieved by the present invention is to suppress the formation of gaps that may exist in the hole when filling the hole with metal and to further reduce the over-hang of the hole inlet improved by the deposition of the seed film using the chemical vapor deposition method It is to provide a metal-fill method of a hole and a semiconductor device formed thereby that can improve the capability.

도 1a 및 도 1b는 종래 기술에 따른 구리 배선 형성 방법을 나타낸 것이다.1A and 1B show a copper wiring forming method according to the prior art.

도 2a 내지 도 2c는 본 발명에 따른 구리 배선 형성 방법을 나타낸 것이다.2A to 2C illustrate a method of forming a copper wiring according to the present invention.

본 발명이 이루고자 하는 기술적 과제를 달성하기 위하여, 본 발명은 반도체 기판상에 홀을 포함하는 절연층을 형성하고 홀의 내벽 및 절연층 상면에 장벽층을 형성한다. 장벽층 상에 시드막을 형성하고 시드막 표면이 균일하도록 시드막을 식각한다. 홀을 매립하면서 시드막 상에 금속층을 형성한다.In order to achieve the technical problem to be achieved by the present invention, the present invention forms an insulating layer including a hole on a semiconductor substrate and forms a barrier layer on the inner wall of the hole and the upper surface of the insulating layer. A seed film is formed on the barrier layer, and the seed film is etched so that the seed film surface is uniform. A metal layer is formed on the seed film while filling the holes.

이하, 첨부도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명한다. 그러나, 본 발명의 실시예는 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 본 발명의 실시예는 본 발명의 개시가 완전해지도록 하며, 당 업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위하여 제공되어지는 것이다. 도면 상에서 동일한 부호로 표시된 요소는 동일한 구성 요소를 의미한다. 또한, 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다라고 기재되는 경우에 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제3의 막이 개재되어질 수도 있다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are intended to complete the present disclosure and to provide a more complete description of the present invention to those skilled in the art. Elements denoted by the same reference numerals in the drawings means the same components. In addition, when a film is described as being "on" another film or semiconductor substrate, the film may be present in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween.

이하 도2a 내지 도 2c를 참고로 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to FIGS. 2A to 2C.

도 2a에서 반도체 기판(200)상에 하부 금속층(210) 및 홀을 포함한 절연층(220)을 순차적으로 형성한다. 상기 홀의 내벽 및 절연층(220) 상에 장벽층(230)을 형성한다. 장벽층(230)은 Ta 또는 TaN을 이용하여 형성한다. 장벽층(230) 상에 시드막(240)을 형성한다. 시드막(240)의 형성은 화학 기상 증착법에 의하거나 또는 물리 기상 증착법과 화학 기상 증착법을 순차적으로 진행한다. 화학 기상 증착법에 의한 시드막(240)의 형성은 스퍼터링 방식에 의한 시드막 증착시 홀 입구에 존재하는 오버-행을 개선한다. 증착된 시드막(240)은 참조 번호 250으로 표시된 바와 같이 표면 균일도가 불량하다. 본 발명의 실시예에서는 하부 금속층(210) 및 시드막(240)에 구리를 사용하였다. 그러나, 구리 대신 다른 금속의 사용도 가능하다.In FIG. 2A, an insulating layer 220 including a lower metal layer 210 and a hole is sequentially formed on the semiconductor substrate 200. The barrier layer 230 is formed on the inner wall of the hole and the insulating layer 220. The barrier layer 230 is formed using Ta or TaN. The seed layer 240 is formed on the barrier layer 230. The seed film 240 may be formed by chemical vapor deposition or by physical vapor deposition and chemical vapor deposition. The formation of the seed film 240 by the chemical vapor deposition method improves the over-hang present at the hole inlet when the seed film is deposited by the sputtering method. The deposited seed film 240 has poor surface uniformity as indicated by reference numeral 250. In the exemplary embodiment of the present invention, copper is used for the lower metal layer 210 and the seed layer 240. However, other metals may be used instead of copper.

도 2b에서 시드막(240) 표면에 대해 식각을 진행하여 홀 입구의 오버-행을 더욱 감소시키고(260) 시드막(240)의 표면을 균일하게(270) 한다. 참조번호 245는 식각 후의 시드막을 나타낸다. 식각 방법으로는 예를 들면, 아르곤 가스를 이용한 RF(Radio Frequency) 스퍼터링 식각을 이용한다. 식각 깊이는 시드막 표면으로부터 30Å 이상이 바람직하며 시드막(240)이 전부 제거되지 않을 정도면 충분하다. 이 때, RF 스퍼터링 식각 공정은 시드막(240) 증착과 인시튜(In-situ)로 동일 챔버에서 실시할 수 있거나 또는 다른 챔버에서 실시가 모두 가능하다.In FIG. 2B, the surface of the seed layer 240 is etched to further reduce the over-hang of the hole inlet (260) and evenly 270 the surface of the seed layer 240. Reference numeral 245 denotes a seed film after etching. As an etching method, for example, RF (Radio Frequency) sputtering etching using argon gas is used. The etching depth is preferably 30 μs or more from the surface of the seed film, and may be sufficient so that not all of the seed film 240 is removed. In this case, the RF sputtering etching process may be performed in the same chamber by the seed film 240 deposition and in-situ, or both may be performed in another chamber.

도 2c에서 구리로 홀을 매립하면서 시드막(240) 상에 상부 금속층(280)을 형성하고 CMP(Chemical Mechanical Polishing)를 하여 상부 금속층(280)을 평탄화한다. 구리로 홀을 매립하는 방법은 바텀-업 필 또는 컨퍼멀 필 방식으로(미도시) 진행되는 전기도금 공정을 이용할 수 있다. 결과적으로, 시드막(240)의 표면 식각 공정을 진행함으로써 시드막(240)의 표면이 균일해지고 홀 입구의 오버행을 더욱 감소시킨다. 이후 전기 도금 공정을 진행하여 홀을 매립하는 경우, 홀 내에 존재하는 틈이 억제되고 필 능력도 향상시킬 수 있다. 본 발명의 실시예는 하부 금속층(210)과 상부 금속층(280)을 구비하여 형성되는 금속 배선 형성 방법에 적용하여 설명하였지만, 본 발명은 하부 금속층을 구비하지 않는 반도체 소자에도 적용될 수 있다.In FIG. 2C, the upper metal layer 280 is formed on the seed layer 240 while the holes are filled with copper, and the upper metal layer 280 is planarized by chemical mechanical polishing (CMP). The method of filling holes with copper may use an electroplating process that proceeds in a bottom-up fill or conformal fill method (not shown). As a result, by performing the surface etching process of the seed film 240, the surface of the seed film 240 is uniform and the overhang of the hole inlet is further reduced. After the electroplating process to fill the hole, the gap present in the hole can be suppressed and the peeling ability can be improved. Although the embodiment of the present invention has been described by applying to the metal wiring forming method including the lower metal layer 210 and the upper metal layer 280, the present invention can be applied to a semiconductor device having no lower metal layer.

상술한 바와 같이 본 발명의 금속-필 방법 및 이에 의해 형성되는 반도체 소자에서는 전기도금 공정을 진행하기 전에 시드막 표면을 식각함으로써 시드막의 표면이 균일해지고 홀 입구의 오버-행이 개선된 상태에서 홀을 매립하여 홀 내의 틈의 형성을 억제하고 필 능력을 향상시킬수 있다.As described above, in the metal-fill method of the present invention and the semiconductor device formed thereby, the surface of the seed film is etched by etching the seed film surface before the electroplating process, and the hole is improved in the over-hang of the hole inlet. By filling the gap, the formation of gaps in the holes can be suppressed and the peeling ability can be improved.

Claims (9)

반도체 기판;Semiconductor substrates; 상기 반도체 기판상에 홀을 포함하여 형성된 절연층;An insulating layer including holes on the semiconductor substrate; 상기 홀의 내벽 및 상기 절연층 상에 형성된 장벽층;A barrier layer formed on the inner wall of the hole and the insulating layer; 상기 장벽층 상에 형성되고 식각 공정에 의해 표면이 균일한 시드막; 및A seed film formed on the barrier layer and having a uniform surface by an etching process; And 상기 홀을 매립하면서 상기 시드막 상면에 형성된 금속층을 포함하는 반도체 소자.And a metal layer formed on an upper surface of the seed layer while filling the hole. 반도체 기판을 준비하는 단계;Preparing a semiconductor substrate; 상기 반도체 기판상에 홀을 포함하는 절연층을 형성하는 단계;Forming an insulating layer including a hole on the semiconductor substrate; 상기 홀의 내벽 및 상기 절연층 상에 장벽층을 형성하는 단계;Forming a barrier layer on the inner wall of the hole and the insulating layer; 상기 장벽층 상에 시드막을 형성하는 단계;Forming a seed film on the barrier layer; 표면이 균일하게 상기 시드막의 표면을 소정 깊이 식각하는 단계; 및Etching the surface of the seed film to a predetermined depth with a uniform surface; And 상기 홀을 매립하면서 상기 시드막 상에 금속층을 형성하는 단계를 포함하는 반도체 소자의 홀의 금속-필링 방법.Forming a metal layer on the seed layer while filling the hole. 제2 항에 있어서, 상기 반도체 기판을 준비하는 단계와 상기 절연층을 형성하는 단계 사이에, 상기 반도체 기판상에 하부 금속층을 형성하는 단계를 더 구비하는 반도체 소자의 홀의 금속-필링 방법.The method of claim 2, further comprising forming a lower metal layer on the semiconductor substrate between preparing the semiconductor substrate and forming the insulating layer. 제2 항 또는 제3 항에 있어서, 상기 하부 금속층 및 상기 홀을 매립하는 금속층이 구리로 이루어진 반도체 소자의 홀의 금속-필링 방법.4. The method of claim 2 or 3, wherein the lower metal layer and the metal layer filling the hole are made of copper. 제2 항에 있어서, 상기 시드막의 형성 단계에서 화학 기상 증착법에 의하거나 또는 물리 기상 증착법 과 화학 기상 증착법을 순차적으로 진행하여 상기 시드막을 형성하는 반도체 소자의 홀의 금속-필링 방법.The metal-filling method of claim 2, wherein the seed film is formed by chemical vapor deposition or by performing physical vapor deposition and chemical vapor deposition in sequence. 제2 항에 있어서, 상기 시드막의 표면은 건식 식각에 의해 식각되는 반도체 소자의 홀의 금속-필링 방법.The method of claim 2, wherein the surface of the seed layer is etched by dry etching. 제2 항에 있어서, 상기 시드막의 식각은 RF(Radio Frequency) 스퍼터링 식각에 의해 식각되는 반도체 소자의 금속-필링 방법.The metal-filling method of claim 2, wherein the seed layer is etched by RF (Radio Frequency) sputtering. 제2 항에 있어서, 상기 시드막의 식각은 아르곤 가스를 이용하는 RF 스퍼터링 식각에 의해 식각되는 반도체 소자의 금속-필링 방법.The metal-filling method of claim 2, wherein the seed layer is etched by RF sputter etching using argon gas. 제2 항에 있어서, 상기 소정 깊이는 30Å 이상인 반도체 소자의 금속-필링 방법.The method of claim 2, wherein the predetermined depth is 30 μs or more.
KR1020010000839A 2001-01-06 2001-01-06 Method for metal-filling and semiconductor device therefor KR20020057764A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020010000839A KR20020057764A (en) 2001-01-06 2001-01-06 Method for metal-filling and semiconductor device therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020010000839A KR20020057764A (en) 2001-01-06 2001-01-06 Method for metal-filling and semiconductor device therefor

Publications (1)

Publication Number Publication Date
KR20020057764A true KR20020057764A (en) 2002-07-12

Family

ID=27690990

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010000839A KR20020057764A (en) 2001-01-06 2001-01-06 Method for metal-filling and semiconductor device therefor

Country Status (1)

Country Link
KR (1) KR20020057764A (en)

Similar Documents

Publication Publication Date Title
JPH10189733A (en) Metal coating method for porous dielectric
KR100332118B1 (en) Method of forming a metal wiring in a semiconductor device
KR100301248B1 (en) Method of forming a metal wiring in a semiconductor device
KR100323875B1 (en) Method of forming a metal wiring in a semiconductor device
JP2002026017A (en) Method of forming metal wiring of semiconductor element
JP2001053077A (en) Semiconductor integrated circuit device and its manufacture
KR100333712B1 (en) A method for forming damascene type metal wire in semiconductor device
KR100559030B1 (en) Copper metal wiring formation method of semiconductor device
KR20020076810A (en) Method of fabricating Copper line of semiconductor device
KR100407682B1 (en) A method of forming a metal line in a semiconductor device
US6949472B1 (en) Method for high kinetic energy plasma barrier deposition
KR20020057764A (en) Method for metal-filling and semiconductor device therefor
KR100399909B1 (en) Method of forming inter-metal dielectric in a semiconductor device
KR100307827B1 (en) Metal wiring contact formation method of semiconductor device
KR100552811B1 (en) Metal line formation method of semiconductor device
KR20070066298A (en) Metalline of semiconductor device and method of manufacturing the same
US20090261477A1 (en) Semiconductor device and method of manufacturing the same
KR940011732B1 (en) Manufacturing method of semiconductor device
KR100257154B1 (en) Method of forming metal wiring in semiconductor device
KR101185853B1 (en) Method for forming metal line of semiconductor device
KR100396687B1 (en) Method for forming metal interconnection of semiconductor device
KR20020002911A (en) Method for forming metal line of semiconductor device
KR20030096828A (en) Method for forming copper metal line of semiconductor device
KR100585063B1 (en) Method for forming a metal layer by a selective electroplating
KR101127025B1 (en) Method for Forming Copper Line of Semiconductor Device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application