KR20020057242A - Method for manufacturing thin film transistor lcd - Google Patents
Method for manufacturing thin film transistor lcd Download PDFInfo
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- KR20020057242A KR20020057242A KR1020000087533A KR20000087533A KR20020057242A KR 20020057242 A KR20020057242 A KR 20020057242A KR 1020000087533 A KR1020000087533 A KR 1020000087533A KR 20000087533 A KR20000087533 A KR 20000087533A KR 20020057242 A KR20020057242 A KR 20020057242A
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- layer
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- ohmic contact
- film transistor
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- 239000010409 thin film Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 6
- 239000011521 glass Substances 0.000 claims abstract description 5
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 239000010408 film Substances 0.000 claims description 42
- 150000002500 ions Chemical class 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 239000002904 solvent Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- 229910021419 crystalline silicon Inorganic materials 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- 238000004528 spin coating Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013532 laser treatment Methods 0.000 description 1
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Nonlinear Science (AREA)
- Optics & Photonics (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
본 발명은 액정표시장치의 제조 방법에 관한 것으로, 보다 구체적으로는,오믹 콘택층의 형성을 용이하게 수행할 수 있는 박막 트랜지스터 액정표시장치 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor liquid crystal display device capable of easily forming an ohmic contact layer.
일반적으로, 액정표시장치 어레이 기판의 단위 화소에는 스위칭 소자인 박막 트랜지스터가 배치되어 있다. 상기 박막 트랜지스터는 소오스/드레인 전극과 채널층을 가지고 있는데, 상기 소오스/드레인 전극은 도전율이 우수한 금속으로 되어 있고, 상기 채널 층은 이보다 낮은 도전율을 갖는 결정질 실리콘으로 되어 있다.In general, a thin film transistor, which is a switching element, is disposed on a unit pixel of a liquid crystal display array substrate. The thin film transistor has a source / drain electrode and a channel layer. The source / drain electrode is made of a metal having excellent conductivity, and the channel layer is made of crystalline silicon having a lower conductivity.
이와 같은, 금속 전극과 채널 층이 직접 콘택되는 부분에서는 전도율의 차이가 급격하므로, 이를 완충시키기 위하여 오믹 콘택층이 필요하다. 이러한, 오믹 콘택층을 형성하는 방법으로는 종래에는 결정화된 실리콘 층에 이온을 주입시켜 도핑층을 형성시켰다.In the portion where the metal electrode and the channel layer are in direct contact with each other, the difference in conductivity is sharp, and an ohmic contact layer is required to buffer the difference. As a method of forming the ohmic contact layer, a doping layer is formed by implanting ions into a crystallized silicon layer.
상기에서 이온 주입은 이온 샤우워(Ion Shower)나 이온 플랜터(Ion Implanter)와 같은 플라즈마를 이용하여, 수행하고 있다. 상기 이온 샤우워를 사용하는 경우에는 가속에너지가 낮아 저렴한 비용으로 도핑층을 형성할 수 있고, 상기 이온 임플랜터를 사용하는 경우에는 이온 주입 깊이에 따른 밀도 조절이 가능하여 두께를 용이하게 조절할 수 있다.The ion implantation is performed by using a plasma such as an ion shower or an ion planter. In the case of using the ion shower, the acceleration energy is low to form a doped layer at low cost, and in the case of using the ion implanter, the density can be easily adjusted according to the ion implantation depth. have.
그러나, 상기와 같은 이온 주입법을 사용하여 이온을 가속시키는 경우에는 가속 에너지로 10 ~100Kev정도가 필요한데, 이러한 에너지로 가속된 이온들이 도핑층을 형성하는 과정에서 하부층에 많은 손상을 일으키는 문제점 있다.However, in the case of accelerating ions using the ion implantation method as described above, about 10 to 100 Kev is required as the acceleration energy, and the ions accelerated by such energy cause a lot of damage to the lower layer in the process of forming the doped layer.
또한, 상기와 같은 방법으로 도핑층을 형성하더라도 추가적인 어닐링 공정이 필요한데, 어닐링은 엑시머 레이저나 퍼나시로 하며, 두 장비 모두 고가인 단점이 있다. 이온 샤우워에 비하여 도핑층의 두께 조절이 용이하다는 임플랜터 방법은 원형 마그네트가 필요한데, 상당한 고가여서 제조 단가가 상승하는 문제점이 있다.In addition, even if the doping layer is formed by the above method, an additional annealing process is required. The implanter method, which is easier to control the thickness of the doping layer than the ion shower, requires a circular magnet, but has a problem that the manufacturing cost increases due to a considerable cost.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 오믹 콘택층의 형성을 용이하게 수행할 수 있는 박막 트랜지스터 액정표시장치 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a thin film transistor liquid crystal display device which can easily perform the formation of an ohmic contact layer.
도 1a 내지 도 1d는 본 발명에 따른 박막 트랜지스터 액정표시장치 제조 공정을 도시한 단면도.1A to 1D are cross-sectional views illustrating a manufacturing process of a thin film transistor liquid crystal display device according to the present invention.
도 2a 내지 도 2c는 본 발명에 따른 결정화된 실리콘에 불순물이 확산되는 과정을 도시한 단면도.2A to 2C are cross-sectional views illustrating a process of diffusing impurities into crystallized silicon according to the present invention.
도 3은 본 발명의 또 다른 실시예를 도시한 단면도.3 is a cross-sectional view showing yet another embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10: 비정질 실리콘막 11: 게이트 절연막10: amorphous silicon film 11: gate insulating film
15: 게이트 전극 17: 도핑 막15 gate electrode 17 doped film
19: 오믹 콘택층 19a: 불순물19: ohmic contact layer 19a: impurities
20: 절연막 21: 소오스 전극20: insulating film 21: source electrode
23: 드레인 전극 50: 유리 기판23: drain electrode 50: glass substrate
100: 레이저(laser)빔100: laser beam
상기한 본 발명의 목적을 달성하기 위하여, 본 발명은, 유리 기판 상에 절연막을 증착하는 단계; 상기 절연막 상에 폴리 실리콘층을 증착하는 단계; 상기 게이트 절연막과 게이트 금속을 차례로 증착하고, 이를 패터닝하여 게이트 전극을 형성하는 단계; 상기 도핑층 내의 불순물이 상기 폴리실리콘 층으로 확산되도록, 상기 게이트 전극을 포함한 기판의 전 영역 상에 도핑 막을 도포하는 단계; 상기 결과물을 열처리 하여 상기 게이트 전극 양측의 폴리 실리콘층 부분의 표면에 오믹 콘택층을 형성하는 단계; 상기 오믹 콘택층이 형성된 기판 상에 상기 오믹 콘택층과 콘택되게 소오스/드레인 전극을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object of the present invention, the present invention comprises the steps of depositing an insulating film on a glass substrate; Depositing a polysilicon layer on the insulating film; Depositing the gate insulating film and the gate metal in sequence and patterning the gate insulating film to form a gate electrode; Applying a doping film over the entire area of the substrate including the gate electrode such that impurities in the doping layer diffuse into the polysilicon layer; Heat treating the resultant to form an ohmic contact layer on a surface of a portion of the polysilicon layer on both sides of the gate electrode; And forming a source / drain electrode on the substrate on which the ohmic contact layer is formed to be in contact with the ohmic contact layer.
또한, 본 발명은, 상기 도핑 막은 솔벤트성 용액에 N+또는 P+의 이온을 포함하는 물질이 첨가되어 이루어지고, 상기 도핑 막은 스핑 코팅으로 도포하며, 상기 도핑 막은 100 ~500Å 두께로 도포하고, 상기 열처리는 퍼니스(furnace) 또는 레이저를 이용하여 수행하고, 상기 열처리는 250℃ ~400℃로 수행하는 것을 특징으로 한다.In addition, the present invention, the doping film is made by adding a substance containing ions of N + or P + to the solvent-based solution, the doping film is coated with a sping coating, the doping film is applied to a thickness of 100 ~ 500Å, The heat treatment is performed by using a furnace (furnace) or a laser, the heat treatment is characterized in that carried out at 250 ℃ ~ 400 ℃.
본 발명에 의하면, 도핑 층을 형성할 때 스핀 코팅에 의하여 도핑막을 형성하고, 열처리 또는 레이저를 통하여 어닐링 하여 하부 층에 손상을 줄이고, 공정을 단순화 시킬수 있다.According to the present invention, when the doping layer is formed, the doping film is formed by spin coating, and heat treatment or annealing through a laser can reduce damage to the underlying layer and simplify the process.
이하, 첨부한 도면에 의거하여 본 발명의 바람직한 실시 예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명에 따른 박막 트랜지스터 액정표시장치 제조 공정을 도시한 단면도이다. 도 1a에 도시된 바와 같이, 투명성 절연 기판 즉, 유리 기판(50) 상에 SiO2계의 절연막(20)과 A-Si계의 비정질 실리콘막(10)을 차례로 증착한다. 다음으로, 도 1b에 도시된 바와 같이, 상기 비정질 실리콘막(10)을 결정화(12) 시키고, 이어서 SiNx계의 게이트 절연막(11)과 게이트 금속을 순차적으로 증착한다음, 이를 패터닝하여 게이트 전극(15)을 형성한다. 그런 다음, 상기 게이트 전극(15)이 형성된 기판(50) 상에 POCl3혹은, 휘발성이 강한 용액에 N+, P+이온을 첨가 시킨 도핑막(17)을 스핀 코팅 방법으로 도포한다.1A to 1D are cross-sectional views illustrating a process of manufacturing a thin film transistor liquid crystal display device according to the present invention. As shown in FIG. 1A, an SiO 2 insulating film 20 and an A-Si amorphous silicon film 10 are sequentially deposited on a transparent insulating substrate, that is, a glass substrate 50. Next, as shown in FIG. 1B, the amorphous silicon film 10 is crystallized 12, and then a SiN x -based gate insulating film 11 and a gate metal are sequentially deposited and then patterned to form a gate electrode. (15) is formed. Then, a doping film 17 in which N + and P + ions are added to POCl 3 or a highly volatile solution is applied onto the substrate 50 on which the gate electrode 15 is formed by spin coating.
도 1c에 도시된 바와 같이, 상기 도포된 도핑 막(17)을, 퍼나시(furnace) 또는 레이저를 이용하여 열처리를 하면, 상기 도핑 막(17)이 결정질 실리콘층(12)에 확산되면서 오믹 콘택층(19)이 형성된다.As shown in FIG. 1C, when the coated doped film 17 is heat-treated using a furnace or a laser, the doped film 17 is diffused into the crystalline silicon layer 12 while being in ohmic contact. Layer 19 is formed.
그리고 나서, 도 1d에 도시된 바와 같이, 소오스/드레인 전극(21, 23)을 형성함으로써, 폴리 실리콘 박막 트랜지스터를 완성한다. 이때, 상기 소오스/드레인(21, 23)의 형성시에는 게이트 전극(15) 상에 남아 있던 도핑막이 스퍼터링에 의해 제거된다.Then, as shown in FIG. 1D, the source / drain electrodes 21 and 23 are formed, thereby completing the polysilicon thin film transistor. At this time, when the source / drain 21 and 23 are formed, the doped film remaining on the gate electrode 15 is removed by sputtering.
도 2a 내지 도 2c는 본 발명에 따른 결정화된 실리콘막 상에 도핑 용액이 확산되는 과정을 도시한 단면도로서, 도 2a에 도시된 바와 같이, 비정질 실리콘막(10)이 결정질 실리콘막(12)이되면 표면이 거칠어지고, 갈라지는데, 도핑 막(19)은 도 2b에 도시된 바와 같이 결정질 실리콘막(10) 틈사이로 침투되고, 상기 게이트/드레인 전극(21,23)을 형성하기 위한 스퍼터링 공정에서 더욱 깊게 확산된다.2A to 2C are cross-sectional views illustrating a process of diffusing a doping solution onto a crystallized silicon film according to the present invention. As shown in FIG. 2A, an amorphous silicon film 10 is formed of a crystalline silicon film 12. When the surface is roughened and cracked, the doped film 19 is penetrated between the gaps of the crystalline silicon film 10, as shown in FIG. Spreads deeper.
도 3은 본 발명의 또 다른 실시예를 도시한 단면도로서, 도시한 바와 같이, 다른 실시예는 도 2a 내지 도 2c와 동일한 증착 과정을 거치지만, 여기에서는 비정질 실리콘막(10)을 레이저나 열처리에 의하여 결정화 시키지 않고, 즉, 비정질인 상태에서 도핑 막(17)을 스핀 코팅으로 도포하고, 레이저를 기판의 후면부에서 조사한다. 상기 레이저는 기판 상에 증착된 비정질 실리콘막(10)을 결정질 실리콘막으로 변화시키는 동시에 도핑막(17)을 상기 결정질 실리콘막상에 확산시켜 오믹 콘택층을 형성할 수 있게된다. 그러면, 열처리 공정이 줄어 들게 되어, 열에 의하여 기판이 받는 손상을 제거 할 수 있으며, 공정이 단순화되는 잇점이 있다.3 is a cross-sectional view showing another embodiment of the present invention. As shown in the drawing, another embodiment undergoes the same deposition process as in FIGS. 2A to 2C, but here, the amorphous silicon film 10 is subjected to laser or heat treatment. The doped film 17 is applied by spin coating without crystallization, that is, in an amorphous state, and the laser is irradiated from the rear side of the substrate. The laser converts the amorphous silicon film 10 deposited on the substrate into a crystalline silicon film and simultaneously diffuses the doped film 17 onto the crystalline silicon film to form an ohmic contact layer. Then, the heat treatment process is reduced, so that the damage to the substrate due to heat can be removed, and the process is simplified.
이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, 도핑 막을 스핀 코팅에 의하여 도포한다음, 열처리를 통해 오믹 콘택층을 형성할 수 있어, 상기 오믹콘택층의 형성을 용이하게 수행할 수 있음은 물론, 이온 주입을 이용하지 않는 것에 기인해서, 플라즈마에 의한 기판의 손상을 방지할 수 있다.As described in detail above, according to the present invention, the doped film may be coated by spin coating, and then the ohmic contact layer may be formed through heat treatment, thereby easily forming the ohmic contact layer. Due to not using ion implantation, damage to the substrate due to plasma can be prevented.
또한, 비정질 실리콘을 결정화 하지않고, 도핑 막을 증착하여 동시에 결정화 및 오믹 콘택층을 형성할 수도 있으며, 이경우에는 공정 시간과 수율 증대를 확보할 수 있다.In addition, a crystallization and an ohmic contact layer may be simultaneously formed by depositing a doped film without crystallizing the amorphous silicon, in which case it is possible to secure an increase in process time and yield.
이하, 본 발명은 그 요지가 일탈하지 않는 범위에서, 다양하게 변경하여 실시할 수 있다.Hereinafter, this invention can be implemented in various changes, in the range which does not deviate from the summary.
Claims (6)
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960026922A (en) * | 1994-12-22 | 1996-07-22 | 양승택 | Ohmic electrode formation method of compound semiconductor device |
| KR19980064220A (en) * | 1996-12-20 | 1998-10-07 | 로더리히네테부쉬 | MOOS transistor |
| KR20000043908A (en) * | 1998-12-29 | 2000-07-15 | 김영환 | Method for forming contact of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960026922A (en) * | 1994-12-22 | 1996-07-22 | 양승택 | Ohmic electrode formation method of compound semiconductor device |
| KR19980064220A (en) * | 1996-12-20 | 1998-10-07 | 로더리히네테부쉬 | MOOS transistor |
| KR20000043908A (en) * | 1998-12-29 | 2000-07-15 | 김영환 | Method for forming contact of semiconductor device |
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