KR20020056691A - Method for obtaining margin of etching process - Google Patents

Abstract

PURPOSE: A method of securing etching process margin in a liquid crystal display panel is provided to form a data line or a gate of the liquid crystal display panel using CO/Al/CO films to improve etching margin and etching yield when a via hole is etched. CONSTITUTION: CO/Al/CO films are laminated as a gate electrode layer(4) on a glass substrate(2) and patterned through photolithography. A gate insulating layer, a data line, and a pixel electrode are formed on the CO/Al/CO films. Since the CO/Al/CO films are used as the gate electrode layer, etch selectivity of the gate insulating layer and the gate electrode is secured when a via hole(12) is dry-etched.

Description

METHODS FOR OBTAINING MARGIN OF ETCHING PROCESS}

The present invention relates to a method of securing an etching process margin in a liquid crystal display panel, and more particularly, to a method of securing an etching process margin in a liquid crystal display panel laminated with a triple layer of CO / Al / CO with a gate electrode and data metal. will be.

By using a Co / Al / Co triple layer as a data line or gate line in the TFT via hole dry etching process, the selectivity for SF6 gas of SiNx (or SiON) and Co is obtained to obtain a process margin close to infinity. Can be improved.

In order to have n + a-Si and excellent ohmic contact resistance, Co / Al / Co triple layer data line is applied.

In the process of using SF6 as an etching gas in a semiconductor process, by using a Co / Al / Co triple layer thin film electrode, very good selectivity and electrical conductivity can be obtained.

It can be used to improve the interfacial properties of the Si / metal electrode in the semiconductor process and to implement a low-resistance electrode.

When using current Mo / Al / Mo data lines in the via-hole dry etching process, the upper Mo and passivation of SiNx, which is a passivation for SF6 gas, are poor, which can cause a large amount of defects in array and cell processes. . In addition, when SiNx and Al having excellent selectivity are used as a single layer, hillock, electromigration, and the like occur, thereby degrading device characteristics.

Conventional methods for producing Co-silicides with very low ohmic contact resistance on n + a-Si are deposited on n + a-Si and then heat-treated. Co-silicide was formed. However, this method has a lot of problems, such as the remaining amount of Co in the subsequent process to remove the remaining Co to proceed to the subsequent process.

The data lines (Mo / Al / Mo) in the current staggered TFT array process are in contact with n + a-Si at the bottom and ITO at the top, respectively. In this stack of data lines, n + a-Si makes contact with Mo, resulting in a relatively high ohmic contact resistance. In addition, the presence of fine defects at this interface has a higher ohmic contact resistance, causing pixel defects and the like, which may cause a decrease in yield.

When using a single layer of Co as a data line, there are many limitations due to the relatively high resistance of Co.

The present invention has been made to improve as described above, a liquid crystal display for improving the etching margin and etching yield during the via hole etching process by stacking a triple layer of CO / Al / CO with the data line or gate metal of the liquid crystal display panel The purpose of the panel is to provide a method of securing an etching process margin.

1 is a side view for showing an etching process in a liquid crystal display panel according to an embodiment of the present invention;

2 is a side view illustrating a gate pad part in a liquid crystal display panel according to another exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

2: glass substrate, 4: gate metal,

6: gate insulator, 8: SiNx,

10: source / drain electrode, 12: ITO,

14: Passivation layer.

According to a preferred embodiment of the present invention for achieving the above object, by applying a stack of three layers of cobalt / aluminum / cobalt to the gate electrode thin film on the upper surface of the glass substrate, the gate insulator, data line and In the liquid crystal display panel, a method of securing an etching process margin is provided, wherein the pixel electrode is deposited to obtain an etching margin and an optimum etching yield during the etching process of the panel.

Meanwhile, according to another exemplary embodiment of the present invention, a gate electrode thin film and a gate insulator are stacked on an upper surface of a glass substrate, and a data line formed of three layers of cobalt / aluminum / cobalt is formed on an upper surface of the glass substrate, and a pixel electrode is formed on the upper surface of the glass substrate. The deposition process provides a method of securing an etching process margin in a liquid crystal display panel, characterized in that the etching margin and the optimum etching yield can be obtained during the etching process of the panel.

Preferably, a cobalt metal layer (Co / Al / Co) is used to improve passivation or selectivity with the active layer in the via hole dry etching process, and the bottom layer of the data line is n + a-Si or Contact with Si to form metal silicide at its interface upon final annealing without further heat treatment.

In addition, a method of securing an etching process margin in a liquid crystal display panel is formed by forming a metal silicide at an interface between Si and a metal by using a heat treatment or an excimer laser in order to lower ohmic contact resistance.

Hereinafter, a method of securing an etching process margin in a liquid crystal display panel according to the present invention will be described in detail with reference to the accompanying drawings.

The method proposed in the present invention uses Co / Al / Co as a data line to form Co-silicide during final annealing after patterning and etching, so there is no problem of Co residual. Therefore, in the present invention, a Co / Al / Co triple layer stack can be applied.

In addition, Co / Al / Co triple stack can be applied to the via hole dry etching process by using the excellent etching selectivity between the data line upper layer Co and SiNx, thereby obtaining an optimal process method.

On the other hand, the top Co of the data line is in contact with passivation SiNx and the bottom Co is in contact with n + a-Si. In the final annealing process, Co-silicide is formed on the n + a-Si layer with excellent interfacial properties and very low ohmic contact resistance. Passivation SiNx, on the other hand, is thermally stable with Co and no silicide is formed.

Co has very good chemical resistance to current ITO etchant, so using Co / Al / Co stacks as data lines can greatly reduce data open by ITO etchant attack.

1 is a side view illustrating an etching process in a liquid crystal display panel according to an embodiment of the present invention, and FIG. 2 is a side view illustrating a gate pad part in a liquid crystal display panel according to another embodiment of the present invention.

Referring to this, when the Co / Al / Co triple layer proposed in the present invention is applied to the TFT array process, the process sequence is as follows.

First, the gate metal 4 is deposited on the glass substrate 2 (1 chamber), and photolithography, wet or dry etching is performed. In this case, the gate metal 4 is coated with Co / Al / Co or Al / Co. In this case, the etching selectivity of SiNx (8, or SiON; 6) and the gate metal 4, which are excellent gate insulating layers 6, may be obtained when the subsequent via holes 12 are dry-etched.

Next, active vapor deposition, photolithography and etching are performed.

Thereafter, source / drain electrode 10 deposition (Co / Al / Co), photolithography, etching (sword / drain, n +); The source / drain 10 etching process may be either a dry etching process or a dry etching process using Cl-based gas at room temperature to 50 ° C (one step etching process may be applied).

Next, passivation deposition (14), photolithography, and via dry etching are performed, which mainly uses SF6 as the source gas during the dry etching of the via holes (12). Co deposited as an upper layer of the data line is etched into the SF6 gas. Or not attacked. Therefore, by using Co as the upper layer of the data line, the etching selectivity of the SiNx / data line (Co / Al / Co; 10) excellent in the dry etching of the via hole 12 may be obtained, thereby ensuring sufficient process margin.

In addition, by using Co / Al / Co or Al / Co as the gate metal 4, excellent via hole 12 dry etching selectivity of the gate pad portion 18 can be obtained, thereby obtaining sufficient process margin.

After that, a pixel electrode (ITO) 20 is deposited, and photolithography and etching are performed. Since Co has excellent chemical durability against ITO etchant, defects such as data open due to etchant attack during ITO etching are performed. Can be significantly lowered.

Finally, annealing (formation of good ohmic contact between Co, the bottom layer of the data line, and n + a-Si, the active layer); When contacted with amorphous silicon and Co, it is formed in the Co-silicide (16) n + a-Si / Co interface having a very low ohmic contact resistance by a slight heat treatment.

Since the temperature is about 300 ° C. in the final annealing process, Co-silicide 16 having very low ohmic contact resistance and excellent interfacial properties is formed at the interface between Co, the bottom layer of the data line, and active n + a-Si. .

In summary, the case where Co / Al / Co is applied to the gate line 4 and the data line 10 is shown, respectively, and the TFT and the gate pad part 18 are dry when the via hole dry etching process is performed. The upper cobalt (Co) attack does not occur due to the etching source gas SF6, thereby greatly improving the electrical characteristics of the device. This is due to Co's excellent selectivity to SF6 plasma net P.

Cobalt (Co) has a very good physical and chemical durability against pixel electrode (ITO) wet etchant, thus greatly reducing the data line opening that occurs during ITO etching, thereby greatly improving yield.

In the dry etching process using the F-based gas as an etching gas, Co thin film electrode is applied to realize excellent selectivity of SiNx (8), Si, SiON (6) and the like.

Meanwhile, the data line 10 may be applied to a 4 mask process using excellent selectivity in dry etching and via dry etching.

In addition, it can be used as a substitute electrode material having excellent electrical conductivity, ohmic contact, and excellent selectivity in a TFT or semiconductor process.

Therefore, according to the method of securing the etching process margin in the liquid crystal display panel according to the present invention, by securing the etching margin and the optimal etching receipe during the via hole dry etching process, it is possible to obtain various effects such as accumulation of process technology, yield improvement, etc. In addition, it is possible to secure an excellent etching process margin in the four mask process.

Claims (5)

A stack of three layers of cobalt / aluminum / cobalt is applied to the gate electrode thin film on the upper surface of the glass substrate, and the gate insulator, the data line, and the pixel electrode are deposited on the upper surface, so that the etching margin and the optimum etching yield are obtained during the etching process of the panel. A method of securing an etching process margin in a liquid crystal display panel, characterized by being obtained. On the upper surface of the glass substrate, a gate electrode thin film and a gate insulator are stacked, and a data line laminated with three layers of cobalt / aluminum / cobalt is formed on the upper surface of the glass substrate, and pixel electrodes are deposited on the upper surface to etch margin during the etching process of the panel. A method of securing an etching process margin in a liquid crystal display panel, characterized in that the optimum etching yield can be obtained. The method of claim 1, wherein a cobalt metal layer (Co / Al / Co) is used to improve passivation or selectivity with the active layer in the via hole dry etching process. . 2. The liquid crystal display panel of claim 1, wherein the bottom layer of the data line is in contact with n + a-Si or Si so that metal silicide is formed at an interface thereof during final annealing without additional heat treatment. Way. The method of claim 1, wherein metal silicide is formed at an interface between Si and the metal by using a heat treatment or an excimer laser to lower ohmic contact resistance.