KR20020056664A - Method for forming element isolation film of semicoductor device - Google Patents

Method for forming element isolation film of semicoductor device Download PDF

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Publication number
KR20020056664A
KR20020056664A KR1020000086066A KR20000086066A KR20020056664A KR 20020056664 A KR20020056664 A KR 20020056664A KR 1020000086066 A KR1020000086066 A KR 1020000086066A KR 20000086066 A KR20000086066 A KR 20000086066A KR 20020056664 A KR20020056664 A KR 20020056664A
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South Korea
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pad
layer
trench
oxide film
film
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KR1020000086066A
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Korean (ko)
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손상호
김정수
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박종섭
주식회사 하이닉스반도체
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Priority to KR1020000086066A priority Critical patent/KR20020056664A/en
Publication of KR20020056664A publication Critical patent/KR20020056664A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: A method for fabricating an isolation layer of a semiconductor device is provided to prevent a hump between a drain current and a gate voltage and a phenomenon that a gate oxide layer is deteriorated, by preventing a thinning phenomenon of the gate oxide layer in a moat portion even after several cleaning processes are performed. CONSTITUTION: A pad oxide layer(12), a pad polysilicon layer and a pad nitride layer are sequentially formed on a semiconductor substrate(11). A photoresist layer pattern for a trench mask is formed on the nitride layer. The pad nitride layer, the pad polysilicon layer, the pad oxide layer and the semiconductor substrate are selectively patterned to form a trench in the semiconductor substrate by using the photoresist layer pattern as a mask. The photoresist layer pattern is eliminated and the sidewall of the trench is oxidized. A high density plasma oxide layer for filling the trench is formed on the pad oxide layer including the trench. The high density plasma oxide layer is blanket-etched and planarized to be left only in the trench. The pad nitride layer and the pad polysilicon layer are eliminated.

Description

반도체소자의 소자분리막 형성방법{Method for forming element isolation film of semicoductor device}Method for forming element isolation film of semicoductor device

본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 트렌치프로파일을 개선하여 가장자리부의 효과 및 게이트산화막의 열화를 방지할 수 있는 반도체소자의 반도체소자의 소자분리막 형성방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device of a semiconductor device capable of improving the trench profile to prevent the effect of the edge portion and deterioration of the gate oxide film.

현재 적용하고 있는 얕은 트렌치 소자분리방법(STI; Shallow Trench Isolation)는 모우트(Moat)부근에서 게이트산화막이 얇아져서 드레인전류-게이트 전압(Id-Vg)상에서의 험프(Hump) 및 게이트산화막의 특성 열화가 생길 수 있는 소지가 많다.Shallow Trench Isolation (STI), which is currently applied, is characterized by the characteristics of Hump and gate oxide on drain current-gate voltage (Id-Vg) due to thinning of gate oxide near moat. There is a lot of potential for deterioration.

그래서, 모우트(Moat)부근에서 게이트산화막이 얇아지는 문제를 개선함 으로써 위에서 언급한 문제들이 생길 소지를 없앨 수 있으므로 얕은 트렌치소자 분리(STI) 공정을 이용하는 모든 반도체에 적용할 수 있다.Therefore, the problem of the above-mentioned problems can be eliminated by improving the problem of thinning the gate oxide film near the moat, so that it can be applied to all semiconductors using a shallow trench isolation (STI) process.

이러한 관점에서, 종래기술에 따른 반도체소자의 소자분리막 형성방법을 도 1 내지 2를 참조하여 설명하면 다음과 같다.In this regard, the method of forming a device isolation film of a semiconductor device according to the prior art will be described with reference to FIGS.

도 1 내지 도 2는 종래기술에 따른 반도체소자의 소자분리막 형성방법을 설명하기 위한 공정단면도이다.1 to 2 are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the prior art.

도 3은 종래기술에 따른 반도체소자의 소자분리막에 있어서의 드레인전류- 게이트전압((Id-Vg)간의 험프특성을 나타낸 그래프이다.3 is a graph showing hump characteristics between the drain current and the gate voltage (Id-Vg) in a device isolation film of a semiconductor device according to the prior art.

종래기술에 따른 반도체소자의 소자분리막 형성방법은, 도 1에 도시된 바와같이, 먼저 반도체기판(1)상에 패드산화막(2)과 패드질화막(3)을 순차적으로 증착한다.In the method of forming a device isolation film of a semiconductor device according to the prior art, as illustrated in FIG. 1, first, a pad oxide film 2 and a pad nitride film 3 are sequentially deposited on a semiconductor substrate 1.

이어서, 상기 패드질화막(3)상에 트렌치마스크용 감광막패턴(미도시)을 형성하고, 이를 마스크로 상기 패드질화막(3)과 패드산화막(2) 및 반도체기판(1)을 선택적으로 패터닝하여 상기 반도체기판(1)내에 트렌치(4)를 형성한다.Subsequently, a trench mask photoresist pattern (not shown) is formed on the pad nitride layer 3, and the pad nitride layer 3, the pad oxide layer 2, and the semiconductor substrate 1 are selectively patterned using the mask. The trench 4 is formed in the semiconductor substrate 1.

그다음, 상기 감광막패턴(미도시)을 제거하고, 상기 트렌치(4)의 바닥 및 측면에 측벽산화막(5)와 선형산화막(6)을 형성한다.Next, the photoresist pattern (not shown) is removed and sidewall oxide film 5 and linear oxide film 6 are formed on the bottom and side surfaces of the trench 4.

이어서, 상기 선형산화막(6)을 포함한 상기 질화막(3)의 상면에 상기 트렌치(4)을 매립하는 고밀도플라즈마산화막(7)을 형성하고, 이를 CMP공정을 사용하여 전면식각하여 상기 트렌치(4)에만 남도록한다.Subsequently, a high-density plasma oxide film 7 filling the trench 4 is formed on the upper surface of the nitride film 3 including the linear oxide film 6, and the entire surface is etched by using a CMP process. Should only remain.

그다음, 도 2에 도시된 바와같이, 상기 CMP공정을 진행한후 포스트세정공정 을 진행한다음 상기 질화막(3)을 제거한다.Next, as shown in FIG. 2, the CMP process is performed, followed by a post-cleaning process, and then the nitride film 3 is removed.

이어서, 문턱전압스크린산화공정전에 프리세정공정 및 게이트산화막공정전 프리세정공정등을 진행한다. 이때, 상기 선형산화막(6)쪽의 식각속도가 빠른 관계로 상기 선형산화막(6)쪽이 움푹 파이는 모우트(moat)(A)가 생기게 된다.Subsequently, a preclean process before the threshold voltage screen oxidation process, a preclean process before the gate oxide film process, and the like are performed. At this time, the etch rate of the linear oxide film 6 is high, and thus, a moat A is formed in which the linear oxide film 6 is pitted.

상기한 바와같이, 종래기술에 있어서는, 도2에서와 같이, 모우트가 생기게 됨으로 인해 게이트산화막의 씨닝(Thinning) 현상이 생기고, 이로 인해 도3에서와 같은 드레인전류- 게이트전압((Id-Vg)상에서의 험프 및 게이트산화막의 특성열화등이 생길 수 있다.As described above, in the prior art, as shown in FIG. 2, a moat is generated, which causes thinning of the gate oxide film, which causes the drain current-gate voltage ((Id-Vg) as shown in FIG. May cause deterioration of the characteristics of the hump and the gate oxide film.

그러므로, 게이트산화막의 씨닝을 방지하는 공정의 개발이 절실히 요구된다.Therefore, development of a process for preventing thinning of the gate oxide film is urgently required.

이에, 본 발명은 상기 종래기술의 제반문제점을 해결하기 위하여 안출한 것으로서, 본 발명의 목적은 게이트산화막의 씨닝을 방지하여 게이트산화막의 특성열화를 방지하고자한 반도체소자의 소자분리막 형성방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, an object of the present invention to provide a method for forming a device isolation film of a semiconductor device to prevent the deterioration of the characteristics of the gate oxide film by preventing the thinning of the gate oxide film. have.

도 1 내지 도 2는 종래기술에 따른 반도체소자의 소자분리막 형성방법을 설명하기 위한 공정단면도이다.1 to 2 are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the prior art.

도 3은 종래기술에 따른 반도체소자의 소자분리막에 있어서의 드레인전류- 게이트전압((Id-Vg)간의 험프특성을 나타낸 그래프이다.3 is a graph showing hump characteristics between the drain current and the gate voltage (Id-Vg) in a device isolation film of a semiconductor device according to the prior art.

도 4 내지 도 7은 본 발명에 따른 반도체소자의 소자분리막 형성방법을 설명하기 위한 공정단면도이다.4 to 7 are process cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to the present invention.

[도면부호의설명][Description of Drawing Reference]

11 : 반도체기판 12 : 패드산화막11 semiconductor substrate 12 pad oxide film

13 : 패드폴리실리콘층 14 : 패드질화막13 pad polysilicon layer 14 pad nitride film

15 : 트렌치 16 : 열산화막15: trench 16: thermal oxide film

17 : 선형산화막 18 : 고밀도플라즈마산화막17: linear oxide film 18: high density plasma oxide film

상기 목적을 달성하기 위한 본 발명은, 반도체기판상에 패드산화막과 패드폴리실리콘층 및 패드질화막을 순차적으로 형성하는 단계; 상기 패드질화막상에 트렌치마스크용 감광막패턴을 형성하는 단계; 상기 감광막패턴을 마스크로 상기 패드질화막, 패드폴리실리콘층 및 패드산화막, 반도체기판을 선택적으로 패터닝하여 상기 반도체기판내에 트렌치를 형성하는 단계; 상기 감광막패턴을 제거하고 트렌치측벽을 측벽산화처리하는 단계; 상기 트렌치를 포함한 패드질화막상에 상기 트렌치를 매립하는 고밀도플라즈마산화막을 형성하는 단계; 상기 고밀도플라즈마 산화막을 전면식각하여 트렌치에만 남도록 평탄화시키는 단계; 상기 패드질화막과 패드폴리실리콘층을 제거하는 단계;를 포함하여 이루어지는 것을 특징으로한다.The present invention for achieving the above object, the step of sequentially forming a pad oxide film, a pad polysilicon layer and a pad nitride film on a semiconductor substrate; Forming a photoresist pattern for a trench mask on the pad nitride film; Selectively trenching the pad nitride layer, the pad polysilicon layer, the pad oxide layer, and the semiconductor substrate using the photoresist pattern as a mask to form a trench in the semiconductor substrate; Removing the photoresist pattern and subjecting the trench sidewalls to sidewall oxidation; Forming a dense plasma oxide film filling the trench on a pad nitride film including the trench; Planarizing the high-density plasma oxide layer by etching the entire surface so that only the trench remains; And removing the pad nitride film and the pad polysilicon layer.

이하, 본 발명에 따른 반도체소자의 소자분리막 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a device isolation film of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 4 내지 도 7은 본 발명에 따른 반도체소자의 소자분리막 형성방법을 설명하기 위한 공정단면도이다.4 to 7 are process cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to the present invention.

본 발명에 따른 반도체소자의 소자분리막 형성방법은, 도 4에 도시된 바와같이, 먼저 반도체기판(11)상에 패드산화막(12)과 패드폴리실리콘층(13)을 순차적으로 증착한다.In the method of forming a device isolation film of a semiconductor device according to the present invention, as shown in FIG. 4, first, a pad oxide film 12 and a pad polysilicon layer 13 are sequentially deposited on a semiconductor substrate 11.

이어서, 상기 패드폴리실리콘층(13)상에 패드질화막(14)을 증착하고, 상기 패드질화막(14)상에 트렌치마스크용 감광막패턴(미도시)을 형성하고, 이를 마스크로 상기 패드질화막(14), 패드폴리실리콘층(13), 패드산화막(11) 및반도체기판(11)을 선택적으로 패터닝하여 상기 반도체기판(11)내에 트렌치(15)를 형성한다.Subsequently, a pad nitride layer 14 is deposited on the pad polysilicon layer 13, and a photoresist layer pattern (not shown) for trench mask is formed on the pad nitride layer 14, and the pad nitride layer 14 is formed using a mask. ), The pad polysilicon layer 13, the pad oxide film 11 and the semiconductor substrate 11 are selectively patterned to form a trench 15 in the semiconductor substrate 11.

그다음, 도 5에 도시된 바와같이, 상기 감광막패턴(미도시)을 제거하고, 상기 트렌치(15)의 바닥 및 측면에 측벽산화공정을 실시한다. 이때, 상기 측벽산화 공정시에 상기 패드폴리 실리콘층(13)이 산화되면서 열산화막(Thermal oxide)(16)이 높게 성장한다.Next, as shown in FIG. 5, the photoresist pattern (not shown) is removed, and a sidewall oxidation process is performed on the bottom and side surfaces of the trench 15. At this time, as the pad polysilicon layer 13 is oxidized during the sidewall oxidation process, the thermal oxide layer 16 grows high.

이어서, 도 6에 도시된 바와같이, 상기 열산화막(16)의 표면상에 선형산화막(17)을 형성하고, 전체 구조의 상면에 상기 트렌치(15)를 매립하는 고밀도플라즈마산화막(18)을 형성한다.Subsequently, as shown in FIG. 6, a linear oxide film 17 is formed on the surface of the thermal oxide film 16, and a high-density plasma oxide film 18 filling the trench 15 is formed on the upper surface of the entire structure. do.

그다음, 상기 고밀도플라즈마산화막(18)를 CMP공정을 이용하여 전면식각하여 상기 트렌치(15)에만 남도록 한다.Then, the high-density plasma oxide film 18 is etched entirely using a CMP process so as to remain only in the trench 15.

이어서, 상기 패드산화막(12)이 노출될때까지 패드질화막(14)과 패드폴리실리콘층(13)을 완전히 제거한다. 이때, 패드산화막(12)은 게이트산화막으로 사용한다.Subsequently, the pad nitride layer 14 and the pad polysilicon layer 13 are completely removed until the pad oxide layer 12 is exposed. In this case, the pad oxide film 12 is used as a gate oxide film.

상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 소자분리막 형성 방법에 있어서는, 종래기술에서와 같은 여러 세정공정을 거치게 되더라도 모우트 (moat)부분에 있는 게이트산화막의 씨닝현상은 나타나지 않는다.As described above, in the method of forming a device isolation film of a semiconductor device according to the present invention, thinning of the gate oxide film in the moat portion does not appear even after various cleaning processes as in the prior art.

따라서, 본 발명은 종래기술에서 나타나는 게이트산화막의 씨닝현상으로인해 드레인전류-게이트전압간의 험프 및 게이트산화막의 열화현상을 방지할 수 있다.Therefore, the present invention can prevent the hump and the deterioration of the gate oxide film between the drain current and the gate voltage due to the thinning phenomenon of the gate oxide film shown in the prior art.

그러므로, 본 발명에 따른 반도체소자의 소자분리막 형성방법은 더 안정된 소자 특성을 구현할 수 있다.Therefore, the device isolation film forming method of the semiconductor device according to the present invention can implement more stable device characteristics.

Claims (5)

반도체기판상에 패드산화막과 패드폴리실리콘층 및 패드질화막을 순차적으로 형성하는 단계;Sequentially forming a pad oxide film, a pad polysilicon layer, and a pad nitride film on the semiconductor substrate; 상기 패드질화막상에 트렌치마스크용 감광막패턴을 형성하는 단계;Forming a photoresist pattern for a trench mask on the pad nitride film; 상기 감광막패턴을 마스크로 상기 패드질화막, 패드폴리실리콘층 및 패드산화막, 반도체기판을 선택적으로 패터닝하여 상기 반도체기판내에 트렌치를 형성하는 단계;Selectively trenching the pad nitride layer, the pad polysilicon layer, the pad oxide layer, and the semiconductor substrate using the photoresist pattern as a mask to form a trench in the semiconductor substrate; 상기 감광막패턴을 제거하고 트렌치측벽을 측벽산화처리하는 단계;Removing the photoresist pattern and subjecting the trench sidewalls to sidewall oxidation; 상기 트렌치를 포함한 패드질화막상에 상기 트렌치를 매립하는 고밀도플라즈마산화막을 형성하는 단계;Forming a dense plasma oxide film filling the trench on a pad nitride film including the trench; 상기 고밀도플라즈마산화막을 전면식각하여 트렌치에만 남도록 평탄화시키는 단계;Planarizing the dense plasma oxide layer by etching the entire surface of the high density plasma oxide film; 상기 패드질화막과 패드폴리실리콘층을 제거하는 단계;를 포함하여 이루어지는 것을 특징으로하는 반도체소자의 소자분리막 형성방법.Removing the pad nitride layer and the pad polysilicon layer; and forming a device isolation film for the semiconductor device. 제1항에 있어서, 상기 측벽산화처리시에 상기 폴리실리콘층도 산화되는 것을 특징으로하는 반도체소자의 소자분리막 형성방법.The method of claim 1, wherein the polysilicon layer is also oxidized in the sidewall oxidation process. 제1항에 있어서, 상기 측벽산화를 통해 열산화막이 트렌치의 측벽위로 높게형성되는 것을 특징으로하는 반도체소자의 소자분리막 형성방법.The method of claim 1, wherein a thermal oxide layer is formed on the sidewalls of the trench through the sidewall oxidation. 제1항에 있어서, 상기 고밀도플라즈마산화막의 평탄화는 CMP공정을 이용하여 이루어지는 것을 특징으로하는 반도체소자의 소자분리막 형성방법.The method of claim 1, wherein the planarization of the high density plasma oxide film is performed using a CMP process. 제1항에 있어서, 상기 측벽산화처리후에 선형산화막 형성공정을 더 포함하는 것을 특징으로하는 반도체소자의 소자분리막 형성방법.The method of claim 1, further comprising: forming a linear oxide film after the sidewall oxidation treatment.
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JPH10340950A (en) * 1997-04-11 1998-12-22 Mitsubishi Electric Corp Trench isolation structure and fabrication thereof
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KR20000027703A (en) * 1998-10-29 2000-05-15 김규현 Method for manufacturing a shallow trench for a semiconductor device isolation
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Patent Citations (8)

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Publication number Priority date Publication date Assignee Title
JPH104136A (en) * 1996-04-15 1998-01-06 Samsung Electron Co Ltd Method for forming element isolating film of semiconductor device
JPH10340950A (en) * 1997-04-11 1998-12-22 Mitsubishi Electric Corp Trench isolation structure and fabrication thereof
KR19980084107A (en) * 1997-05-21 1998-12-05 문정환 Device isolation method of semiconductor device
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