KR20020056660A - Method for forming fine pattern of semiconductor device - Google Patents

Method for forming fine pattern of semiconductor device Download PDF

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KR20020056660A
KR20020056660A KR1020000086062A KR20000086062A KR20020056660A KR 20020056660 A KR20020056660 A KR 20020056660A KR 1020000086062 A KR1020000086062 A KR 1020000086062A KR 20000086062 A KR20000086062 A KR 20000086062A KR 20020056660 A KR20020056660 A KR 20020056660A
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pattern
electron beam
forming
semiconductor device
fine pattern
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KR1020000086062A
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Korean (ko)
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KR100376882B1 (en
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정성웅
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박종섭
주식회사 하이닉스반도체
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Electron Beam Exposure (AREA)

Abstract

PURPOSE: A method for fabricating a fine pattern of a semiconductor device is provided to increase the area of a storage node, by forming a pattern using a ArF photoresist layer so that an electron beam is radiated to a wafer. CONSTITUTION: A photoresist layer is applied on the wafer. A baking process is performed regarding the photoresist layer at a temperature lower than 150 deg.C. The photoresist layer is patterned through an exposure and development process. An electron beam is radiated to the wafer having a patterned photoresist layer to fix the pattern. The exposure process is performed by using a laser beam having a wavelength of 100-248 nanometer.

Description

반도체소자의 미세패턴 형성방법{Method for forming fine pattern of semiconductor device}Method for forming fine pattern of semiconductor device

본 발명은 반도체소자의 미세패턴 형성방법에 관한 것으로, 보다 상세하게는 ArF노광계를 이용한 반도체소자의 미세패턴 형성방법에 관한 것이다.The present invention relates to a method of forming a fine pattern of a semiconductor device, and more particularly to a method of forming a fine pattern of a semiconductor device using an ArF exposure system.

최근에는 반도체 소자의 집적도가 증가되면서 소자의 설계에 필요한 디자인 룰이 점점 감소하고 있다. KrF 노광계로 가능한 패턴크기는 0.13㎛ 정도이다. 따라서, 패턴크기를 더욱 감소시키기 위한 해결책으로 제시되고 있는 노광계가 ArF 이다. 512M 이상 급의 디램이나 0.13㎛이하급의 로직소자의 사용이 예상되는 ArF 감광막의 문제점을 개선할 수 있는 방향을 제시하여 새로운 감광막의 개발없이 현재의 시스템을 사용하여 미세 패턴 형성을 위한 ArF 도입 시기의 감축에 도움이 될 것으로 생각된다.Recently, as the degree of integration of semiconductor devices has increased, design rules required for the design of devices have gradually decreased. The pattern size possible with the KrF exposure system is about 0.13 m. Therefore, ArF is proposed as a solution for further reducing the pattern size. Introduces the direction to improve the problems of ArF photoresist film, which is expected to use DRAM of 512M or more class or logic element of 0.13㎛ or less, and introduce ArF to form fine pattern using current system without developing new photoresist film It is thought to help in the reduction.

현재 가장 문제가 되고 있는 ArF 노광법은 ArF용으로 개발된 감광막을 사용하여 노광을 하고 이를 SEM 조사로 확인할 때 감광막의 크기(dimension)이 감소한다는 것이다. 이는 감광막이 전자빔에 약하기 때문인데, 이와 같은 현상으로 인해 CD를 확인하기 위한 조사(inspection)를 진행한 부분과 그렇지 못한 부분의 CD 변화(variation)가 발생하게 되어 실제 제품을 제조하는 방법으로는 적합치 못하다.The ArF exposure method, which is the most problematic problem at present, is to reduce the size of the photoresist film when exposure is performed using the photoresist film developed for ArF and confirmed by SEM irradiation. This is because the photoresist film is weak to the electron beam, and this phenomenon causes CD variation of the part which has been inspected to check the CD and the part which is not, which is not suitable as a method of manufacturing the actual product. Can not do it.

또한, 현재 개발중인 소자와 같이 100nm 가량의 미세패턴을 노광해야 하는 경우에는 라인(line)의 경우 폭(width)에 비해 스페이스(space)가 다소 넓은 것이 소자의 동작에 유리한 경향이 있다.In addition, when the micropattern of about 100 nm needs to be exposed, such as a device currently under development, a slightly wider space than the width of the line tends to be advantageous for the operation of the device.

이렇게 폭(width)에 비해 스페이스가 다소 넓은 미세패턴을 형성하고자 하는 경우에 마스크제작만으로 이를 실현시키기는 다소 어려움이 따른다.In the case of forming a fine pattern in which the space is somewhat wider than the width, it is difficult to realize this only by manufacturing the mask.

특히, 스토리지노드 마스크(storage node mask)와 같은 경우는 캐패시터의 크기를 증가시키기 위해 홀(hole)의 크기를 될수 있는대로 크게 형성시켜야 하는데, 이 마스크를 만들고 이를 이용하여 패턴을 형성하는 기술에는 많은 문제를 안고 있다.In particular, in the case of a storage node mask, the size of a hole must be made as large as possible to increase the size of a capacitor. There are many techniques for forming this pattern and forming a pattern using the mask. I have a problem.

이에 본 발명은 상기 종래기술의 문제점을 해결하기 위하여 안출한 것으로써, 본 발명의 목적은 ArF 노광계를 사용하여 반도체소자의 특성을 개선 시키고자한 반도체소자의 미세패턴 형성방법을 제공함에 있다.Accordingly, the present invention has been made to solve the problems of the prior art, an object of the present invention to provide a method for forming a fine pattern of a semiconductor device to improve the characteristics of the semiconductor device using an ArF exposure system.

또한, 본 발명의 다른 목적은, ArF 노광계를 사용하여 패턴 형성 신뢰도를 향상시킬 수 있는 반도체소자의 미세패턴 형성방법을 제공함에 있다.Another object of the present invention is to provide a method of forming a fine pattern of a semiconductor device capable of improving pattern formation reliability using an ArF exposure system.

도 1은 본 발명에 따른 반도체소자의 미세패턴 형성방법에 있어서, 감광막의 노광직후의 도면이다.1 is a view immediately after exposure of a photosensitive film in the method of forming a fine pattern of a semiconductor device according to the present invention.

도 2는 본 발명에 따른 반도체소자의 미세패턴 형성방법에 있어서, 도1에서 의 감광막을 전자빔 조사후의 도면이다.FIG. 2 is a view of the photosensitive film of FIG. 1 after electron beam irradiation in the method for forming a fine pattern of a semiconductor device according to the present invention.

[도면부호의설명][Description of Drawing Reference]

1, 1a : PR이 제거된 부분 10, 10a : PR이 남은 부분1, 1a: PR part removed 10, 10a: PR part left

상기 목적을 달성하기 위한 본 발명은, 웨이퍼상에 감광막을 도포하는 단계;The present invention for achieving the above object, the step of applying a photosensitive film on the wafer;

상기 감광막을 베이킹처리하는 단계; 상기 감광막을 노광 및 현상공정을 통해 패터닝하는 단계; 및 전자빔을 상기 감광막이 패터닝된 웨이퍼에 조사하여 패턴을 고정시키는 단계;를 포함하여 이루어지는 것을 특징으로한다.Baking the photosensitive film; Patterning the photosensitive film through an exposure and development process; And irradiating an electron beam onto the photosensitive film-patterned wafer to fix the pattern.

이하, 본 발명에 따른 반도체소자의 미세패턴 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a fine pattern of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

본 발명에 따른 반도체소자의 미세패턴 형성방법은, 먼저, 웨이퍼상에 감광막을 도포하고, 150℃ 미만의 온도에서 베이킹(baking)한 후 100~248nm 의 파장을 가진 레이저로 상기 감광막을 조사한후 노광 및 현상공정을 진행하는 경우, 후속 전자빔(E-beam)을 상기 감광막(photoresist)에 조사하여 패턴의 형성을 고정시킨다.In the method for forming a micropattern of a semiconductor device according to the present invention, first, a photosensitive film is coated on a wafer, baked at a temperature of less than 150 ° C, and then irradiated with the photosensitive film with a laser having a wavelength of 100 to 248 nm. And in the case of the development process, a subsequent electron beam (E-beam) is irradiated to the photoresist to fix the formation of the pattern.

이때, 상기 감광막을 노광한후 4~15keV의 가속전압을 가진 전자빔(E-beam을 이용하여 감광막(photoresist)이 패터닝된 웨이퍼의 전면을 조사한다.At this time, after exposing the photoresist, the entire surface of the photoresist patterned wafer is irradiated using an electron beam (E-beam) having an acceleration voltage of 4 to 15 keV.

또한, 전자빔을 조사하여 수축이 일어나는 감광막을 사용하여 패턴을 형성할 수도 있다.In addition, a pattern may be formed using a photosensitive film in which shrinkage occurs by irradiating an electron beam.

그리고, 스토리지노드의 면적을 증가시키기 위해 수축이 일어난 상기감광막(photoresist)을 이용하여 패턴을 형성하고, 상기 전자빔 조건에 의해 웨이퍼에 전자빔 조사를 진행하여 패턴을 형성할 수도 있다.In addition, a pattern may be formed using the photoresist in which shrinkage occurs to increase an area of the storage node, and a pattern may be formed by performing electron beam irradiation on a wafer under the electron beam conditions.

또한, 비트라인의 스페이스를 증가시켜 비트라인의 기생캐패시턴스(bit line parasitic capacitance)를 감소시키기 위해 수축된 감광막(photoresist)을 이용하여 패턴을 형성하고, 상기 전자빔조건에 의해 웨이퍼에 전자빔 조사를 진행하여 패턴을 형성할 수도 있다.In addition, in order to reduce the bit line parasitic capacitance of the bit line by increasing the space of the bit line, a pattern is formed using a contracted photoresist, and electron beam irradiation is performed on the wafer under the electron beam conditions. You may form a pattern.

더욱이, 전자빔에 의해 수축이 일어나는 감광막을 베이킹처리한후 ArF 노광계를 이용하여 패턴을 형성하는 경우에 전자빔을 이용하여 웨이퍼를 전면조사를 실시하여 패턴을 형성할 수도 있다.Further, when the photoresist film shrinks due to the electron beam is baked, and the pattern is formed using an ArF exposure system, the wafer may be subjected to full irradiation using the electron beam to form a pattern.

그다음, 상기 반도체웨이퍼를 CD SEM조사를 실시한다.Then, the semiconductor wafer is subjected to CD SEM irradiation.

이를 이용한 부가적인 실시예를 도 1 및 도 2를 참조하여 설명하면 다음과 같다.An additional embodiment using the same will be described with reference to FIGS. 1 and 2 as follows.

도 1은 본 발명에 따른 반도체소자의 미세패턴 형성방법에 있어서, 감광막의 노광직후의 도면이다.1 is a view immediately after exposure of a photosensitive film in the method of forming a fine pattern of a semiconductor device according to the present invention.

도 2는 본 발명에 따른 반도체소자의 미세패턴 형성방법에 있어서, 도1에서 의 감광막을 전자빔 조사후의 도면이다.FIG. 2 is a view of the photosensitive film of FIG. 1 after electron beam irradiation in the method for forming a fine pattern of a semiconductor device according to the present invention.

도 1 및 2에 도시된 바와같이, 캐패시터의 하부전극용 스토리지노드나 비트라인과 같은 경우에, 식각공정을 진행하여 제거되어야 할 영역의 부분(1)(1a)이 남아야 할 영역의 다른 부분(10)(10a)에 비해 큰 것이 소자의 동작에 유리하다.As shown in FIGS. 1 and 2, in the case of a storage node for a lower electrode or a bit line of a capacitor, another portion of a region in which portions (1) 1a of regions to be removed by an etching process are to be left ( Larger than 10) 10a is advantageous for the operation of the device.

먼저, 스토리지노드의 경우에, 캐패시터의 용량을 결정하는 스토리지노드면적이 증가되고, 비트라인의 경우에, 비트라인의 캐패시턴스가 감소되므로써 신호전달 속도가 향상된다.First, in the case of the storage node, the storage node area for determining the capacity of the capacitor is increased, and in the case of the bit line, the signal transfer speed is improved by reducing the capacitance of the bit line.

이 경우, 마스크나 노광 조건에 의해 실현시킬 수도 있으나, 공정마진측면에서 상대적으로 불리하게 된다. 특히, 스토리지노드의 경우는 크기확보와 공정 마진이 서로 트레이드오프(trade-off) 관계에 있으므로 면적확보를 하는 것이 매우 어려운 일이다.In this case, although it can implement | achieve by a mask or exposure conditions, it becomes comparatively disadvantageous in terms of process margin. In particular, in the case of a storage node, it is very difficult to secure an area because size and process margins are traded off.

따라서, 전자빔(E-beam) 조사를 이용하여 스토리지노드의 경우는 면적을 확보하고, 비트라인의 경우는 스페이스 증가를 자연스럽게 이룰 수 있다.Therefore, the area of the storage node can be secured by using the E-beam irradiation, and the space can be increased naturally in the case of the bit line.

반도체 소자의 미세패턴을 보다 원활하게 형성시키는 방법으로서 ArF 감광 막과 같이, 전자빔에 조사되었을 때 수축(shrinkage)을 일으키는 감광막에 대한 적용 및 응용에 대하여 제시하면 다음과 같다.As a method of forming a fine pattern of a semiconductor device more smoothly, the application and application of a photoresist film that causes shrinkage when irradiated with an electron beam, such as an ArF photoresist film, are as follows.

먼저, ArF 감광막과 같이, 전자빔(E-beam)이 조사되었을 때 수축 (shrinkage)을 일으키는 감광막을 가지고 CD SEM을 이용하여 라인폭 및 스페이스 를 모니터링(monitoring)하면, 전자빔(E-beam)이 조사된 부분과 실제 패턴이 형성된 나머지 대부분의 다른 영역들과는 다른 결과를 얻게 된다.First, like an ArF photosensitive film, when a line width and a space are monitored using a CD SEM with a photosensitive film that causes shrinkage when an electron beam is irradiated, the electron beam is irradiated. The result is different from most of the other areas where the part and the actual pattern are formed.

따라서, 전자빔 스캐닝(E-beam scanning) 장비를 이용하여 웨이퍼의 전면을 조사한 후 CD SEM 장비를 이용하여 조사하게 되면, 이미 수축(shrinkage)이 일어난 후에 모니터링하게 되므로 CD SEM으로 측정한 샘플(sample)이 다른 부분과 동일한 결과를 나타나게 된다.Therefore, if the front surface of the wafer is irradiated using an electron beam scanning (E-beam scanning) apparatus and then irradiated using a CD SEM apparatus, the sample is measured by CD SEM since it is monitored after shrinkage has already occurred. This produces the same results as the other parts.

스토리지노드(Storage node)와 같이 노광되어 제거되어야 할 부분의 크기를크게 해야 할 경우에 매우 유용한 방법이다. 이 역시 전자빔(E-beam)의 조사를 웨이퍼의 전면에 진행하여 스페이스를 증가시키면 캐패시터 면적의 증가에 기여 하게 된다.This is very useful when you need to increase the size of the area that needs to be exposed and removed, such as a storage node. This also contributes to the increase of the capacitor area if the electron beam (E-beam) irradiation to the front of the wafer to increase the space.

상기한 바와같이, 본 발명에 따른 반도체소자의 미세패턴 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the method of forming a fine pattern of a semiconductor device according to the present invention has the following effects.

본 발명에 따른 반도체소자의 미세패턴 형성방법에 있어서는, ArF 감광막을 이용하여 패턴을 형성하여 웨이퍼를 전자빔조사하므로써 스토리지노드의 면적을 증가시킬 수 있다.In the method for forming a fine pattern of a semiconductor device according to the present invention, the area of the storage node can be increased by forming a pattern using an ArF photosensitive film and irradiating the wafer with an electron beam.

또한, 본 발명에 따른 반도체소자의 미세패턴 형성방법은, ArF노광계를 사용하므로써 패턴 형성의 신뢰도를 향상시킬 수 있다.Further, in the method of forming a fine pattern of a semiconductor device according to the present invention, the reliability of pattern formation can be improved by using an ArF exposure system.

Claims (6)

웨이퍼상에 감광막을 도포하는 단계;Applying a photosensitive film on the wafer; 상기 감광막을 베이킹처리하는 단계;Baking the photosensitive film; 상기 감광막을 노광 및 현상공정을 통해 패터닝하는 단계; 및Patterning the photosensitive film through an exposure and development process; And 전자빔을 상기 감광막이 패터닝된 웨이퍼에 조사하여 패턴을 고정시키는 단계;를 포함하여 이루어지는 것을 특징으로하는 반도체소자의 미세패턴 형성방법.And irradiating an electron beam onto the photosensitive film-patterned wafer to fix the pattern. 상기 베이킹처리는 150℃ 미만의 온도에서 진행하는 것을 특징으로하는 반도체소자의 미세패턴 형성방법.The baking process is a method of forming a fine pattern of a semiconductor device, characterized in that proceeding at a temperature of less than 150 ℃. 상기 노광공정은 100~248nm 의 파장을 가진 레이저를 이용하여 진행하는 것을 특징으로하는 반도체소자의 미세패턴 형성방법.The exposure process is a fine pattern forming method of a semiconductor device, characterized in that for proceeding using a laser having a wavelength of 100 ~ 248nm. 상기 전자빔 조사는 4~15keV의 가속전압을 가진 전자빔(E-beam을 이용하여 진행하는 것을 특징으로하는 반도체소자의 미세패턴 형성방법.The electron beam irradiation is a method of forming a fine pattern of a semiconductor device, characterized in that the electron beam (E-beam) having an acceleration voltage of 4 ~ 15keV. 제1항에 있어서, 스토리지노드의 면적을 증가시키기 위해 전자빔이 조사된 상기 감광막(photoresist)을 이용하여 패턴을 형성하고, 상기 전자빔 조건에 의해 웨이퍼에 전자빔 조사를 진행하여 패턴을 형성하는 단계를 더 포함하는 것을 특징으로하는 반도체소자의 미세패턴 형성방법.The method of claim 1, further comprising forming a pattern by using the photoresist to which the electron beam is irradiated to increase the area of the storage node, and forming a pattern by performing electron beam irradiation on the wafer under the electron beam condition. Method of forming a fine pattern of a semiconductor device comprising a. 제1항에 있어서, 비트라인의 스페이스를 증가시켜 비트라인의 기생캐패 시턴스를 감소시키기 위해 수축된 감광막(photoresist)을 이용하여 패턴을 형성하고, 상기 전자빔조건에 의해 웨이퍼에 전자빔 조사를 진행하여 패턴을 형성하는 단계를 더 포함하는 것을 특징으로하는 반도체소자의 미세패턴 형성방법.The method of claim 1, wherein a pattern is formed by using a contracted photoresist to increase the space of the bit line to reduce the parasitic capacitance of the bit line, and subject the wafer to electron beam irradiation under the electron beam conditions. The method of forming a fine pattern of a semiconductor device, characterized in that it further comprises forming a pattern.
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