KR20020055474A - Substrate structure for integrated systems and the method for manufacturing - Google Patents

Abstract

PURPOSE: A circuit structure for an integration system is provided capable of integrating an active device, for examples transistor and diode, along with a high performance SAW device having a high stability(Q) by using a presented integration circuit process. CONSTITUTION: A circuit board is divided into a device area(a) and a SAW area(b). An amorphous insulation film(20) is deposited on a mono crystallized circuit board(10). An active area(30) is defined at a desired portion on the amorphous insulation film(20). A first insulation film(40) is stacked in a rest area for insulation. A second insulation film(60) is formed on the first insulation film(40) to insulate a first metal layer from a device. A gate electrode(50) is formed on the active area(30). A first metal layer pattern(70) is coated on a contact portion in which the second insulation film(60) is etched. A third insulation film(80) is formed on an entire surface of the first metal film pattern. A second metal film pattern(90) is formed on a via-contact portion coming in contact with the first metal film pattern(70) and on the mono crystallized circuit board(10).

Description

Substrate structure for integrated system and its manufacturing method {SUBSTRATE STRUCTURE FOR INTEGRATED SYSTEMS AND THE METHOD FOR MANUFACTURING}

The present invention relates to a substrate (or wafer) structure for an integrated system and a method of manufacturing the same. More specifically, the present invention relates to a substrate structure for integrating a passive element and an active element using a surface acoustic wave (SAW) and a single chip, and a manufacturing method for integrating the same.

Recently, research on S.O.C (System On Chip), which forms a system by integrating a large number of devices in one chip, is known to create a great added value, and many studies have been conducted. In particular, in order to construct an integrated system in the RF domain, it is necessary to configure an active component such as a transistor and an inductor or a filter having a high stability (Q) value on one chip.

In the conventional method, the inductor having a relatively high stability (Q) value can be integrated in one chip through the development of the metal process and the increase in the resistance of the substrate. However, when the frequency is increased, it is inevitably affected by the substrate. Transistors made on the same substrate were also affected by the substrate and degraded.

In this sense, the use of an insulating substrate can greatly improve the high frequency characteristics. High frequency (RF) systems require high performance filters, and the most promising ones are SAW filters with high stability (Q) values. The filter is connected to the IC in the form of discrete components in a system containing an existing intermediate frequency (IF) or RF, or manufactured on another piezoelectric wafer and then connected to the IC through bonding to be used for implementing the system. However, there have been problems in miniaturization, process complexity, and device yield, respectively.

In other words, research on bonding SAW filters to IC chips has been published considering that passive devices and active devices such as SAW cannot be integrated directly on the same substrate. However, the process is complicated and difficult, and the wire required for the package has been published. A problem arises in that the process must be doubled.

Accordingly, the present invention is to solve the above problems, the present invention can integrate the active device (transistor and diode) and the high performance SAW device having a high stability (Q) value using the existing integrated circuit process. It is an object of the present invention to provide a structure of a substrate for an integrated system.

In addition, an object of the present invention is to provide a substrate manufacturing method for an integrated system capable of integrating IC and SAW devices by using the substrate structure.

As a technical idea for achieving the above object of the present invention, the present invention forms an amorphous oxide film on a single crystal substrate having both insulation and piezoelectricity, and forms a single crystal silicon film thereon, thereby forming an active element (transistor and diode) on one substrate. A substrate structure for fabricating a high performance SAW device, and a substrate structure for an integrated system integrating transistors and SAW devices on the substrate and a method of manufacturing the same are provided.

1 is a cross-sectional view showing the structure of a single crystal substrate having both piezoelectricity and insulation in accordance with the present invention;

FIG. 2 is a cross-sectional view of a structure in which transistors and SAW devices are integrated together on the same chip using the single crystal substrate shown in FIG.

3A to 3D are cross-sectional views of a process for forming the structure of the single crystal substrate shown in FIG. 1 using the smart cut method.

4A to 4D are cross-sectional views for forming a structure of the single crystal substrate shown in FIG. 1 using an SOI wafer as a device wafer.

5A to 5D are cross-sectional views of a process for integrating a transistor and a SAW device together on the single crystal substrate shown in FIG.

6A to 6C are cross-sectional views illustrating a wafer structure in which a silicon film is directly provided on a single crystal substrate having both piezoelectric and insulating properties as shown in FIG. 1 without a buffer layer.

<Description of the symbols for the main parts of the drawings>

10: single crystal substrate 20: amorphous insulating film

30: single crystal silicon film 35: active region

40: first insulating film 50: gate electrode

60: second insulating film 70: first metal film pattern

80: third insulating film 90: second metal film pattern

100: silicon substrate 120: silicon area

140, 160, 220: oxide film 200: amorphous silicon film

Hereinafter, with reference to the accompanying drawings, the configuration and operation of the embodiment of the present invention will be described in detail.

1 is a cross-sectional view showing the structure of a single crystal substrate having both piezoelectricity and insulation in accordance with the present invention.

Referring to the structure of FIG. 1, an amorphous insulating film 20 is formed on a single crystal substrate 10, and a single crystal silicon film 30 is stacked on the single crystal substrate 10.

The single crystal substrate 10 may have piezoelectricity and insulation at the same time. For example, a quartz having a crystal direction of the substrate exhibiting piezoelectricity may be used.

The amorphous insulating film 20 is formed on the piezoelectric single crystal substrate 10 because it serves as a kind of buffer layer that can solve the difference in thermal expansion coefficient between the piezoelectric single crystal substrate 10 and the silicon film. Used.

In addition, the amorphous insulating film 20 serving as the buffer layer absorbs the difference in thermal expansion coefficient between the single crystal silicon film 30 and the single crystal substrate 10 in a silicon integrated circuit process so that the fabrication is smoothly performed.

As for the thickness of the amorphous insulating film 20, an appropriate value may be selected from a value between 1 nm and 2 mPa. In addition, the transistor formed in the single crystal silicon film 30 and the piezoelectric single crystal substrate 10 may be isolated to prevent deterioration of device characteristics due to piezoelectricity.

In this case, the thickness of the single crystal silicon film 30 varies depending on the type of transistor to be implemented. For example, when a MOS device is integrated with a SAW filter, a silicon film having a relatively thin thickness is used, and a device such as a bipolar transistor is used. If you want to integrate a rather thick silicon film of about 1 m 또는 or more can be used.

FIG. 2 is a final cross-sectional view of an integrated circuit process using a MOS transistor and a SAW filter in the substrate structure illustrated in FIG. 1.

Referring to FIG. 2, the substrate is divided into an element region a and an SAW region b, and an amorphous insulating layer 20 is deposited on the single crystal substrate 10 of the element region a. An active region 35 is defined in a predetermined portion of the amorphous insulating layer 20, and a first insulating layer 40 (eg, an oxide layer) for insulating is stacked in the remaining region.

A second insulating layer 60 (eg, an oxide film) is formed on the first insulating layer 40 to insulate the first metal layer from the device, and the gate electrode 50 is formed on the upper portion of the first insulating layer 40. Is formed.

A first metal film pattern 70 is formed on the contact portion where the second insulating film 60 is etched, and a third insulating film 80 (eg, an oxide film) for insulating the first metal layer is formed on the entire surface of the second insulating film 60. Is formed.

The second metal film pattern 90 is formed on the via contact portion in contact with the upper portion of the first metal film pattern 70. The second metal film pattern 90 is also formed on the single crystal substrate 10 in the SAW region b. Is formed.

As shown in FIG. 2, the present invention is much simpler than a conventional structure formed by bonding a quart substrate on which an SAW filter is formed on an IC chip, and can improve process complexity and yield. have.

In other words, the conventional method has a burden of wiring twice for each IC chip and bonded SAW filter chip for packaging. In addition, since the pad of the IC chip must be exposed through the bonded SAW filter chip, there is a difficulty in forming a through-hole in the substrate of the thick SAW filter.

3A to 3D illustrate a process cross-sectional view for forming the structure of the single crystal substrate illustrated in FIG. 1, and use a smart cut method, which is one of methods for making a silicon on insulator (SOI). In brief, the process is as follows.

Referring to FIG. 3A, a silicon region 120 is formed by first implanting a high dose (10 ¹⁶ cm ⁻² or more) of hydrogen ions into a silicon substrate 100 at an appropriate depth by using an implant process. Ion implantation is carried out through an oxide film 140 having a thickness of 1 nm to 500 nm.

At this time, the penetration range Rp of the ions implanted by the ion implantation energy is determined, which is directly connected to the thickness of the single crystal silicon film 30 finally formed.

Referring to FIG. 3B, a handle wafer in which an amorphous insulating film 20 (for example, an oxide film) is formed on the single crystal substrate 10 having both piezoelectricity and insulation property to relax the thermal expansion coefficient is shown.

Referring to FIG. 3C, the device wafer of FIG. 3A is bonded to the handle wafer of FIG. 3B. The oxide film 140 of FIG. 3A and the oxide film on the handle wafer, that is, the amorphous insulating film 20, are bonded to each other. In this case, since the oxide film-oxide film is bonded, the bonding strength of the bonding becomes higher than in the other cases.

At this time, when the wafers are bonded and heat is applied, the device wafer of FIG. 3A is cut along the region where hydrogen is implanted.

Thereafter, in order to make a device on the surface of the remaining silicon film, a mirror surface must be made. To this end, a chemical mechanical polishing (CMP) process is performed to form a single crystal silicon film 30, thereby providing a substrate structure as shown in FIG. 3D. The active element and the SAW filter can be integrated together through an integrated circuit process.

4A to 4D are cross-sectional views for forming a structure of the single crystal substrate shown in FIG. 1 using a conventional SOI wafer as a device wafer.

Referring to FIG. 4A, an oxide film 140 having a thickness of 1 nm to 2 mÅ is formed on the surface of the single crystal silicon film 30 before bonding the SOI wafer, which is a device wafer.

Referring to FIG. 4B, first, a handle wafer in which an amorphous insulating film 20 (for example, an oxide film) is formed on the single crystal substrate 10 having both piezoelectricity and insulation property is alleviated.

Referring to FIG. 4C, when the surface of the oxide film 140 is bonded to the oxide film of the handle wafer, that is, the surface of the amorphous insulating film 20, the oxide film-oxide film is bonded, thereby increasing the bonding strength of the bonding interface.

Referring to FIG. 4D, after bonding, a wafer structure capable of removing a substrate silicon and a buried oxide (BOX), that is, an oxide layer 160, of a SOI wafer and forming a mirror surface device through a CMP process is formed.

5A through 5D are cross-sectional views illustrating a process of integrating a transistor and an SAW device together on the single crystal substrate illustrated in FIG. 1, and illustrate a process of integrating a MOS transistor and an SAW filter in the substrate structure of FIG. 1.

5A, an amorphous insulating film 20 and a first insulating film 40 (eg, an oxide film) are sequentially stacked on the single crystal substrate 10.

In this case, an active region 35 is defined in a portion of the first insulating layer 40, and an oxide layer is formed in the remaining region for insulation.

In addition, as shown in FIG. 5D of the subsequent process, all the oxide films are formed in the region for making the SAW filter, but according to the process, the first insulating film 20 is left in the region where the SAW filter is to be manufactured, and then the SAW filter is removed later. Of course it can.

Referring to FIG. 5B, a MOS transistor including, for example, a source region, a drain region, a gate oxide film, and a gate electrode is formed in the active region 35, and then a second insulating layer 60 (eg An oxide film) was deposited so as to insulate the first metal layer from the device.

Here, although the process of manufacturing a MOS transistor as an example was given, it is also possible to manufacture a bipolar element or other elements. In addition, the thickness of the silicon film, that is, the single crystal insulating film 30 is determined according to the structure of the device to be manufactured, and the single crystal insulating film 30 may be formed at 5 nm to 5 m Å.

Referring to FIG. 5C, after forming a contact hole for source / drain contact of the active region 35, a first metal layer pattern 70 is formed by performing a conventional metallization process.

Subsequently, a third insulating film 80 (for example, an oxide film) for insulating between the first metal layer is deposited thereon, and a via contact hole, which is a window for contacting the first metal layer and the second metal layer, is formed. Using the extra mask, the third, second and first insulating films 60, 40 and 20 in the region where the SAW filter is to be manufactured are sequentially removed.

In this case, when the silicon film, that is, the single crystal insulating film 30 remains in the SAW region, it is removed together.

Referring to FIG. 5D, the second metal layer is deposited and patterned on the entire surface of the resultant to form a second metal layer pattern 90, thereby interconnecting the transistor and the SAW filter while simultaneously forming a metal for the SAW filter. Patterns can be formed.

6A to 6C are cross-sectional views illustrating a wafer structure having a silicon film without a buffer layer on a single crystal substrate having both piezoelectric and insulating properties shown in FIG. 1 as another embodiment of the present invention.

FIG. 6 is a process for implementing a structure similar to that of the substrate shown in FIG. 1, and a major feature is that the fabrication process is simple because the substrate is not bonded and etched back.

Referring to FIG. 6A, an amorphous silicon film 200 is deposited without a buffer layer on the single crystal substrate 10 having both insulation and piezoelectricity to alleviate the difference in thermal expansion coefficient.

6B and 6C, when the oxide film 220 is deposited on the amorphous silicon film 200 and heated, the amorphous silicon film 200 seeds the single crystal substrate 10 having both piezoelectric and insulating properties. As a result, a single crystal silicon film 30 having a kind of recrystallization is formed as shown in Fig. 6C.

This method has the advantage that the process is relatively simple, although some crystal defects are expected. However, it may cause a problem for the difference in thermal expansion coefficient during the integrated circuit process.

Therefore, the final substrate structure of FIG. 6C is almost similar to that of FIG. 1, but the buffer layer corresponding to the amorphous insulating film 20 is excluded. As described above, the substrate structure is formed by directly forming an amorphous silicon film 200 on a substrate having both piezoelectricity and insulation property, and thus, the substrate can be formed at a relatively low price.

At this time, the thickness of the amorphous silicon film 200 is changed according to the type of device to be implemented as shown in FIG.

As described above, according to the substrate structure for the integrated system and the manufacturing method thereof according to the present invention, the IC chip and the chip having the SAW element are bonded as in the conventional case, but the present invention is compatible with the IC element and the SAW element. Because it creates a wafer (or substrate) structure, they can all be integrated on the same chip.

Therefore, the present invention is not only simpler than the conventional substrate structure, but also can improve the complexity of the process and the yield of the device. In addition, the performance can be improved by reducing the parasitic component.

Claims (11)

An integrated system characterized by forming an amorphous insulating film for alleviating the difference in coefficient of thermal expansion and isolating the transistor and the piezoelectric single crystal substrate on a single crystal substrate having both piezoelectricity and insulation, and stacking a single crystal silicon film on which a device can be fabricated. Substrate structure for the. The substrate structure according to claim 1, wherein an IC including active elements such as transistors and diodes and passive elements such as SAW elements and inductors are integrated on the same chip. The substrate structure of claim 1, wherein the single crystal substrate uses quarts having piezoelectric crystal directions. The substrate structure for an integrated system according to claim 1, wherein the amorphous insulating film having an insulating property between the single crystal substrate and the amorphous silicon film is formed to a thickness of 1 nm Å to 2 μm Å. The substrate structure of claim 1, wherein the single crystal silicon film is formed to a thickness of 1 nm Å to 5 m Å. The substrate structure of claim 1, wherein an amorphous insulating film is removed between the single crystal substrate and the single crystal silicon film. Forming an oxide film on the silicon substrate; Forming a device wafer by forming a silicon region at a predetermined depth of the silicon substrate using an implant process; Forming a handle wafer by depositing an amorphous insulating film on the single crystal substrate; Bonding the device wafer to a handle wafer; And forming a stacked structure of a single crystal silicon film / amorphous insulating film / single crystal substrate by performing a chemical and mechanical polishing process on the resultant product. The method of claim 7, wherein the substrate Sequentially forming a buried oxide film and a single crystal silicon film on the silicon substrate; Forming an element wafer by forming an oxide film on the single crystal silicon film; Forming a handle wafer by forming an amorphous insulating film on the single crystal substrate; Bonding the device wafer to a handle wafer; And forming a stacked structure of a single crystal silicon film / amorphous insulating film / single crystal substrate by removing the oxide film of the device wafer and performing a chemical and mechanical polishing process. 10. The method of claim 8, wherein the oxide film formed on the single crystal silicon film of the device wafer is formed in a thickness of about 1 nmÅ to 2 mÅ. The method of claim 7, wherein forming the device on the substrate Forming an amorphous insulating film on the single crystal substrate in the device region; Defining an active region on a predetermined portion of the amorphous insulating layer and forming a first insulating layer for insulation; Forming a second insulating film for insulating between the first metal film and the device on the first insulating film, and forming a MOS transistor in a portion defined as the active region; Forming a first metal film pattern on a contact portion where the second insulating film is etched; Forming a third insulating film on the resultant to insulate the first metal layer; Forming a second metal film pattern on the via contact portion in contact with the first metal film pattern and forming a second metal film pattern on the single crystal substrate in the SAW region. Substrate manufacturing method. The method of claim 7, wherein the substrate Forming an amorphous silicon film on the single crystal substrate; Forming an oxide film on the amorphous silicon film; And heating the oxide film to seed the single crystal substrate to form a single crystal silicon film in which recrystallization is performed.