KR20020053547A - Method of manufacturing a capacitor in semiconductor device - Google Patents
Method of manufacturing a capacitor in semiconductor device Download PDFInfo
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- KR20020053547A KR20020053547A KR1020000083207A KR20000083207A KR20020053547A KR 20020053547 A KR20020053547 A KR 20020053547A KR 1020000083207 A KR1020000083207 A KR 1020000083207A KR 20000083207 A KR20000083207 A KR 20000083207A KR 20020053547 A KR20020053547 A KR 20020053547A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 239000003990 capacitor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000010438 heat treatment Methods 0.000 claims abstract description 37
- 239000012298 atmosphere Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 17
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 13
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229910052684 Cerium Inorganic materials 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910052735 hafnium Inorganic materials 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 229910052746 lanthanum Inorganic materials 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052727 yttrium Inorganic materials 0.000 claims description 4
- 229910052726 zirconium Inorganic materials 0.000 claims description 4
- 229910021193 La 2 O 3 Inorganic materials 0.000 claims description 3
- -1 Ta 2 O 5 Inorganic materials 0.000 claims description 3
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 238000011065 in-situ storage Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 4
- 230000007423 decrease Effects 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 150000004760 silicates Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
Abstract
Description
본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로서, 특히 반도체 기판 상부에 SiO2층을 형성하고 그 상부에 얇은 유전체막을 형성한 후, 고온에서 O2로 열처리하거나, UV-O3를 이용하여 열처리를 한 후, 고온에서 N2로 열처리하고 그 상부에 상부전극을 형성하여 캐패시터를 형성함으로써, C-V 히스테리시스의 크기를 감소시킬 수 있는 반도체 소자의 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. In particular, a SiO 2 layer is formed on a semiconductor substrate and a thin dielectric film is formed thereon, and then heat-treated with O 2 at a high temperature, or heat-treated using UV-O 3 . After the heat treatment at high temperature with N 2 and to form a capacitor by forming an upper electrode on the upper, it relates to a capacitor manufacturing method of a semiconductor device capable of reducing the size of the CV hysteresis.
통상, SiO₂를 이용한 MOS(metal-oxide-silicon)구조에서는 C-V 히스테리시스(hysteresis)의 크기가 매우 작은 반면에, Al₂O₃, Ta₂O5, HfO₂, ZrO, La₂O₃, Y₂O₃, CeO₂, TiO₂및 그 의 실리케이트(silicate)등의 고유전 산화막을 이용한 MOS구조에서는 C-V 히스테리시스가 상대적으로 크게 나타나는 문제점이 있다.In general, MOS (metal-oxide-silicon) structure using SiO ₂ has very small CV hysteresis, whereas Al ₂ O ₃ , Ta ₂ O 5 , HfO ₂ , ZrO, La ₂ O ₃ , Y In the MOS structure using high dielectric oxide films such as ₂ O ₃ , CeO ₂ , TiO ₂ and silicates thereof, CV hysteresis is relatively large.
이러한, C-V 히스테리시스는 게이트절연막과 반도체 기판(예를 들면 실리콘 기판)의 계면 근처에 형성되는 트랩 차아지(trap charge)에 의한 것으로 여겨지는데, 이는 캐패시터 특성 및 트랜지스터(transistor)의 특성 등에 영향을 주기 때문에 그 크기를 감소시키기 위한 연구가 활발히 진행중에 있다.This CV hysteresis is believed to be due to trap charges formed near the interface between the gate insulating film and the semiconductor substrate (e.g., silicon substrate), which affects capacitor characteristics and transistor characteristics. Therefore, research to reduce the size is actively underway.
최근, 고온의 열처리공정에 의해 C-V 히스테리시스가 감소하는 것이 관찰되어 C-V 히스테리시스를 감소시키기 위한 연구가 한 단계 진전되었다. 그러나, C-V 히스테리시스를 감소시키기 위한 열처리공정은 최소한 800℃이상의 높은 온도가 필요하게 된다. 이로 인해, MOS를 구성하는 다른 물질이 산화됨과 아울러 손상되어 MOS의 특성이 저하되는 문제가 도출되고 있다.Recently, a decrease in C-V hysteresis has been observed by a high temperature heat treatment process, and the research for reducing C-V hysteresis has been advanced one step. However, the heat treatment process to reduce the C-V hysteresis requires a high temperature of at least 800 ℃. As a result, other materials constituting the MOS are oxidized and damaged, leading to deterioration of the characteristics of the MOS.
따라서, 본 발명의 목적은 고유전체막을 이용한 MOS구조의 캐패시터에서 발생되는 높은 C-V 히스테리시스를 제거하기 위한 반도체 소자의 캐패시터 제조 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device for removing high C-V hysteresis generated in a capacitor of a MOS structure using a high dielectric film.
본 발명의 또 다른 목적은 반도체 기판 상부에 SiO2층을 형성하고 그 상부에 얇은 유전체막을 형성한 후, 고온에서 O2로 열처리하거나, UV-O3를 이용하여 열처리를 한 후, 고온에서 N2로 열처리하고 그 상부에 상부전극을 형성하여 캐패시터를 형성함으로써, C-V 히스테리시스의 크기를 감소시킬 수 있는 반도체 소자의 캐패시터 제조 방법을 제공함에 있다.Another object of the present invention is to form a SiO 2 layer on the semiconductor substrate and a thin dielectric film thereon, and then heat-treated with O 2 at high temperature, or heat-treated with UV-O 3 , followed by N at high temperature. The present invention provides a method of manufacturing a capacitor of a semiconductor device capable of reducing the size of CV hysteresis by heat-treating to 2 and forming a capacitor by forming an upper electrode thereon.
도 1(a) 내지 도 1(e)는 본 발명의 일 실시예에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 순서적으로 도시한 반도체 소자의 단면도.1 (a) to 1 (e) are cross-sectional views of semiconductor devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.
도 2는 본 발명을 적용한 실시예로서, 열처리 하지 않은 n+ poly-Si /Al2O3(80Å)/p-Si MOS구조 캐패시터의 C-V 히스테리시스 특성 그래프.FIG. 2 is a graph illustrating CV hysteresis characteristics of an n + poly-Si / Al 2 O 3 (80 μs) / p-Si MOS structure capacitor, which is not thermally treated as an embodiment to which the present invention is applied. FIG.
도 3은 O2열처리 온도에 따른 n+ poly-Si /Al2O3(80Å)/p-Si MOS구조 캐패시터의 C-V 히스테리시스 특성 그래프.3 is a graph of CV hysteresis characteristics of n + poly-Si / Al 2 O 3 (80 Å) / p-Si MOS structure capacitor according to O 2 heat treatment temperature.
도 4는 열처리 방법에 따른 n+ poly-Si /Al2O3(80Å)/p-Si MOS구조 캐패시터의 C-V 히스테리시스 특성 그래프.Figure 4 is a graph of CV hysteresis characteristics of n + poly-Si / Al 2 O 3 (80 Å) / p-Si MOS structure capacitor according to the heat treatment method.
도 5은 SiO2형성유무에 따른 n+ poly-Si /Al2O3(80Å)/p-Si MOS구조 캐패시터의 C-V 히스테리시스 특성 그래프.5 is a graph of CV hysteresis characteristics of n + poly-Si / Al 2 O 3 (80 Å) / p-Si MOS structure capacitor with or without SiO 2 formation.
도 6은 Al2O3의 두께에 따른 n+ poly-Si/Al2O3(80Å)/p-Si MOS구조 캐패시터의 C-V 히스테리시스 특성 그래프.FIG. 6 is a graph of CV hysteresis characteristics of n + poly-Si / Al 2 O 3 (80 μs) / p-Si MOS structure capacitor according to Al 2 O 3 thickness; FIG.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1 : 반도체 기판 2 : 유전체막1 semiconductor substrate 2 dielectric film
3 : 상부전극3: upper electrode
본 발명은 소정의 반도체 기판 상부에 고유전체 산화막으로 게이트절연막을 형성한 후, 열처리하는 단계와; 상기 게이트절연막 상부에 전극을 형성하는 단계를 포함한다.The present invention comprises the steps of forming a gate insulating film of a high dielectric oxide film on a predetermined semiconductor substrate, and then heat-treating; Forming an electrode on the gate insulating layer.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1(a) 내지 도 1(e)은 본 발명의 일 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 반도체 소자의 단면도이다.1A to 1E are cross-sectional views of semiconductor devices sequentially illustrated to explain a method of manufacturing a semiconductor device according to an embodiment of the present invention.
도 1(a)를 참조하면, 우선 필드영역과 액티브영역으로 분리하기 위한 소정의 소자 분리막(도시되지 않음)이 형성된 반도체 기판(1) 상부에 게이트절연막(2)이 형성된다.Referring to FIG. 1A, first, a gate insulating film 2 is formed on a semiconductor substrate 1 on which a predetermined device isolation film (not shown) is formed to separate a field region and an active region.
또한, 반도체 기판(1) 상부에는 게이트절연막(2)이 형성되기전에 SiO2, Al, Ta, Hf, Zr, La, Y, Ce, Ti등의 금속을 포함한 실리케이트가 600℃∼1000℃의 온도범위와 N2O, NO 및 O2분위기중 어느 하나의 분위기에서 10∼300초 동안 급속 열처리하여 5~20Å 정도의 두께로 형성된다.In addition, a silicate containing a metal such as SiO 2 , Al, Ta, Hf, Zr, La, Y, Ce, Ti, etc., before the gate insulating film 2 is formed on the semiconductor substrate 1 has a temperature of 600 ° C to 1000 ° C. Rapid heat treatment for 10 to 300 seconds in any one of the range and the atmosphere of N 2 O, NO and O 2 is formed to a thickness of about 5 ~ 20Å.
게이트절연막(2)은 Al2O3, Ta2O5, HfO2, ZrO2, La2O3, Y2O3, CeO2및 TiO2중 어느 하나와 Al, Ta, Hf, Zr, La, Y, Ce, Ti 등의 금속을 포함한 실리케이트가 단원자층 증착법(atomic layer deposition : ALD)에 의해 20∼100Å 정도로 형성된다.The gate insulating film 2 may be formed of any one of Al 2 O 3 , Ta 2 O 5 , HfO 2 , ZrO 2 , La 2 O 3 , Y 2 O 3 , CeO 2 and TiO 2 , and Al, Ta, Hf, Zr, La Silicates containing metals such as, Y, Ce, Ti, and the like are formed in an amount of about 20 to 100 Pa by atomic layer deposition (ALD).
도 1(b)를 참조하면, 이후, 게이트절연막(2)은 500∼1000℃의 온도범위와 O2, N2, N2O, NO, UV-O3및 Ar 중 어느 하나의 분위기 또는 진공분위기에서 5∼60분동안 열처리되거나, 600∼1000℃의 온도범위와 O2, N2, N2O, NO, UV-O3및 Ar 중 어느 하나의 분위기 또는 진공분위기에서 10∼300초동안 급속 열처리되거나, 700℃∼1100℃와 열처리에 의해 H2와 O2분위기에서 10∼300초동안 ISSG(in-situ stream generator) 급속 열처리된다.Referring to FIG. 1 (b), the gate insulating film 2 is then subjected to a temperature range of 500 to 1000 ° C. and an atmosphere or vacuum in any one of O 2 , N 2 , N 2 O, NO, UV-O 3, and Ar. Heat-treated for 5 to 60 minutes in an atmosphere, or for 10 to 300 seconds in a temperature range of 600 to 1000 ° C. and any one of O 2 , N 2 , N 2 O, NO, UV-O 3 and Ar or in a vacuum atmosphere. Rapid heat treatment or in-situ stream generator (ISSG) rapid heat treatment for 10 to 300 seconds in H 2 and O 2 atmosphere by heat treatment at 700 ° C. to 1100 ° C.
여기서, UV-O3에 의해 게이트절연막(2)이 열처리될 경우, UV를 이용하여 100℃∼600℃의 온도범위와 O2또는 O3를 여기 시켜 1∼60분동안 열처리된다.In this case, when the gate insulating film 2 is heat-treated by UV-O 3 , the temperature range of 100 ° C. to 600 ° C. and O 2 or O 3 are excited by UV to be heat-treated for 1 to 60 minutes.
도 1(c)를 참조하면, 우선, 게이트절연막(2) 상부에 상부전극(3)이 형성된다.Referring to FIG. 1C, first, an upper electrode 3 is formed on the gate insulating film 2.
상부전극(3)은 TiN, Ta, TaN, WN, MoN, HfN 및 ZrN와 같은 금속물질로 형성되거나, n+ 또는 p+로 도핑된 다결정 실리콘으로 형성된다.The upper electrode 3 is formed of a metal material such as TiN, Ta, TaN, WN, MoN, HfN, and ZrN, or polycrystalline silicon doped with n + or p +.
도 1(d)를 참조하면, 이후, 상부전극(3)은 500∼900℃의 온도범위와 주입량이 5sccm∼10slm정도인 N2또는 Ar분위기 또는 진공분위기에서 10분∼1시간동안 열처리되거나, 500∼1100℃의 온도범위와 주입량이 5sccm∼10slm정도인 N2또는 Ar분위기 또는 진공분위기에서 10초∼10분동안 급속 열처리 된다.Referring to FIG. 1 (d), the upper electrode 3 is heat-treated for 10 minutes to 1 hour in an N 2 or Ar atmosphere or a vacuum atmosphere having a temperature range of 500 to 900 ° C. and an injection amount of about 5 sccm to 10 slm, or Rapid heat treatment for 10 seconds to 10 minutes in a N 2 or Ar atmosphere or a vacuum atmosphere in the temperature range of 500 ~ 1100 ℃ and injection amount of 5sccm ~ 10slm.
여기서, 진공분위기의 진공도는 5 ×10-2∼5 ×10-9Torr로 설정된다.Here, the vacuum degree of the vacuum atmosphere is set to 5 x 10 -2 to 5 x 10 -9 Torr.
도 1(e)를 참조하면, 이후, 상부전극(3)의 상부에 감광막이 코팅된 후, 노광 및 현상공정에 의해 소정의 감광막패턴이 형성된다.Referring to FIG. 1E, after the photoresist film is coated on the upper electrode 3, a predetermined photoresist pattern is formed by an exposure and development process.
이후, 감광막패턴을 이용한 식각공정에 의해 상부전극(3) 및 게이트절연막(2)이 순차적으로 식각되어 캐패시터 패턴이 형성된다.Subsequently, the upper electrode 3 and the gate insulating film 2 are sequentially etched by an etching process using a photosensitive film pattern to form a capacitor pattern.
전술한 바와 같이, 고유전체막을 이용한 MOS 소자에서 발생되는 C-V 히스테리시스를 제어하기 위해, 본 발명은 상부전극이 형성되기 전에 유전체막을 퍼니스열처리 또는 급속 열처리하거나, UV-O3로 열처리한다. 또한, C-V 히스테리시스를 제어하기 위해, 반도체 기판과 유전체막의 계면간에 SiO2를 형성하거나, Al2O3두께를 조절하거나, 상부전극에 인가되는 최대 게이트전압(Gate Voltage)을 낮추어 준다.As described above, in order to control the CV hysteresis generated in the MOS device using the high dielectric film, the present invention heats or rapidly heats the dielectric film or heat-treats it with UV-O 3 before the upper electrode is formed. In addition, in order to control CV hysteresis, SiO 2 is formed between the interface between the semiconductor substrate and the dielectric film, the Al 2 O 3 thickness is adjusted, or the maximum gate voltage applied to the upper electrode is lowered.
상세히 하면, 우선, C-V 히스테리시스의 크기는 상부전극의 형성전 열처리 유무에 따라 많이 달라지게 된다.In detail, first, the size of the C-V hysteresis will vary depending on the presence or absence of heat treatment before forming the upper electrode.
즉, 도 2에 도시된 바와 같이, 상부전극이 형성되기전에 열처리를 하지 않은 샘플의 3V →-3V →3V 스위프(sweep)에서 나타나는 C-V 히스테리시스트의 크기는 상당히 큰데 반해, 도 3에 도시된 바와 같이, O2로 30분동안 열처리를 할 경우, 온도가 높을수록 C-V 히스테리시스의 크기가 감소하는 것을 알 수 있다.That is, as shown in FIG. 2, the magnitude of the CV hysteresis in the 3V → -3V → 3V sweep of the sample that is not heat-treated before the upper electrode is formed is quite large. Likewise, when the heat treatment for 30 minutes with O 2 , it can be seen that the magnitude of the CV hysteresis decreases as the temperature increases.
또한, UV-O3를 이용하여 10분동안 열처리를 할 경우에는 C-V 히스테리시스의 크기가 거의 줄지 않는 것을 알 수 있었고, N2로 30분동안 열처리하거나 급속열처리 할 경우에는 온도가 퍼니스의 O2의 온도보다 높음에도 불구하고 C-V 히스테리시스의 크기가 조금 밖에 감소하지 않은 것을 볼 수 있다.Further, by using a UV-O 3 When the heat treatment for 10 minutes, the CV, the size of hysteresis was found that hardly give, if the heat treatment or rapid thermal annealing for 30 minutes with N 2, the temperature of the furnace O 2 It can be seen that the magnitude of CV hysteresis is only slightly reduced despite being higher than the temperature.
그러나, UV-O3로 열처리를 한 후, N2분위기에서 30분동안 열처리를 할 경우에는 C-V 히스테리시스의 크기가 상당히 줄어드는 것을 알 수 있다. 이와 같이, 여러 가지 열처리 방법에 따른 C-V 히스테리시스의 크기 변화는 도 4에 도시된 바와 같다.However, when the heat treatment with UV-O 3 , the heat treatment for 30 minutes in the N 2 atmosphere it can be seen that the size of the CV hysteresis significantly reduced. As such, the size change of CV hysteresis according to various heat treatment methods is as shown in FIG. 4.
이와 아울러, 도 5에 도시된 바와 같이, 반도체 기판과 유전체막의 계면간에 SiO2층을 형성할 경우, C-V 히스테리시스의 크기가 변화하는 것을알 수 있다. 즉, 상부에 급속 열처리를 이용하여 7∼12Å 정도의 SiO2층을 형성시킨 후, 그 상부에 Al2O3의 유전체막를 증착하고 N2분위기에서 30분동안 열처리할 경우 C-V 히스테리시스의 크기가 감소하는 것을 알 수 있다.In addition, as shown in FIG. 5, when the SiO 2 layer is formed between the interface between the semiconductor substrate and the dielectric film, it can be seen that the magnitude of the CV hysteresis changes. In other words, after forming a SiO 2 layer of about 7 to 12 Å by rapid heat treatment on the top, and depositing an Al 2 O 3 dielectric film on the top and heat treatment for 30 minutes in N 2 atmosphere, the size of CV hysteresis is reduced I can see that.
또한, 도 6에 도시된 바와 같이, 반도체 기판 상부에 형성되는 Al2O3의 두께에 따라 C-V 히스테리시스의 크기가 변화하는 것을 알 수 있다. 즉, Al2O3의 두께가 얇을수록 C-V 히스테리시스의 크기가 감소하는 것을 알 수 있다.In addition, as shown in FIG. 6, it can be seen that the magnitude of the CV hysteresis changes according to the thickness of Al 2 O 3 formed on the semiconductor substrate. That is, it can be seen that as the thickness of Al 2 O 3 decreases, the magnitude of CV hysteresis decreases.
결론적으로 C-V 히스테리시스를 없애기 위해서는 고온에서 O2로 열처리하거나, UV-O3를 이용하여 열처리를 한 후, 고온에서 N2로 열처리 또는 반도체 기판의 상부에 얇은 SiO2층을 형성시키고 고온 열처리를 하거나, 반도체 기판 상부에 형성되는 유전체막의 두께를 얇게 형성하거나, C-V 히스테리시스측정을 위해 걸어주는 최대 게이트전압(Gate Voltage)의 크기를 낮추는 방법이 효과적이다.In conclusion, in order to eliminate CV hysteresis, heat treatment with O 2 at high temperature, UV-O 3 heat treatment, heat treatment with N 2 at high temperature, or a thin SiO 2 layer on top of the semiconductor substrate, For example, a method of reducing the thickness of the dielectric film formed on the semiconductor substrate or reducing the maximum gate voltage applied for the CV hysteresis measurement is effective.
상술한 바와 같이, 본 발명은 반도체 기판 상부에 SiO2층을 형성하고 그 상부에 얇은 유전체막을 형성한 후, 고온에서 O2로 열처리하거나, UV-O3를 이용하여 열처리를 한 후, 고온에서 N2로 열처리하고 그 상부에 상부전극을 형성하여 캐패시터를 형성함으로써, C-V 히스테리시스의 크기를 감소시킬 수 있다.As described above, the present invention forms a SiO 2 layer on the semiconductor substrate and a thin dielectric film formed thereon, followed by heat treatment with O 2 at high temperature, or heat treatment with UV-O 3 , followed by high temperature. By heat-treating with N 2 and forming a capacitor by forming an upper electrode thereon, the magnitude of CV hysteresis can be reduced.
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| KR20190064297A (en) * | 2017-11-30 | 2019-06-10 | 롯데케미칼 주식회사 | A gamma-resistant polycarbonate resin composition having improved color recovery performance |
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| KR100258979B1 (en) * | 1997-08-14 | 2000-06-15 | 윤종용 | Method for manufacturing capacitor of semiconductor by heat treatment of dieledtric layer under hydrogen ambitent |
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| KR20190064297A (en) * | 2017-11-30 | 2019-06-10 | 롯데케미칼 주식회사 | A gamma-resistant polycarbonate resin composition having improved color recovery performance |
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