KR20020051407A - Method of forming a metal wiring in a semiconductor device - Google Patents
Method of forming a metal wiring in a semiconductor device Download PDFInfo
- Publication number
- KR20020051407A KR20020051407A KR1020000080439A KR20000080439A KR20020051407A KR 20020051407 A KR20020051407 A KR 20020051407A KR 1020000080439 A KR1020000080439 A KR 1020000080439A KR 20000080439 A KR20000080439 A KR 20000080439A KR 20020051407 A KR20020051407 A KR 20020051407A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- metal wiring
- metal
- forming
- hard mask
- Prior art date
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 60
- 239000002184 metal Substances 0.000 title claims abstract description 60
- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000010410 layer Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000011229 interlayer Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 claims abstract 4
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 17
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 10
- 239000012790 adhesive layer Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000013077 target material Substances 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- 230000001070 adhesive effect Effects 0.000 abstract description 4
- 239000000853 adhesive Substances 0.000 abstract description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 abstract 12
- 238000000926 separation method Methods 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910018182 Al—Cu Inorganic materials 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 229910010282 TiON Inorganic materials 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 하드 마스크를 이용하여 미세 구조의 금속 배선 패턴을 불량없이 형성할 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices in which a metal wiring pattern having a fine structure can be formed without defect using a hard mask.
0.25㎛ 이하의 CMOS 소자의 제조 기술 중에서 금속 배선을 형성하는 공정은 보다 정밀하고 미세한 디자인 룰이 요구되는 반면에, 배선에 의한 RC 지연(Delay) 측면의 증가를 억제하기 위하여 금속 배선의 두께는 고집적화시키지 못한다. 이로 인하여, 금속 배선의 패터닝을 위한 감광막 패턴의 두께 마진이 부족하게 된다. 즉, 미세 금속 배선을 형성하기 위해서는 감광막 패턴의 두께가 감소되어야 하지만, 식각해야 할 금속 배선의 두께는 상대적으로 두껍기 때문에 금속 식각 과정에서 금속 측벽 보호를 위한 감광막 패턴이 부족하여 배선의 측벽 손상이 심화된다.The process of forming the metal wiring in the manufacturing technology of the CMOS element of 0.25 μm or less requires more precise and finer design rules, while the thickness of the metal wiring is highly integrated to suppress the increase in the RC delay caused by the wiring. I can't let you. For this reason, the thickness margin of the photosensitive film pattern for patterning of metal wiring becomes insufficient. That is, the thickness of the photoresist pattern must be reduced to form the fine metal interconnection, but since the thickness of the metal interconnection to be etched is relatively thick, the photoresist pattern for protecting the metal sidewalls is insufficient in the metal etching process, so that the damage to the sidewall of the wiring is increased. do.
이를 극복하기 위하여 적용되는 기술이 하드 마스크 기술이다. 이 기술은 금속과의 식각률 차이를 이용하는 것으로, 기존의 기술에서 적용되는 물질로는 SiO2막이나 SiON막이다. 그러나, 이 경우 웨이퍼의 가장자리(Edge) 영역에 증착되는 금속 구조(일반적으로 적용되는 금속 구조는 Ti/Al-Cu/Ti/TiN)의 표면(Surface) 불량으로 인하여, 하드 마스크로 적용된 SiO2막이나 SiON막이 금속 식각 후 CD SEM 등의 공정 모니터링(Monitoring) 장비에서 벗겨지거나(Peeling), 웨이퍼 내의 불특정 영역으로 이동되면서 금속 배선을 끊어버리거나, 또는 스택 비아(Stack Via)용 랜딩 패턴(Landing pattern)이 없어지는 등의 불량을 초래한다. 이러한 불량 원인은 금속 구조에 부적절하게 증착된 표면과 SiO2막 혹은 SiON막간의 접착(Adhesion) 부족이 원인이 되기도 한다.The technique applied to overcome this is a hard mask technique. This technique uses a difference in etching rate from a metal, and a material applied in the existing technique is a SiO 2 film or a SiON film. However, in this case, due to the surface defect of the metal structure (generally applied metal structure is Ti / Al-Cu / Ti / TiN) deposited on the edge region of the wafer, the SiO 2 film applied as a hard mask Or SiON films are etched away from process monitoring equipment such as CD SEM after metal etching, breaking metal wires as they move to unspecified areas in the wafer, or landing patterns for stack vias This results in a defect such as disappearing. This failure may be caused by a lack of adhesion between the surface improperly deposited on the metal structure and the SiO 2 film or SiON film.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 금속 배선 구조와의 접착 특성이 우수한 TiO2막을 하드 마스크로 사용함으로써 공정의 신뢰성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of improving the reliability of the process by using a TiO 2 film having excellent adhesion with a metal wiring structure as a hard mask in order to solve the above problems. have.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도.1A to 1D are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
1 : 반도체 기판2 : 층간 절연막1 semiconductor substrate 2 interlayer insulating film
3a : 제 1 Ti막3b : 배선용 금속층3a: first Ti film 3b: wiring metal layer
3c : 제 2 Ti막3d : TiN막3c: second Ti film 3d: TiN film
3 : 금속 배선4 : TiO2막3: metal wiring 4: TiO 2 film
5 : 감광막 패턴5: photosensitive film pattern
본 발명에 따른 반도체 소자의 금속 배선 형성 방법은 층간 절연막 상에 Ti막, 금속 배선용 금속층, 접착층 및 반사 방지막이 순차적으로 적층된 금속 배선 구조가 형성된 반도체 기판이 제공되는 단계, 금속 배선용 금속층 상에 하드 마스크를 형성한 후 패터닝하는 단계 및 패티닝된 하드 마스크를 식각 마스크로 하여 반사 방지막, 접착층, 금속 배선용 금속층 및 Ti막의 노출된 영역을 순차적으로 식각하여 금속 배선을 형성하는 단계로 이루어진다.The method for forming a metal wiring of a semiconductor device according to the present invention is provided with a semiconductor substrate having a metal wiring structure in which a Ti film, a metal wiring metal layer, an adhesive layer, and an antireflection film are sequentially stacked on an interlayer insulating film, and hard on the metal layer for metal wiring. After the mask is formed, patterning is performed, and the patterned hard mask is used as an etch mask to sequentially etch exposed regions of the anti-reflection film, the adhesive layer, the metal wiring metal layer, and the Ti film to form the metal wiring.
금속 배선용 금속층은 알루미늄, 구리 또는 알루미늄 구리 합금으로 형성한다. 접착층은 Ti막으로 형성하며, 반사 방지막은 TiN막을 형성한다.The metal layer for metal wiring is formed of aluminum, copper, or an aluminum copper alloy. The adhesive layer is formed of a Ti film, and the antireflection film forms a TiN film.
하드 마스크는 금속 배선 구조와 접착력이 뛰어난 TiO2막으로 형성하는데, TiO2막은 스퍼터링 방법으로 1000 내지 1500Å의 두께로 형성하거나, 반사 방지막을산소 분위기에서 산화시켜 50 내지 100Å의 두께로 산화층을 형성한 후 Ti막을 증착하고 RTO 처리로 Ti막을 산화시켜 700 내지 1000Å의 두께로 형성한다.The hard mask to form an oxide layer with a thickness of metal interconnect structure and to adhesive force is formed in a superior TiO 2 layer, TiO 2 is formed as a film of 1000 to 1500Å thick by a sputtering method, or by oxidizing at the anti-reflection film is an oxygen atmosphere of 50 to 100Å After the Ti film is deposited and the Ti film is oxidized by RTO treatment to form a thickness of 700 to 1000 Å.
하드 마스크의 패터닝은 C-F 계열의 가스를 식각 가스로 사용하여 실시한다.Patterning of the hard mask is performed using a C-F series gas as an etching gas.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 더욱 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도이다.1A to 1D are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings of a semiconductor device according to the present invention.
도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판(1) 상에 층간 절연막(2)을 형성한 후 제 1 Ti막(3a), 배선용 금속층(3b), 제 2 Ti막(3c) 및 TiN막(3d)을 순차적으로 형성한다.Referring to FIG. 1A, after forming an interlayer insulating film 2 on a semiconductor substrate 1 on which various elements for forming a semiconductor device are formed, a first Ti film 3a, a wiring metal layer 3b, and a second Ti film are formed. (3c) and the TiN film 3d are formed sequentially.
여기서, 제 1 Ti막(3a)은 배선용 금속층(3b)을 증착할 때 증착 특성을 향상시키기 위하여 증착 활성층으로 형성한다. 배선용 금속층(3b)은 저항이 낮은 구리(Cu)나 알루미늄(Al) 또는 알루미늄 구리 합금(Al-Cu)을 증착하여 형성한다. 제 2 Ti막(3c)은 배선용 금속층(3b)과 TiN막(3d)과의 접착 특성이 열악하므로 접착 특성을 향상시키기 위한 접착층으로 사용하기 위하여 형성한다. TiN막(3d)은 노광 공정시 반사 방지막으로 사용하기 위하여 형성한다.Here, the first Ti film 3a is formed of a deposition active layer in order to improve the deposition characteristics when depositing the wiring metal layer 3b. The wiring metal layer 3b is formed by depositing copper (Cu), aluminum (Al), or aluminum copper alloy (Al-Cu) having low resistance. Since the adhesion property between the wiring metal layer 3b and the TiN film 3d is inferior, the 2nd Ti film | membrane 3c is formed in order to use it as an adhesive layer for improving an adhesion | attachment characteristic. The TiN film 3d is formed for use as an antireflection film in the exposure process.
도 1b를 참조하면, TiN막(3d) 상에 하드 마스크로 TiO2막(4)을 형성한 후 금속 배선 라인을 정의하는 감광막 패턴(5)을 형성한다.Referring to FIG. 1B, after the TiO 2 film 4 is formed on the TiN film 3d with a hard mask, a photosensitive film pattern 5 defining a metal wiring line is formed.
TiO2막(4)은 190 내지 210℃의 온도와 5 내지 50mTorr의 압력에서 TiO2또는 Ti를 타겟 물질로 하여 스퍼터링 방법으로 1000 내지 1500Å의 두께로 형성한다. 이때, Ti를 타겟 물질로 사용할 경우에는 증착 챔버 내부로 산소 가스를 공급하여 준다. TiO2막을 형성하는 다른 방법으로는 TiN막(3d)을 산소(O2) 분위기에서 산화시켜 50 내지 100Å의 두께로 TiON막(도시되지 않음)을 형성한 후 Ti막(도시되지 않음)을 증착하고 190 내지 210℃의 온도와 5 내지 50mTorr의 압력에서 RTO 처리로 Ti막을 산화시켜 형성한다. 상기의 방법으로 TiO2막(4)을 700 내지 1000Å의 두께로 형성한다.The TiO 2 film 4 is formed to a thickness of 1000 to 1500 kPa by the sputtering method using TiO 2 or Ti as a target material at a temperature of 190 to 210 ° C. and a pressure of 5 to 50 mTorr. In this case, when Ti is used as the target material, oxygen gas is supplied into the deposition chamber. As another method of forming a TiO 2 film, the TiN film 3d is oxidized in an oxygen (O 2 ) atmosphere to form a TiON film (not shown) to a thickness of 50 to 100 GPa and then a Ti film (not shown) is deposited. And the Ti film is oxidized by RTO treatment at a temperature of 190 to 210 ° C. and a pressure of 5 to 50 mTorr. By the above method, the TiO 2 film 4 is formed to a thickness of 700 to 1000 mW.
도 1c를 참조하면, 감광막 패턴(5)을 식각 마스크로 하여 TiO2막(4)의 선택된 부분을 식각해 패터닝한다.Referring to FIG. 1C, the selected portion of the TiO 2 film 4 is etched and patterned using the photoresist pattern 5 as an etching mask.
이때, TiO2막(4)의 패터닝을 위한 식각 공정은 C-F 계열의 가스를 식각 가스로 사용하여 실시한다.In this case, an etching process for patterning the TiO 2 film 4 is performed using a CF-based gas as an etching gas.
도 1d를 참조하면, 감광막 패턴(5)을 제거한 후 하드 마스크인 TiO2막(4)을 식각 마스크로 하여 TiN막(3d), 제 2 Ti막(3c), 배선용 금속층(3b) 및 제 1 Ti막(3a)의 노출된 영역을 식각하여 금속 배선(3)을 형성한다.Referring to FIG. 1D, after removing the photosensitive film pattern 5, the TiN film 3d, the second Ti film 3c, the wiring metal layer 3b, and the first layer are formed by using the TiO 2 film 4, which is a hard mask, as an etching mask. The exposed region of the Ti film 3a is etched to form the metal wiring 3.
상술한 바와 같이, 본 발명은 하드 마스크로 접착 특성이 우수한 TiO2막을 사용해 형성함으로써 하드 마스크가 후속 공정이나 모니터링 공정에서 떨어져 나가 다른 패턴에 불량이 발생하는 것을 방지하여 공정의 신뢰성을 향상시키고, 수율을 증대시키는 효과가 있다.As described above, the present invention is formed by using a TiO 2 film having excellent adhesive properties as a hard mask to prevent the hard mask from falling off in subsequent processes or monitoring processes to prevent defects in other patterns, thereby improving process reliability and yield. There is an effect to increase.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0080439A KR100380150B1 (en) | 2000-12-22 | 2000-12-22 | Method of forming a metal wiring in a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0080439A KR100380150B1 (en) | 2000-12-22 | 2000-12-22 | Method of forming a metal wiring in a semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020051407A true KR20020051407A (en) | 2002-06-29 |
| KR100380150B1 KR100380150B1 (en) | 2003-04-11 |
Family
ID=27684748
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2000-0080439A KR100380150B1 (en) | 2000-12-22 | 2000-12-22 | Method of forming a metal wiring in a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100380150B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040081240A (en) * | 2003-03-14 | 2004-09-21 | 주식회사 하이닉스반도체 | Method for forming metal line of semiconductor device |
| KR100714287B1 (en) * | 2005-02-25 | 2007-05-02 | 주식회사 하이닉스반도체 | Method for forming a pattern of semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101180697B1 (en) * | 2004-12-21 | 2012-09-07 | 매그나칩 반도체 유한회사 | Method for forming metal line of semiconductor device |
-
2000
- 2000-12-22 KR KR10-2000-0080439A patent/KR100380150B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040081240A (en) * | 2003-03-14 | 2004-09-21 | 주식회사 하이닉스반도체 | Method for forming metal line of semiconductor device |
| KR100714287B1 (en) * | 2005-02-25 | 2007-05-02 | 주식회사 하이닉스반도체 | Method for forming a pattern of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100380150B1 (en) | 2003-04-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100372742B1 (en) | Interconnection forming method utilizing an inorganic antireflection layer | |
| JP3778174B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR100414506B1 (en) | Dry etching method and method of manufacturing a semiconductor device | |
| JP2001338978A (en) | Semiconductor device and its manufacturing method | |
| JP2002009150A (en) | Semiconductor device, its manufacturing method and manufacturing equipment | |
| JP2004063859A (en) | Method for manufacturing semiconductor device | |
| KR100581244B1 (en) | Fabricating method of semiconductor device | |
| JPH07201986A (en) | Manufacture of semiconductor device | |
| KR100293080B1 (en) | Manufacturing method of semiconductor device | |
| JPWO2007043634A1 (en) | Manufacturing method of multilayer wiring | |
| KR100380150B1 (en) | Method of forming a metal wiring in a semiconductor device | |
| KR940003566B1 (en) | Making method for multi-layer wiring of semiconductor device | |
| KR20090037103A (en) | Method for fabricating semiconductor device | |
| KR20030077455A (en) | Method for manufacturing semiconductor device using dual-damascene techniques | |
| US6613680B2 (en) | Method of manufacturing a semiconductor device | |
| JPH1167909A (en) | Manufacture of semiconductor device | |
| JP3371170B2 (en) | Method for manufacturing semiconductor device | |
| KR100571696B1 (en) | Method For Manufacturing Semiconductor Devices | |
| KR100342869B1 (en) | Method for etching multilayered metal line in semiconductor device | |
| KR100854209B1 (en) | Method of fabricating semiconductor devices | |
| JPH10209276A (en) | Wiring forming method | |
| JPH05121378A (en) | Method of manufacturing semiconductor device | |
| KR100457740B1 (en) | A method for manufacturing a multi-layer metal line of a semiconductor device | |
| KR20000056260A (en) | Method of forming a contact in a semiconductor device | |
| KR20030055798A (en) | A method for forming via hole of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| LAPS | Lapse due to unpaid annual fee |