KR20020045451A - Method for fabricating CMOS image sensor - Google Patents
Method for fabricating CMOS image sensor Download PDFInfo
- Publication number
- KR20020045451A KR20020045451A KR1020000075067A KR20000075067A KR20020045451A KR 20020045451 A KR20020045451 A KR 20020045451A KR 1020000075067 A KR1020000075067 A KR 1020000075067A KR 20000075067 A KR20000075067 A KR 20000075067A KR 20020045451 A KR20020045451 A KR 20020045451A
- Authority
- KR
- South Korea
- Prior art keywords
- image sensor
- film
- cmos image
- ion implantation
- oxide
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 4
- 238000005468 ion implantation Methods 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 abstract description 7
- 230000035515 penetration Effects 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 230000000295 complement effect Effects 0.000 abstract 1
- 239000002019 doping agent Substances 0.000 abstract 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14698—Post-treatment for the devices, e.g. annealing, impurity-gettering, shor-circuit elimination, recrystallisation
Abstract
Description
본 발명은 이미지센서 제조방법에 관한 것으로, 특히 CMOS 이미지센서의 포토다이오드 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing an image sensor, and more particularly, to a method of manufacturing a photodiode of a CMOS image sensor.
잘 알려진 바와 같이 CMOS 이미지센서는 핀드포토다이오드를 통해 이미지에 대응되는 전하를 생성하고 모은 다음, 이 전하를 트랜스퍼트랜지스터를 통해 센싱노드로 전달하여 전기적 신호를 검출하는 방식을 사용하게 된다.As is well known, a CMOS image sensor uses a pinned photodiode to generate and collect a charge corresponding to an image, and then transfer the charge to a sensing node through a transfer transistor to detect an electrical signal.
도 1은 종래기술에 따른 CMOS 이미지센서 제조 공정을 보여주는 단면도이다.1 is a cross-sectional view showing a manufacturing process of a CMOS image sensor according to the prior art.
도1을 참조하면, 종래에는 P+실리콘기판(101)상에 저농도의 P에피층(102)을 형성시키고, 필드산화막(Fox)(103)을 형성한 후, 폴리실리콘막(104)과 텅스텐실리사이드막(105)을 연속적으로 도포하고 패터닝함으로써 폴리사이드 게이트 전극을 형성한다.Referring to FIG. 1, conventionally, after forming a low concentration P epitaxial layer 102 on a P + silicon substrate 101, forming a field oxide film (Fox) 103, the polysilicon film 104 and tungsten A polyside gate electrode is formed by applying and patterning the silicide film 105 continuously.
이후 포토다이오드를 형성하기 위한 이온주입마스크로서 감광막 패턴(106)을 형성한 다음, 고에너지 이온주입(107)을 실시함으로써 저농도의 P에피층(102)에 N형불순물층(108)을 형성한다.Thereafter, the photosensitive film pattern 106 is formed as an ion implantation mask for forming the photodiode, and then the high-energy ion implantation 107 is performed to form the N-type impurity layer 108 in the low concentration P epilayer 102. .
도면에는 도시되지 않았지만, 이후 저에너지 이온주입을 실시하여 N형불순물층(108) 상에 P형불순물층을 형성하므로써 핀드포토다이오드의 제조는 완료된다.Although not shown in the drawings, the manufacture of the pinned photodiode is completed by forming a P-type impurity layer on the N-type impurity layer 108 by performing low energy ion implantation.
한편, 적색광에 대한 광감도를 높히기 위하여 고에너지 이온 주입을 통해 포토다이오드를 형성하게 되는 바, 전하운송효율에 영향을 미치는 트랜스터트랜지스터의 채널부분으로의 불순물의 침투(Penetration)를 방지하기 위하여 트랜스퍼트랜지스터의 게이트 폴리실리콘(104)의 두께(T1)를 일반적인 서브-마이크론 기술(Submicron Technology)에서 사용되는 두께보다 두껍게 형성시킨다. (도면의 "A" 참조)On the other hand, the photodiode is formed through high energy ion implantation in order to increase the photosensitivity to the red light, so that the transfer transistor is prevented to prevent the penetration of impurities into the channel portion of the transistor, which affects the charge transport efficiency. The thickness T1 of the gate polysilicon 104 of is formed to be thicker than the thickness used in general sub-micron technology. (See "A" in the drawing.)
고에너지 이온주입시 인(Phosphorous)을 사용하는 경우, 이온주입 에너지가 180keV일때 게이트의 폴리실리콘(104) 두께는 약 4500∼5000Å 정도 필요하다.In the case of using phosphorus (Phosphorous) for high-energy ion implantation, when the ion implantation energy is 180 keV, the thickness of the polysilicon 104 of the gate is required to be about 4500 to 5000 kPa.
그러나 이 방법은 일반적인 서브 마이크론 기술과 상이하기 때문에 공정이 까다로울 뿐만 아니라, 200keV 이상의 고에너지 이온주입 공정에는 적용하기 곤란한 제약조건이 따르기 때문에 불편하다.However, this method is not only difficult to process because it is different from the general submicron technology, but also inconvenient because it is difficult to apply to the high energy ion implantation process of 200 keV or more.
만약 200keV 이상의 고에너지로 포토다이오드를 형성하기 위하여 이온주입을 실시한다면 서브마이크론 기술에서 허용할 수 있는 게이트 폴리실리콘 두께로는 이온 침투를 방지할 수 없어 전하운송효율에 영향을 미치는 트랜스퍼트랜지스터의 채널부분으로의 불순물 유입이 발생되고, 이로 인해 원치 않는 열적발생(Thermally Generated) 전하에 의한 암전류(Dark Current)값이 증가하여 CMOS 이미지센서의 특성이 열화되게 된다.If ion implantation is carried out to form photodiodes with high energy of 200 keV or more, the channel portion of the transfer transistor that affects charge transport efficiency cannot be prevented by ion gate penetration with the gate polysilicon thickness that is acceptable in submicron technology. Impurity inflow into the substrate occurs, which causes dark current to increase due to unwanted thermally generated charges, thereby degrading the characteristics of the CMOS image sensor.
본 발명은 상기한 바와 같은 종래기술의 문제점을 해결하기 위하여 안출된 것으로서, 서브마이크론 기술에서 통상 적용하고 있는 게이트 폴리실리콘 두께를 적용하면서도 고에너지 이온주입시 채널영역으로 이온주입이온이 침투하는 것을 방지하여, 공정의 단순화 및 소자 특성을 향상시키는데 적합한 CMOS 이미지센서 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art as described above, while preventing the penetration of ion implantation ions into the channel region during high energy implantation while applying the thickness of the gate polysilicon commonly applied in submicron technology. Accordingly, an object of the present invention is to provide a method for manufacturing a CMOS image sensor suitable for simplifying the process and improving device characteristics.
도 1은 종래기술에 따른 CMOS 이미지센서 제조 공정중 고에너지 불순물 이온주입이 이루어지는 상태를 나타낸 도면.1 is a view showing a state in which high energy impurity ion implantation is performed during the CMOS image sensor manufacturing process according to the prior art.
도 2a 내지 도 2c는 본 발명의 바람직한 실시예에 따른 CMOS 이미지센서 제조 공정을 보여주는 단면도.2A to 2C are cross-sectional views showing a CMOS image sensor manufacturing process according to a preferred embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
201 : 실리콘기판 202 : 에피층201: silicon substrate 202: epi layer
203 : 필드산화막 204 : 폴리실리콘203: field oxide film 204: polysilicon
205 : 산화막 206 : 감광막패턴205: oxide film 206: photosensitive film pattern
208 : N형불순물층208N-type impurity layer
상기 목적을 달성하기 위한 본 발명의 CMOS 이미지센서 제조방법은, 기판에 게이트 폴리실리콘막을 증착하는 단계: 상기 폴리실리콘막 상에 절연막을 증착하는 단계; 상기 절연막과 상기 폴리실리콘막을 선택적으로 식각하여 게이트패턴을 형성하는 단계; 상기 기판의 일부영역 및 패턴된 상기 절연막의 일측이 노출되는 감광막패턴을 형성하는 단계; 및 고에너지 이온주입을 실시하여 상기 기판에 포토다이오드의 불순물층을 형성하는 단계를 포함하여 이루어진다.According to another aspect of the present invention, there is provided a method of fabricating a CMOS image sensor, the method comprising: depositing a gate polysilicon film on a substrate; Selectively etching the insulating film and the polysilicon film to form a gate pattern; Forming a photoresist pattern in which a portion of the substrate and one side of the patterned insulating layer are exposed; And performing a high energy ion implantation to form an impurity layer of the photodiode on the substrate.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도 2a 내지 도 2c는 본 발명의 바람직한 실시예에 따른 CMOS 이미지센서 제조 공정을 보여준다.2A to 2C show a CMOS image sensor manufacturing process according to a preferred embodiment of the present invention.
도 2a를 참조하면, P+실리콘기판(201)상에 P에피층(202)을 형성시키고, 필드산화막(Fox)(203)을 형성한다.Referring to FIG. 2A, a P epitaxial layer 202 is formed on a P + silicon substrate 201, and a field oxide film (Fox) 203 is formed.
이후, 폴리실리콘막(204)과 산화막(205)을 연속적으로 도포한다. 종래와는 다르게 본 발명에서는 게이트 폴리실리콘(204)의 두께(T2)를 서브-마이크론 기술에 따른 두께인 약 1500-2000Å로 증착하고, 그 상부에 이온주입 베리어(barrier)될 산화막(205)을 1000-1500Å 증착한다. 도면에는 도시되지 않았지만 게이트 폴리실리콘(204)와 P에피층(202) 사이에는 게이트산화막이 게재된다.Thereafter, the polysilicon film 204 and the oxide film 205 are applied successively. Unlike the related art, in the present invention, the thickness T2 of the gate polysilicon 204 is deposited to about 1500-2000 μs, which is a thickness according to the sub-micron technology, and an oxide film 205 to be ion barriered is deposited on top thereof. Deposit 1000-1500Å. Although not shown in the figure, a gate oxide film is interposed between the gate polysilicon 204 and the P epi layer 202.
이어서, 도 2b에 도시된 바와 같이 게이트마스크 및 식각 공정을 통해 산화막(205)과 폴리실리콘막(204) 식각하여 게이트패턴(205a, 204a)을 완성한다.Subsequently, as illustrated in FIG. 2B, the oxide layer 205 and the polysilicon layer 204 are etched through a gate mask and an etching process to complete the gate patterns 205a and 204a.
그 후, P에피층(202)의 일부영역과 상기 게이트패턴(205a, 204a)의 일측이 노출된 감광막패턴(206)을 형성하고, 고에너지 이온주입에 의해 N형불순물층(208)을 형성한다.Thereafter, a portion of the P epi layer 202 and a photosensitive film pattern 206 having one side of the gate patterns 205a and 204a are exposed to form an N-type impurity layer 208 by high energy ion implantation. do.
도면에는 도시되지 않았지만, 이후 저에너지 이온주입을 실시하여 N형불순물층(208) 상에 P형불순물층을 형성하므로써 핀드포토다이오드의 제조는 완료된다.Although not shown in the drawings, the manufacture of the pinned photodiode is completed by forming a P-type impurity layer on the N-type impurity layer 208 by performing low energy ion implantation.
그리고, 산화막(205a)은 게이트 측벽 스페이서 형성시 제거해도 되고 그대로 놔두어도 된다.The oxide film 205a may be removed during the gate sidewall spacer formation or may be left as it is.
본 발명에서와 같은 방법을 적용함으로써 일반적인 서브마이크론 기술과 동일한 공정을 사용할 수 있을 뿐만 아니라, 포토다이오드 형성용 200keV 이상의 고에너지 이온주입 공정도 얼마든지 적용 가능하다.By applying the same method as in the present invention, not only the same process as general submicron technology can be used, but also a high energy ion implantation process of 200 keV or more for photodiode formation can be applied.
즉, 게이트 폴리실리콘 상부에 1000-1500Å의 두꺼운 산화막(205)이 존재하기 때문에, 200KeV 이상의 이온주입에서도 게이트 하부의 채널로 이온이 침투되는 것을 방지할 수 있어 이미지센서의 특성 열화를 방지할 수 있다.That is, since the 1000-1500 두꺼운 thick oxide film 205 is present on the gate polysilicon, ions can be prevented from penetrating into the channel under the gate even in an ion implantation of 200 KeV or more, thereby preventing deterioration of characteristics of the image sensor. .
본 발명은 핀드포토다이오드 이외에 고에너지 이온주입만을 실시하여 형성된 PN 접합 포토다이오드 공정에서도 적용할 수 있고, 또한 기판은 에피층이 없는 상태에서도 적용할 수 있다. 그리고 산화막(205) 대신에 산화질화막, 질화막 등의 절연막도 적용 가능하다.The present invention can be applied to a PN junction photodiode process formed by performing only high energy ion implantation in addition to the pinned photodiode, and the substrate can be applied even in the absence of an epi layer. Instead of the oxide film 205, an insulating film such as an oxynitride film or a nitride film can also be applied.
이렇듯, 본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.As such, although the technical idea of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명에서와 같은 방법을 적용함으로써 일반적인 서브마이크론 기술(Submicron Technology)과 동일한 공정을 사용할 수 있어서 수율 향상에 기여할 수 있을 뿐만 아니라, 포토다이오드 형성시 200KeV 이상의 고에너지 이온주입 공정도 얼마든지 적용 가능하여 제품의 제조공정 조건의 마진도 충분히 확보할 수 있다.By applying the same method as in the present invention, it is possible to use the same process as the general submicron technology, which not only contributes to the yield improvement, but also high energy ion implantation process of 200KeV or more when forming photodiode. The margin of the manufacturing process conditions of the product can also be sufficiently secured.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000075067A KR20020045451A (en) | 2000-12-11 | 2000-12-11 | Method for fabricating CMOS image sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000075067A KR20020045451A (en) | 2000-12-11 | 2000-12-11 | Method for fabricating CMOS image sensor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20020045451A true KR20020045451A (en) | 2002-06-19 |
Family
ID=27680809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000075067A KR20020045451A (en) | 2000-12-11 | 2000-12-11 | Method for fabricating CMOS image sensor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20020045451A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040001201A (en) * | 2002-06-27 | 2004-01-07 | 동부전자 주식회사 | Method of making shallow trench type pixel for cmos image sensor |
| KR100593160B1 (en) * | 2004-12-30 | 2006-06-26 | 매그나칩 반도체 유한회사 | Method for fabricating cmos image sensor |
| KR100745596B1 (en) * | 2004-11-29 | 2007-08-02 | 삼성전자주식회사 | Image sensor and method for forming the same |
| KR100802294B1 (en) * | 2006-11-20 | 2008-02-11 | 동부일렉트로닉스 주식회사 | Method for manufactruing image sensor |
| KR100954905B1 (en) * | 2007-12-24 | 2010-04-27 | 주식회사 동부하이텍 | Method for Manufacturing of Image Sensor |
-
2000
- 2000-12-11 KR KR1020000075067A patent/KR20020045451A/en not_active Application Discontinuation
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040001201A (en) * | 2002-06-27 | 2004-01-07 | 동부전자 주식회사 | Method of making shallow trench type pixel for cmos image sensor |
| KR100745596B1 (en) * | 2004-11-29 | 2007-08-02 | 삼성전자주식회사 | Image sensor and method for forming the same |
| US7602034B2 (en) | 2004-11-29 | 2009-10-13 | Samsung Electronics Co., Ltd. | Image sensor and method for forming the same |
| KR100593160B1 (en) * | 2004-12-30 | 2006-06-26 | 매그나칩 반도체 유한회사 | Method for fabricating cmos image sensor |
| KR100802294B1 (en) * | 2006-11-20 | 2008-02-11 | 동부일렉트로닉스 주식회사 | Method for manufactruing image sensor |
| KR100954905B1 (en) * | 2007-12-24 | 2010-04-27 | 주식회사 동부하이텍 | Method for Manufacturing of Image Sensor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2667390B2 (en) | Semiconductor device manufacturing method | |
| US6514785B1 (en) | CMOS image sensor n-type pin-diode structure | |
| US20060276014A1 (en) | Self-aligned high-energy implantation for deep junction structure | |
| KR100672729B1 (en) | Method for manufacturing of CMMS image sensor | |
| GB2242782A (en) | Process and structure for a transistor-capacitor cell | |
| TWI613816B (en) | Semiconductor device and methods for forming the same | |
| KR100731064B1 (en) | Method for manufacturing of cmos image sensor | |
| US7429496B2 (en) | Buried photodiode for image sensor with shallow trench isolation technology | |
| US8460993B2 (en) | Method for fabricating CMOS image sensor with plasma damage-free photodiode | |
| JP2000031454A (en) | Image sensor with expanded pinned photodiode and manufacture thereof | |
| US20090068784A1 (en) | Method for Manufacturing of the Image Sensor | |
| US5210049A (en) | Method of making a solid state image sensor | |
| US20090166687A1 (en) | Image Sensor and Method for Manufacturing the Same | |
| KR100720474B1 (en) | CMOS Image sensor and Method for fabricating of the same | |
| US6303421B1 (en) | Method of manufacturing CMOS sensor | |
| US7141852B2 (en) | Semiconductor device and fabricating method thereof | |
| KR20020045451A (en) | Method for fabricating CMOS image sensor | |
| KR20020045453A (en) | Method for fabricating photo diode by double photo-mask process | |
| JPH0730091A (en) | Manufacture of solid-state image sensing device | |
| KR20010061356A (en) | method for fabricating pixel of image sensor to improved doping profile of low voltage photodiodes | |
| KR100518868B1 (en) | Image sensor and manufacturing method | |
| KR100776151B1 (en) | A fabricating method of image sensor with improved high intergation | |
| KR19980072520A (en) | Manufacturing Method of Semiconductor Device | |
| US20080124830A1 (en) | Method of manufacturing image sensor | |
| KR100290883B1 (en) | Method for manufacturing of solide state image sensor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| N231 | Notification of change of applicant | ||
| WITN | Withdrawal due to no request for examination |