KR20020043936A - Computing system capable of controlling program operation velocity - Google Patents

Abstract

PURPOSE: A computing system for controlling the operation speed of the program is provided to control computer operation speed by controlling each module of the program. CONSTITUTION: The computing system for controlling the program operation speed comprises a memory(22) storing the information of the operation speed of the modules composing the program, a CPU(20) including a logic operation circuit(24), and an operation speed controller(40) providing a clock signal having a frequency confronting to respective operation speeds of the modules by responding to an instruction signal. When a driving signal is inputted from the external, the logic operation circuit generates the instruction signal confronting to respective operation speed of the modules based on the information stored in the memory. The CPU operates the program by responding to the clock signal.

Description

COMPUTING SYSTEM CAPABLE OF CONTROLLING PROGRAM OPERATION VELOCITY}

The present invention relates to a computing system, and more particularly to a computing system that can control the operating speed of the program.

In general, a computing system embeds a predetermined program and drives the program according to an external driving command. Such computing systems are being developed to execute programs at high speed.

Meanwhile, a program for driving a computing system may be composed of various modules that perform various operations. Some of the modules of such a program necessarily need to operate at high speed, while there may be any module that is not high speed. For example, a module for data processing requires high speed operation, but waiting modules waiting for user input may not be high speed.

However, the conventional computing system always operates at a high speed regardless of the operation speed required by each module. Therefore, the conventional computing system has a problem that the power consumption is large.

An object of the present invention is to provide a computing system capable of controlling the operation speed of a program for each module constituting the program, in order to effectively solve the above problems of the prior art.

1 is a block diagram schematically illustrating a configuration of a computing system capable of controlling an operation speed of a program according to an exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an operation speed controller of FIG. 1.

3 is a flowchart illustrating a process of controlling an operating speed of a program in the computing system of FIG. 1.

<Description of the symbols for the main parts of the drawings>

10: input unit 20: central processing unit

30: output unit 40: operation speed control unit

One aspect of the present invention for achieving the above object relates to a computing system for driving a program in response to a user's command input through an external input device, and outputs the execution result of the program to the output device. The computing system of the present invention includes a memory for storing information on an operation speed of modules constituting the program, and a module of the program based on information stored in the memory when a driving signal for the program is input from the outside. A central processing unit having a logic operation circuit for generating an instruction signal corresponding to each operation speed; And an operation speed controller configured to generate a clock signal having a frequency corresponding to an operation speed of each of the modules of the program in response to the indication signal, and provide the clock signal to the central processing unit, wherein the central processing unit is configured to respond to the clock signal. Run the program.

Hereinafter, a computing system capable of controlling an operation speed of a program according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3. Referring to FIG. 1, the computing system of the present invention includes an input unit 10, a central processing unit 20, an output unit 30, and an operation speed control unit 40.

The input unit 10 is connected to the central processing unit 20 and is configured to allow a user to input a driving command of a program. In addition, the input unit 10 converts a user's command input through it into an electrical signal and transmits the command to the central processing unit 20. On the other hand, the input unit 10 may be implemented in various forms, such as a keyboard, a mouse, etc. Since this is a known technique, detailed description of each component of the input unit 10 will be omitted.

The central processing unit 20 is connected to the output unit 30 and the operation speed control unit 40, when the user's driving command is input through the input unit 10, the output unit 30 based on the driving command And control the operation of the operation speed controller 40. The central processing unit 20 includes a memory 22 and a logic operation circuit 24. The memory 22 stores a program and information on an operating speed of modules constituting the program. Information on the operation speed of the modules stored in the memory 22 may be set by the user using the input unit 10. The logic operation circuit 24 drives a program in response to a program driving command of a user input through the input unit 10. In addition, during the execution of the program, the logic operation circuit 24 requests and receives information on the operation speed of each module stored in the memory 22. In addition, the logic operation circuit 24 determines whether each module of the program is set to operate at the maximum operating speed of the computing system (hereinafter referred to as "reference speed") or the reference speed through the information transmitted from the memory 22. Check if it is set to run at different speed. As a result of the check, when the module of the program is set to operate at a speed different from the reference speed, the logic operation circuit 24 outputs an instruction signal VIDC corresponding to the operation speed of each module. On the other hand, when the check result shows that each module of the program is set to operate at the reference speed, the logic operation circuit 24 drives each module at the reference speed.

At this time, the output unit 30 outputs the execution result of the program driven by the logic operation circuit 24.

The operation speed control unit 40 outputs a clock signal CLK having a frequency corresponding to the operation speed of each module in response to the instruction signal VIDC output from the logic operation circuit 24 of the central processing unit 20. Transmission to the central processing unit 20. The operation speed control unit 40 according to the present embodiment is described as a deceleration circuit for slowing down the operation speed of each module. As described above, the operation speed control unit 40 according to the present embodiment includes a command signal transmission line 42 for guiding the command signal VIDC output from the central processing unit 20 and a first signal connected in series with each other. And second resistor-capacitor circuits 44 and 46. In this case, a common node to which the instruction signal transmission line 42 is connected, that is, the instruction signal receiver N45, is formed at the junction of the first and second RC circuits 44 and 46. The voltage level of the indication signal VIDC is substantially coincident with the power supply voltage VCC when the module is set to operate at high speed, and is floated when it is set to operate at low speed. The first RC circuit 44 is formed between the central processing unit 20 and the indication signal receiving terminal N45 and includes a first resistor 44a and a first capacitor 44b connected in parallel with each other. The second RC circuit 46 is formed between the indication signal receiving terminal N45 and the power supply voltage VCC and includes a second resistor 46a and a second capacitor 46b connected in parallel with each other. Accordingly, when the voltage level of the indication signal VIDC substantially coincides with the power supply voltage VCC, the potential difference between the indication signal receiving end N45 and the second RC circuit 44 is substantially zero (zero). And the power supply voltage VCC input to the central processing unit 20 is provided to the first RC circuit 44. When the voltage level of the indication signal VIDC is floated, the power supply voltage VCC input to the second RC circuit 46 is provided to the first RC circuit 44.

3 is a flowchart illustrating a process of controlling an operating speed of a program in the computing system of FIG. 1. 1 to 3, when a driving command for a program is input to the central processing unit 20 through the input unit 10 (S110), the logic operation circuit 24 of the central processing unit 20 is programmed. Drive (S210). In addition, during execution of the program, the logic operation circuit 24 checks the operation speed of each module by requesting information on the operation speed of each module constituting the program stored in the memory 22 (S130).

In operation S130, when the operation speed of the module is set to be lower than the reference speed, the central processing unit 20 outputs an indication signal VIDC to the operation speed controller 40 (S140). When the voltage level of the indication signal VIDC substantially matches the power supply voltage VCC, the operation speed controller 40 generates the clock signal CLK using only the first RC circuit 44 (S150). ). In other words, when the voltage level of the indication signal VIDC substantially coincides with the power supply voltage VCC, the potential difference between the indication signal receiving terminal N45 and the second RC circuit 46 is substantially zero (zero). Therefore, the first RC circuit 44 receives the power supply voltage VCC input to the central processing unit 20 to generate a clock signal CLK having a frequency corresponding to the operation speed (relatively high speed) of the module. When the voltage level of the indication signal VIDC is floated, the operation speed controller 40 generates the clock signal CLK using the first and second RC circuits 44 and 46 (S150). In other words, when the voltage level of the indication signal VIDC is floated, the first RC circuit 44 receives the power supply voltage VCC through the second RC circuit 46 to operate at a relatively low speed of the module of the program. Generates a clock signal CLK having a frequency corresponding to Here, the clock signal CLK has a frequency for driving a module of a program at a speed slower than a reference speed.

Subsequently, the operation speed controller 40 provides the generated clock signal CLK to the central processing unit 20 (S160). In this case, the CPU 20 drives a module of the program slower than the reference speed in response to the clock signal CLK provided thereto. At this time, the execution result of the program is output on the output unit 30. Accordingly, since power consumed to drive the program becomes smaller than power consumed when the selected program is driven at the reference speed, the power consumption of the computing system can be reduced.

On the other hand, in the checking step (S130), when the module of the program is set to drive at the reference speed of the computing system, the central processing unit 20 drives the module without generating an indication signal. At this time, the execution result of the program is output on the output unit 30.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. . For example, in the above-described embodiment, the operation speed controller 40 includes only one indication signal transmission line 42 to drive the operation speed of a program only at a reference speed or a specific speed slower than the reference speed. In another embodiment of the present invention, the operation speed control unit 40 includes a plurality of indication signal transmission lines to which different signals are input, and various types of deceleration circuits to which the respective indication signal transmission lines are connected to drive the program at various operation speeds. Can be implemented. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, in the computing system capable of controlling the program operating speed of the present invention, each module of the program is operated at an appropriate speed, so that the power consumption is significantly reduced compared to the conventional computing system which is always driven at a constant speed. Has the effect of becoming.

Claims (6)

A computing system for driving a program in response to a user's command input through an external input device and outputting a result of executing the program to an output device, Memory corresponding to the operating speed of the modules constituting the program, and when a drive signal for the program is input from the outside, corresponding to the operating speed of each of the modules of the program based on the information stored in the memory A central processing unit having a logic operation circuit for generating an instruction signal to dictate; And An operation speed controller configured to generate a clock signal having a frequency corresponding to an operation speed of each of the modules of the program in response to the indication signal and provide the clock signal to the central processing unit; And the central processing unit controls the operation speed of the program, in response to the clock signal. The method of claim 1, wherein the operation speed control unit And a deceleration circuit for slowing the operation speed of the program below a predetermined reference operation speed. The method of claim 2, wherein the deceleration circuit Computing system capable of controlling the operating speed of the program, characterized in that it comprises a plurality of RC circuits arranged in series. The method of claim 2 or 3, wherein the deceleration circuit An instruction signal receiver for receiving the instruction signal provided from the central processing unit; A first RC circuit formed between the indication signal receiving end and the central processing unit; And A second RC circuit formed between the indication signal receiving terminal and a power supply voltage; The voltage level of the indication signal is And a power supply voltage or a float corresponding to an operating speed of each of the modules of the program. The method of claim 4, wherein the first RC circuit Computing system capable of controlling the operating speed of a program comprising a first resistor and a first capacitor connected in parallel with each other. The method of claim 5, wherein the second RC circuit Computing system capable of controlling the operating speed of the program, characterized in that it comprises a second resistor and a second capacitor connected in parallel with each other.