KR20020037397A - Adaptive digital filter - Google Patents

Abstract

PURPOSE: An adaptive digital filter is provided to sharply reduce a size by removing a selector between a plurality of blocks having a plurality of taps. CONSTITUTION: An input data delay section(d0-d3) receives input data. The input data delay section(d0-d3) includes a plurality of delay elements which are connected to one another to form a loop. A plurality of counting data delay sections(d0-d15,d'0-d'15) upgrades a counting value based on an operation of output data and an error signal of each stage in the input data delay section(d0-d3). An output data delay section(d''0- d''3) outputs filtered data based on each counting data from the plurality of counting data delay section(d0-d15,d'0-d'15) and the input data. The output data delay section(d''0-d''3) includes a plurality of delay elements which are connected to one another to form a loop.

Description

Adaptive digital filter {ADAPTIVE DIGITAL FILTER}

The present invention relates to an adaptive digital filter suitable for an adaptive equalizer in a digital signal processing apparatus. In particular, the present invention is directed to providing an adaptive digital filter whose size is reduced due to a simple configuration by removing selectors installed between a plurality of blocks each performing a time division multiplexing operation and sequentially transmitting data between the blocks. will be.

In general, adaptive equalizers are widely used in the field of telecommunications and can adaptively adapt the linear amplitude and phase distortion of digital data transmitted from channels that are varied by various factors such as the transceiver's location, distance, terrain, buildings, and weather. It is used to equalize or compensate.

The adaptive equalizer consists of an error signal generator, an adaptive digital filter and a coefficient updater. In this configuration, the adaptive digital filter occupies the largest area occupied by the adaptive equalizer, and is a finite impulse response filter having a finite response characteristic in time with respect to a unit input. Filter ('FIR') and Infinite Impulse Response, in which the unit sampling response continues infinitely in time.

Recently, researches for minimizing the size of the above-described finite impact response filter (FIR) generally employed in the adaptive digital filter have been actively conducted.

The construction of the finite shock response filter was disclosed in October 1998 by Kamran Azadet and Chris J. Nicole, LOW-POWER EQUALIZER ARCHITECTURES FOR HIGH-SPEED MODEMS, IEEE Communications Magazine. Fig. 11 (b) of page 122 shows a direct form filter structure employing time division multiplexed multipliers. The structure thereof is converted into a transposed form as shown in FIG. 1.

As can be seen in FIG. 1, the data input Xn, which is a discrete time sequence, is received as input data for each channel. Where n represents the sampling time position. The input data Xn is sequentially input for each operation period by the plurality of input data delay loops d0 to d3, d4 to d7, d8 to d11, and d12 to d15. The input data sequentially delayed and output by the delay element d of each input data delay loop is generated by an error signal generator (not shown) by the multipliers 22, 28, 34 and 40. Is multiplied by). This error signal En is expressed as a value including the adaptive step size μ. A plurality of coefficient data delay loops d'0 to d'3, d'4 to d'7, d'8 to d'11, d for performing coefficient update on the multiplied data value X _nk mu En Coefficients are adapted or updated as in Equation (1).

Where μ is an adaptation step size as a positive constant.

Subsequently, the coefficient updated data C _n and the input data X _n are multiplied by the multipliers 18, 24, 30, and 36. The data values C _n X _n multiplied by the multipliers 18, 24, 30, 36 are input to the adders 42, 44, 46, 48. Adders 42, 44, 46, and 48 add multiple outputs selected from respective selectors 10, 12, 14, and 16 and the multiplied data values C _n X _n to form a plurality of digital filtering data delay loops. and outputs (d "0 to d" 3, d "4 to d" 7, d "8 to d" 11, and d "12 to d" 15), respectively. Each of the digital filtering data delay loops d " 0 to d " 3, d " 4 to d " 7, d " 8 to d " 11, d " 12 to d " 15 sequentially delays the input data, As shown in Equation 2, the converged digital filtering data Yn is output.

Where Xn is the input data

Yn is the output data

Ck is the k th tap weighting {k = 0,1,2, ..., N-1}

On the other hand, the finite shock response filter having the above configuration is designed to allow the multiplier to perform time division multiplexing operation. That is, the required filter operation period T is divided by an integer multiple to operate in synchronization with the divided clock. For example, a block made up of a plurality of taps (that is, dn, d'n, d " n) that operates according to each clock divided into quarters of the required filter operation period T, Parallel data processing is performed using 100, 200, 300, and 400 as shared units.

With this time division multiplexing operation, in the case of FIG. 1, four taps are provided for every four blocks, and the total number of taps is 16 and the filter operation clock is four times. It replaces the function. That is, the number of twelve taps is reduced.

However, in this arrangement, as shown in Fig. 2, each block 100, 200, 300, 400 capable of performing each of the four tap operations operates independently. In order to control the sequential data transfer between these blocks, the selectors 4, 6, 8, for alternately selecting and outputting the input data Xn and the output data Yn according to the control signal SEL between the blocks. 12, 14, 16 must be provided, so that the size of the filter is increased. Furthermore, when the number of taps is increased, the transmission length of the control signal of the selector is increased, thereby degrading the stability of the operation timing.

Accordingly, an object of the present invention is to provide a digital filter which is greatly reduced in size by removing a selector between a plurality of blocks composed of a plurality of taps.

Another object of the present invention is to provide a digital filter that is easy to design by having a simple configuration.

Another object of the present invention is to provide a digital filter for performing a stable filtering operation.

The above object is achieved by the digital filter of the present invention having a new hardware configuration.

The present invention eliminates the selector installed between blocks consisting of a plurality of tabs. As a result, the area of the digital filter is greatly reduced, and the length of the control line for controlling the operation of the selector is reduced, thereby improving the stability of the filtering operation.

In addition, a plurality of input data delay loops and a plurality of output data delay loops for sequentially transmitting data between blocks are designed in the form of a single loop.

According to one aspect of the present invention, an input data delay unit for forming a loop in which a plurality of delay elements are directly connected to each other as a unit of stages to receive input data; A plurality of coefficient data delay units for updating coefficients based on calculation of output data and error signals for each stage of the input data delay unit; In order to output the coefficient data from the plurality of coefficient data delay units and the filtered data based on the operation of the input data, a plurality of delay elements are directly connected to each other as a unit of a stage and have an output data delay unit having a loop. Digital filters are provided.

Further features, objects, and advantages of the adaptive digital filter of the present invention will now become more apparent from the detailed description according to the configuration of the present invention with reference to the drawings.

1 is a circuit diagram of a finite impact response filter according to the prior art.

2 is a block diagram according to the configuration of FIG.

3 is a block diagram of a finite impact response filter in accordance with an embodiment of the present invention.

4 is a block diagram of a receiver for HDTV for explaining the position of the finite shock response filter according to the present invention;

5 is a detailed circuit diagram according to the configuration of FIG. 3.

6 is an operational waveform diagram according to the T / 4 filter operation clock in accordance with one embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

Ⅰ (d0 ~ d15): Input data delay loop

II (d'0 to d'3, d'4 to d'7, d'8 to d'11, d'12 to d'15): Coefficient data delay loop

III (d "0 to d" 15): Output data delay loop

56, 62, 68, 74: first multiplier group

58, 64, 70, 76: first adder group

54, 60, 66, 72: second multiplier group

78, 80, 82, 84: second adder group

52: first selector

86: second selector

50 (d50): delay element

In digital signal processing, for example, digital data used for a high definition television (HDTV) broadcast signal is delivered to a user through an analog channel such as Very High Frequency (VHF) or Ultra High Frequency (UHF). The waveform delivered by the analog channel represents frequency distortion, nonlinear or harmonic distortion, and time dispersion.

In order to transmit digital data over such an analog channel, the data is typically modulated using Pulse Amplitude Modulation (PAM) and is typically used to increase the amount of data that can be transmitted within the available channel bandwidth. Quadrature Amplitude Modulation (QAM) technology is used.

QAM transmits a plurality of, for example, 16 or 32 symbol data in a "constellation" pattern in the form of PAM.

In pulse amplitude modulation, each signal has the form of a pulse whose amplitude level is determined by the transmitted symbol. In 16 QAM, 16 symbols are used that may have positions of, for example, -3, -1, 1, and 3 in each quadrature symbol space (ie, constellation or symbol plane) channel.

In an efficient digital signal processing apparatus, each symbol transmitted over a discrete time channel is increased by a time interval used to represent the symbol by multipath channel effects. As such, the distortion generated by the overlap of the received symbols is referred to as inter-symbol interference (ISI).

The transposed finite shock response filter (FIR) according to the present invention is used to minimize signal distortion, such as intersymbol interference (ISI) of the transmitted symbols.

As shown in Fig. 3, the adaptive finite shock response filter of the present invention comprises a digital filter portion 500, selectors 52, 86 and a delay element 50. The digital filter unit 500 of the finite impact response filter of the present invention removes the selector for controlling data transmission between blocks unlike the conventional technology.

The digital filter unit 500 operates in synchronism with a filter operation clock of 4x, which divides the operating frequency T of the filter required for performing the time division multiplexing operation into, for example, 1/4.

In addition, the digital filter unit 500 operates according to a least mean square error adaptive filtering algorithm that repeatedly updates the filter coefficients of the digital filter unit according to a predetermined convergence condition. For reference, these algorithms were described in August 1960, IRE Wescon Conv. Rec., Part 4, pp. 96-104, entitled B. Windrow and M.E., entitled "Adaptive Switching Circuits." Presented by Hoff, Jr. A method for removing the signal distortion using the LMS algorithm is described in September 1987, Proc. IEEE, Vol. 73, No. 9, pp. 1349-1387, entitled S.U.H. It was discussed by Qureshi.

As shown in Figure 4, the input data Xn is modulated using QAM technology and transmitted over the multipath channel 1 of the VHF or UHF transmission, followed by realization by a quadrature demodulation (3). The component of the part and the imaginary part is a symbol of the complex component extracted. In addition, the input data Xn received by the finite shock response filter 5 includes intersymbol distortion (ISI) generated by amplitude and / or delay distortion generated by a multipath channel effect. The finite impact response filter 5 filters the input data Xn by using updated coefficient data as in the prior art. As a result, the filtered data Yn of the complex component in which the intersymbol distortion component is minimized is output. The coefficient update data is updated by an error signal En generated from an error signal generator (not shown), which is calculated using the filtered data output. The data filtered by the finite shock response filter 5 is input to the decoder 7 and restored as transmitted information data.

3, the delay element 50 of the finite-impact response filter is the input data 51 (the output of the delay element d15 of 'I' of FIG. 5) which is finally delayed out of the input data delay loop to be described later. Temporarily save and output. All delay elements presented herein, including delay element 50, are shift registers connected in series to each other's inputs and outputs, and store complex components with binary information by integer multiples of the filter's operating clock and into adjacent registers. It is designed to move unidirectional seats.

The selector 52 is connected to the delay element 50 to receive the output data and the input data Xn of the delay element 50. The selector 52 selects the output data of the delay element 50 or the input data Xn according to the selection control signal SEL1, and selects the delay element of the first sequence of the input data delay loop of the digital filter unit 500. Output to d0) in FIG.

In addition, the selector 86 is controlled by the selection control signal SEL2, and the delay element 87 ('III' of FIG. 5) is sequentially delayed immediately before &quot; 0 &quot; or the filter output finally output in the output data delay loop. output of d " 1) is selected and output to the first delay element d " 15 of the output data delay loop. Here, the selectors 52 and 86 are conventional multiplexers.

5 shows a more detailed configuration of the digital filter unit 500.

Prior to the detailed description, the digital filter unit 500 of the present invention replaces the function of the existing 16 taps by the number of four taps by a time division multiplexing operation. However, the present invention is not limited thereto, and if the filter operation clock is driven at 8 times speed, the number of four taps can replace the function of 32 taps.

As shown in FIG. 5, the digital filter unit 500 of the finite impact response filter according to the present invention receives the input data Xn to be digitally filtered and is calculated based on the digitally filtered output data Yn. Receive an error signal En.

The digital filter unit 500 inputs the input data delay loop I (d0 to d15) and the coefficient data delay loop II (d'0 to d) for the coefficient update by the error signal and the digital filtering of the input data Xn. '15), output data delay loop III (d "0 to d" 15), first multiplier group 56, 62, 68, 74, first adder group 58, 64, 70, 76, second multiplier Groups 54, 60, 66, 72, and second adder groups 78, 80, 82, 84.

Here, the delay elements forming each loop are connected in series by four in the lateral direction to form one stage, respectively. Four input data delay elements d0 to d3, four coefficient data delay elements d'0 to d'3, and four output data delay elements d "0 to d" 3 form one block. Forming. In addition, the longitudinal delay elements dn, d'n, and d "n each form tabs.

In the input data delay loop I (d0 to d15), four stages, a total of 16 delay elements are connected in series. These sixteen delay elements sequentially output the stored data from right to left in accordance with, for example, four times the filter operation clock (4xclock) of the received input data Xn.

In coefficient data delay loop II (d'0 to d'15), four stages, a total of 16 delay elements, are connected in series. These sixteen delay elements cycle coefficient data Cn in each stage according to, for example, four times the filter operation clock, and sequentially output the data stored in the right-to-left direction.

As mentioned above, the coefficient is updated according to the error signal extracted from the previous filtering operation for use in the next filtering operation.

In the output data delay loop III (d "0 to d" 15), four stages, a total of 16 delay elements are connected in series. These sixteen delay elements sequentially output the data stored in the left to right direction according to the filtered output data (Yn) four times the filter operation clock.

Each multiplier of the multiplier groups 56, 62, 68, and 74 multiplies the output of each stage of the input data delay loop by the error signal En.

Each adder of adders group 58, 64, 70, and 76 adds the output of each multiplier 56, 62, 68, 74 and the updated coefficient data of each stage of the coefficient data delay loop. The outputs of adders 58, 64, 70, and 76 are fed back to the coefficient data delay stage.

Each multiplier of the multiplier groups 54, 60, 66, and 72 multiplies the output of each stage of the coefficient data delay loop by the input data Xn and outputs the multiplied output.

Each adder in the adder group 78, 80, 82, 84 adds the output of the multiplier 54, 60, 66, 72 and the previous output of each stage of the output data delay loop to obtain digitally filtered output data Yn. Output

Here, the multipliers and the adders forming each group are designed to process binary data of complex components output from each delay element.

The data shift operation of the input data delay loop and the output data delay loop of the present invention having the above configuration will be described with reference to Table 1 and FIG. 6 below.

d50 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d150 X ₁ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 X ₁ 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 X ₁ 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 X ₁ 0 0 0 0 0 0 0 0 0 0 0 00 X ₂ 0 0 0 X ₁ 0 0 0 0 0 0 0 0 0 0 00 0 X ₂ 0 0 0 X ₁ 0 0 0 0 0 0 0 0 0 00 0 0 X ₂ 0 0 0 X ₁ 0 0 0 0 0 0 0 0 00 0 0 0 X ₂ 0 0 0 X ₁ 0 0 0 0 0 0 0 00 X ₃ 0 0 0 X ₂ 0 0 0 X ₁ 0 0 0 0 0 0 00 0 X ₃ 0 0 0 X ₂ 0 0 0 X ₁ 0 0 0 0 0 00 0 0 X ₃ 0 0 0 X ₂ 0 0 0 X ₁ 0 0 0 0 00 0 0 0 X ₃ 0 0 0 X ₂ 0 0 0 X ₁ 0 0 0 00 X ₄ 0 0 0 X ₃ 0 0 0 X ₂ 0 0 0 X ₁ 0 0 00 0 X ₄ 0 0 0 X ₃ 0 0 0 X ₂ 0 0 0 X ₁ 0 00 0 0 X ₄ 0 0 0 X ₃ 0 0 0 X ₂ 0 0 0 X ₁ 00 0 0 0 X ₄ 0 0 0 X ₃ 0 0 0 X ₂ 0 0 0 X ₁ X ₁ X ₅ 0 0 0 X ₄ 0 0 0 X ₃ 0 0 0 X ₂ 0 0 00 X ₁ X ₅ 0 0 0 X ₄ 0 0 0 X ₃ 0 0 0 X ₂ 0 00 0 X ₁ X ₅ 0 0 0 X ₄ 0 0 0 X ₃ 0 0 0 X ₂ 00 0 0 X ₁ X ₅ 0 0 0 X ₄ 0 0 0 X ₃ 0 0 0 X ₂ X ₂ X ₆ 0 0 X ₁ X ₅ 0 0 0 X ₄ 0 0 0 X ₃ 0 0 00 X ₂ X ₆ 0 0 X ₁ X ₅ 0 0 0 X ₄ 0 0 0 X ₃ 0 00 0 X ₂ X ₆ 0 0 X ₁ X ₅ 0 0 0 X ₄ 0 0 0 X ₃ 00 0 0 X ₂ X ₆ 0 0 X ₁ X ₅ 0 0 0 X ₄ 0 0 0 X ₃ ... XX ₁₆ X ₁₂ X ₈ X ₄ X ₁₃ X ₉ X ₅ X ₁ X ₁₄ X ₁₀ X ₆ X ₂ X ₁₅ X ₁₁ X ₇ X ₃

Table 1 describes the operation of the delay elements d50 and d0 to d15 constituting the input data delay loop for updating the coefficients. In the initial operation, zero is set for all delay elements of the input data delay loop by the reset signal reset. When the reset signal is LOW, each output signal Xn_sign_in to Yn is " U ", that is, unknown data (Unknown) is output.

As is well known, the adaptive digital filter of the present invention is designed to operate at a clock speed obtained by dividing the filter operating frequency required for the time division multiplexing operation by an integer multiple. For example, the digital filter of the present invention operates in synchronization with a clock obtained by dividing the required filter operating frequency clk_Fs by a quarter, that is, a clock speed four times higher. However, the present invention is not necessarily limited thereto, and may be designed to operate at a clock speed of 8 times divided by 1/8 of the required filter operating frequency clk_Fs.

As can be seen from the waveform of FIG. 6 and Table 1 above, the reset signal becomes HIGH, and during the first operation period divided into T / 4 periods of the X1 interval, the control signal SEL1 of the selector becomes HIGH to selector ( X _{1, which} is an output signal Xn_sign_in of 52), is selected. This selected X ₁ is stored in the first delay element d0 of the input data delay loop I. At this time, the output signals EnXn_0 to 3 of the multiplier groups 56, 62, 68, and 74, the coefficient signals Cn_0 to 3 output from the adder groups 58, 64, 70, and 76, and the multiplier groups 54, 60, The data of the output signals tdl_0 to 3_in of 66, 72) are generated as shown in FIG. During the remaining operation period, the control signal SEL1 of the selector becomes LOW, and the data stored in the delay element d50, which is the data output from the delay element d15, is indicated by " L " Is selected and output.

In Fig. 6, data Cn is a coefficient to be stored in the nth delay element of the coefficient data delay loop (II), for example, during the first operation period divided into T / 4 periods of the X1 interval, C1 is the delay element d'0, C2 is stored in delay element d'4, C3 is stored in delay element d'8, and C4 is stored in delay element d'12. For the next second period, for example, C1 is shifted to d'1 and C5 is stored as d'0. C6, C7, and C8 are also stored as above. In this way, the coefficients of C1 to C16 in the X1 period are stored in the respective storage units in accordance with the divided clocks.

The data Tn is a filtering output to be stored in the nth delay element of the output data delay loop (III). For example, during the first operation period divided into T / 4 periods in the X1 period, T1 is delay element d "3 and T2 is delay. In element d "7, T3 is stored in delay element d" 11 and T4 is stored in delay element d "15. For the next second period, for example, T1 is shifted to d "2 and T5 is stored as d" 3. T6, T7, and T8 are also stored as above. In this way, the filtered data of T1 to T16 is stored in the respective storage units in the X1 section.

Again, during the first operation period of T / 4 of the filter operating frequency during the next X2 period, similarly to the above, the control signal SEL1 of the selector becomes HIGH and the new input data as the output signal Xn_sign_in of the selector 52. X ₂ is selected and output. At this time, the input data X ₁ stored in the delay element d3 is shifted to the next delay element d4.

In FIG. 6, data Dn is a coefficient to be stored in the n + 1 th delay element, for example, during the first operation period divided into T / 4 periods in the X2 period, D1 is delay element d'0, and D2 is delay element d '. At 4, D3 is stored in delay element d'8 and D4 is stored in delay element d'12. For the next second period, for example, D1 is shifted to d'1 and D5 is stored as d'0. D6, D7, and D8 are also stored as above. In this way, the coefficients of D1 to D16 are stored in the storage unit in accordance with the divided clock in the X2 period. En is a coefficient to be stored in the n + 2th delay element.

The data Kn is a filtering output to be stored in the n + 1 th delay element of the output data delay loop III. For example, during the first operation period divided into T / 4 periods during the X2 period, K1 is the delay element d "3 and K2. Is stored in delay element d "7, K3 is stored in delay element d" 11, and K4 is stored in delay element d "15. For the next second period, for example, K1 is shifted to d "2 and K5 is stored as d" 3. K6, K7, and K8 are also stored in the same way. As such, the filtered data of K1 to K16 is stored in the storage unit during the X2 period.

From Table 1 and Figure 6, it can be seen that the four tap spacings are maintained between the delay elements together with the data storage sequence. However, if the multiplexing operation is performed by dividing the required filter operating frequency by eight, it may be easily inferred that two tap intervals are maintained between the delay elements.

Now, look at Table 2 to see the data shift behavior of the registers that make up the output data delay loop that operates at 4-tap intervals.

d "15 d" 14 d "13 d" 12 d "11 d" 10 d "9 d" 8 d "7 d" 6 d "5 d" 4 d "3 d" 2 d "1 d" 0Y ₄ 0 0 0 Y ₃ 0 0 0 Y ₂ 0 0 0 Y ₁ 0 0 0Y ₈ Y ₄ 0 0 Y ₇ Y ₃ 0 0 Y ₆ Y ₂ 0 0 Y ₅ Y ₁ 0 0Y ₁₂ Y ₈ Y ₄ 0 Y ₁₁ Y ₇ Y ₃ 0 Y ₁₀ Y ₆ Y ₂ 0 Y ₉ Y ₅ Y ₁ 0Y ₁₆ Y ₁₂ Y ₈ Y ₄ Y ₁₅ Y ₁₁ Y ₇ Y ₃ Y ₁₄ Y ₁₀ Y ₆ Y ₂ Y ₁₃ Y ₉ Y ₅ Y ₁ Y ₅ Y ₁₆ Y ₁₂ Y ₈ Y ₄ Y ₁₅ Y ₁₁ Y ₇ Y ₃ Y ₁₄ Y ₁₀ Y ₆ Y ₂ Y ₁₃ Y ₉ Y ₅ Y ₉ Y ₅ Y ₁₆ Y ₁₂ Y ₈ Y ₄ Y ₁₅ Y ₁₁ Y ₇ Y ₃ Y ₁₄ Y ₁₀ Y ₆ Y ₂ Y ₁₃ Y ₉ Y ₁₃ Y ₉ Y ₅ Y ₁₆ Y ₁₂ Y ₈ Y ₄ Y ₁₅ Y ₁₁ Y ₇ Y ₃ Y ₁₄ Y ₁₀ Y ₆ Y ₂ Y ₁₃ Y ₁₇ Y ₁₃ Y ₉ Y ₅ Y ₁₆ Y ₁₂ Y ₈ Y ₄ Y ₁₅ Y ₁₁ Y ₇ Y ₃ Y ₁₄ Y ₁₀ Y ₆ Y ₂ Y ₆ Y ₁₇ Y ₁₃ Y ₉ Y ₅ Y ₁₆ Y ₁₂ Y ₈ Y ₄ Y ₁₅ Y ₁₁ Y ₇ Y ₃ Y ₁₄ Y ₁₀ Y ₆ Y ₁₀ Y ₆ Y ₁₇ Y ₁₃ Y ₉ Y ₅ Y ₁₆ Y ₁₂ Y ₈ Y ₄ Y ₁₅ Y ₁₁ Y ₇ Y ₃ Y ₁₄ Y ₁₀ Y ₁₄ Y ₁₀ Y ₆ Y ₁₇ Y ₁₃ Y ₉ Y ₅ Y ₁₆ Y ₁₂ Y ₈ Y ₄ Y ₁₅ Y ₁₁ Y ₇ Y ₃ Y ₁₄ Y ₃ Y ₁₄ Y ₁₀ Y ₆ Y ₁₇ Y ₁₃ Y ₉ Y ₅ Y ₁₆ Y ₁₂ Y ₈ Y ₄ Y ₁₅ Y ₁₁ Y ₇ Y _{3 · ·}

The rightmost Y value in Table 2 is the output data of the final delay element d "0 of the output data delay loop III. As can be seen from Table 2 and Figure 6, the last of the operating period of T / 4, The control signal SEL2 of the selector 86 becomes HIGH in the operation period and keeps LOW in the remaining operation cycles. When the control signal SEL2 of the selector 86 becomes HIGH, the value of the output 85 is "0." Is selected and output. At this time, the input value 0 is added by the adder 78 to tdl_3_in, which is the output value of the multiplier 54, and stored in the first delay element d "15 of the output data delay loop III. . The output of the delay element d "0 at this time becomes a filtering output.

During the remaining LOW periods of the selector 86, the output of the delay element d "1 is selected and output. At this time, the output of the delay element d" 1 is output by the adder 78 by the output value of the multiplier 54. Is added to tdl_3_in and stored in the first delay element d "15 of the output data delay loop III. The output data delay loop III repeats the above-described operation and accumulates and converges at each stage. Create

As described above, the present invention removes the selector provided between the plurality of blocks of the digital filter, and performs the same operation as each shared block as one shared unit. For this purpose, a plurality of conventional input data delay loops and a plurality of output data delay loops are configured in the form of a single loop.

Therefore, a selector for sequential transmission of data between blocks is conventionally unnecessary, so that the size of the digital filter is greatly reduced. In addition, the stability of the operation timing is increased by reducing the transmission length of the control signal for controlling the selector.

As mentioned above, although the conventional exemplary embodiment of the present invention has been described in which a plurality of input data delay loops and a plurality of output data delay loops are designed as a single loop to perform a filtering operation, the present invention is not necessarily limited thereto. There may be various various embodiments within the scope of the technical idea described in.

In addition, the configuration of the digital filter according to the present invention can be applied to any adaptive filter, equalizer or other electrical filter device.

In addition, the configuration of the digital filter according to the present invention may be applied to the analog filter by replacing the multiplier, the adder and the register with the analog element.

Claims (16)

In the digital filter, An input data delay unit in which a plurality of delay elements are directly connected to each other as a unit of stages to receive input data to form a loop; A plurality of coefficient data delay units for updating coefficients based on calculation of output data and error signals for each stage of the input data delay unit; In order to output the coefficient data from the plurality of coefficient data delay units and the filtered data based on the operation of the input data, a plurality of delay elements are directly connected to each other as a unit of a stage and have an output data delay unit having a loop. Digital filter, characterized in that. The digital filter of claim 1, further comprising a first selector connected to the input data delay unit to select and output one of new input data and last delayed input data. 2. The digital filter of claim 1, further comprising a second selector connected to the output data delay unit for selecting and outputting any one of "0" or an output immediately before the filter output. 3. The digital filter of claim 2, further comprising a delay element connected to an input of the first selector for temporarily storing and outputting the last delayed input data. 2. The digital filter of claim 1, wherein the digital filter performs a time division multiplexing operation in synchronization with a filter operation clock of N times the operation frequency T of the filter divided by 1 / N. 6. The first selector according to any one of claims 2, 4 and 5, wherein the first selector selects and outputs the new input data during the first operation period among the predetermined multiple divided operation periods of the filter operating frequency and the remaining operation. And selecting and outputting the last delayed input data stored in the delay element during the period. 6. The filter of claim 3 or 5, wherein the second selector selects and outputs the data of " 0 " during the last operation period among predetermined operating periods divided by a predetermined number of filter operating frequencies, and the filter output bar for the remaining operation periods. A digital filter, characterized in that for selecting and outputting the output of the entire sequence. The method of claim 1, wherein the digital filter, A first multiplier group multiplying the output data of the input data delay unit by the error signal; A first adder group for adding output data of the first multiplier group and output data of the coefficient data delay unit, and outputting the added data to an input of the coefficient data delay unit for coefficient update; A second multiplier group which multiplies the input data by the coefficient data updated by the coefficient data delay unit; And a second adder group configured to add output data of the second multiplier group and data output immediately before the output data delay unit. A signal processing apparatus for recovering an input signal received from a channel, A demodulator for extracting a predetermined component of a received input signal; An input signal delay unit for receiving and delaying an output signal from the demodulator, a coefficient signal delay unit for updating coefficients according to an output signal of the input signal delay unit, and counting signals of the coefficient signal delay unit and calculation of the input signal; A filter having an output signal delay unit for outputting a filtered signal based on the filter; It includes a recovery unit for restoring the original signal from the output signal of the filter, And the input signal delay unit and the output signal delay unit of the filter form a loop in which a plurality of delay elements are directly connected to each other as a unit of a stage. 10. The signal processing apparatus of claim 9, wherein the input signal delay unit further comprises a first selector for selecting and outputting either a new input signal or a last delayed input signal. 10. The signal processing apparatus according to claim 9, wherein the output signal delay unit further comprises a second selector for selecting and outputting any one of "0" or an output immediately before the filter output. 11. The signal processing apparatus according to claim 10, further comprising a delay element connected to an input of the first selector for temporarily storing and outputting the last delayed input signal. The signal processing apparatus according to claim 9, wherein the filter performs a time division multiplexing operation in synchronization with a filter operation clock of N times the operation frequency T of the filter divided by 1 / N. 14. The first selector of any one of claims 10, 12, and 13, wherein the first selector selects and outputs the new input signal during a first operation period of a predetermined multiple divided operation periods of a filter operating frequency, and the remaining operation. And during the period, select and output the last delayed input signal stored in the delay element. The filter of claim 11 or 13, wherein the second selector selects and outputs the signal of "0" during the last operation period among the predetermined operation periods divided by a predetermined frequency of the filter operation frequency, and the filter output bar during the remaining operation periods. A signal processing apparatus characterized in that for selecting and outputting the output of the entire sequence. The method of claim 9, wherein the filter, A first multiplier group multiplying the output signal by the input signal delay unit and the error signal; A first adder group that adds an output signal of the first multiplier group and an output signal of the coefficient signal delay unit, and outputs the added signal to an input of the coefficient signal delay unit for coefficient update; A second multiplier group that multiplies the input signal by the coefficient signal updated by the coefficient signal delay unit; And a second adder group configured to add an output signal of the second multiplier group and a signal output immediately before the output signal delay unit.