KR20020033906A - frame search circuit in DS3 signal - Google Patents

Abstract

PURPOSE: A DS(Digital Signal)3 signal frame search circuit is provided to search a frame pattern of a DS3 payload when demultiplexing the DS3 signals with a high speed for speedily processing the DS3 signals. CONSTITUTION: The circuit comprises an input module(10), a DS3 block generator(20), the first clock distribution generator(30), the second clock distribution generator(40), and a shift module(50). The input module(10) receives DS3 data and DS3 clocks, and reads the DS3 data with the DS3 clocks. The DS3 block generator(20), with a size of 1 frame, includes a multiple frame counter(21) for counting sub frames, a sub frame counter(22) for counting blocks, a block counter(23) for counting time slots, a DS2 counter(24) for counting the DS2 data, and a bit search module(25) for searching a frame bit placed at a set position for searching a DS3 frame pattern. The first clock distribution generator(30) and the second clock distribution generator(40) distribute the DS3 clocks by 85 and 170, respectively. The shift module(50) shifts the DS3 data of the first clock distribution generator by the DS3 clocks. The bit search module(25) includes the first, the second, and the third block which recognize the first, the second and the third data of the DS3 data as a frame bit, respectively. The shift module(50) includes the first(51), the second(52) and the third shift circuit(53) which shifts the DS3 data by the DS3 clocks and inputs the shifted DS3 data to an input terminal of the first, the second and the third block of the bit search module(25), respectively.

Description

Frame search circuit in DS3 signal

The present invention relates to a frame search circuit for a DS (Digital Signal) 3 signal, and more particularly, to a frame search circuit for quickly finding a frame pattern when demultiplexing a payload of a DS 3 signal.

The DS3 signal frame format consists of a total of 4760 bits, and there are seven subframes of 680 bits, and each subframe has eight blocks of 85 bits, and the first bit of the block is used as a control bit.

The control bits indicated by F1 and F0 of the control bits are used as bits for finding a frame pattern, and the F (Frame) bit is used when the frame search circuit finds a DS3 frame pattern to demultiplex the DS3 playload. The value is 1-0-0-1 and the interval is 170 bits.

A search block section (1) for finding the bit that is high among the DS3 data bits to find the frame, a counter block section (2) that counts 680 as the DS3 clock by considering the bit as F1, and 170 as the DS3 clock. , A check block unit 3 for counting 340, 510, and 680 and checking the F bit value 1-0-0-1 for each counting step, and the F bit (1-0-0-) of each of seven sub-frames. It consists of a final block part 4 which checks whether 1) is found.

The search block unit 1 receives a DS3 data signal and a DS3 clock as an input, reads a DS3 data signal with a DS3 clock, and if the DS3 data is high, considers the first F1 of the F bits to find the DS3 frame pattern and enables the counter block. (enable)

The counter block unit 2 is a counter block capable of reading 680 with a DS3 clock, and the interval of the F bits (1-0-0-1) is 170 bits, so that the data value is low after counting 170 in the counter unit. low, counting 170 (340 digits) to the next F bit, if not low, reset the counter and go back to the search block (1).

Check the value of data in the 340 TS (Time Slot) position as above, and the digit of the F bit (1-0-0-1) is 0 TS (Time Slot) -170 TS-340 TS-510 TS. The data value of is low. If the data value is low, counting continues until 510 TS. If the data value is high, the counter is reset and returned to the search block unit (1).

The 510 TS is also performed as described above. If the F bit of one subframe is found because the data value becomes high in the 510 TS, the 1 subframe F bit ok signal is transmitted to the final block unit 4, as described above. Then, the F bits of the remaining six subframes are found, and the result of the F bit search of each subframe is transmitted to the final block section 4. FIG.

The final block section 4 receives the seven subframe F bit ok signals and outputs a frame search ok signal if all are ok.

As described above, when the DS3 frame pattern is found, the DS3 data signal must be checked by one bit at a time. Therefore, there is a problem that the DS3 frame pattern time specified in the standard can be exceeded.

Accordingly, an object of the present invention is to solve a conventional problem, and to provide a frame pattern within a short time when demultiplexing a payload of a DS3 signal.

1 is a block diagram of a conventional frame search circuit.

2 is a table diagram of a DS3 signal format applied to the present invention.

3 is a block diagram of a frame search circuit of the present invention.

4 is a detailed circuit diagram of a bit search unit of FIG. 2;

<Explanation of symbols for the main parts of the drawings>

1: Search block part 2: Count block part

3: check block part 4: final block part

10: input unit 20: DS3 block generation unit

21: M frame counter section 22: sub frame counter section

23: block counter 24: DS2 counter

25: bit search unit 30: first clock distribution generator

40: second clock distribution generating unit 50: shift unit

51: first shift portion 52: second shift portion

53: third shift portion 100: first block portion

200: second block portion 300: third block portion

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

An embodiment of the frame search circuit of the present invention,

An input unit 10 that receives DS (Digital Signal) 3 data and a DS3 clock and reads DS3 data into a DS3 clock;

An M (Multi) frame counter unit 21 for counting seven subframes, a subframe counter unit 22 for counting eight blocks, a block counter unit 23 for counting 85 TSs, A DS2 counter section 24 for counting seven DS2 data, and a bit search section 25 for searching the F (Frame) bit at a prescribed position for searching the DS3 frame pattern. And a DS3 block generator 20;

A first clock distribution generator (30) for dividing the DS3 clock by 85;

A second clock distribution generator 40 for dividing the DS3 clock into 170;

And a shift unit 50 for shifting the DS3 data of the first clock distribution generator to a DS3 clock.

The bit search unit 25

A first block portion for considering the first of the DS3 data as F bits;

A second block portion for considering the second of the DS3 data as F bits;

Preferably, the third block is composed of a third block that regards the third of the DS3 data as F bits.

The shift unit 50

A first shift unit (51) for shifting DS3 data into a DS3 clock and inputting it to an input terminal of the first block unit;

A second shift unit 52 for shifting DS3 data into a DS3 clock and inputting it to an input terminal of the second block unit;

The third shift unit 53 is preferably configured to shift the DS3 data to the DS3 clock and input the DS3 data to the input terminal of the third block unit.

FIG. 2 is a table diagram of a DS3 signal format applied to the present invention, FIG. 3 is a block diagram of the frame search circuit of the present invention, and FIG. 4 is a detailed circuit diagram of the bit search unit of FIG. 2. .

As shown in FIG. 1, one block is composed of 85 bits, the first bit is a control bit, and the remaining 84 bits are polyload bits composed of seven DS2s.

The 1 block is a total of 680 bits because each of the seven DS2 data is located 12, the subframe is composed of eight blocks, of which eight control bits, the F bit is located across one control bit The spacing between the F bits is 170 bits.

Since the M (Multi) frame is composed of seven subframes, the total number is 4760 bits. The input unit of FIG. 2 receives a DS3 data signal and a DS3 clock to make a type of data to be used in the F bit search unit, and a first clock distribution generator. (30) inputs the DS3 clock and makes a shift of 1SHIFT_CLK ÷ 85 with a clock ÷ 85 signal and a DS3 clock, and NOT_1SHIFT_CLK ÷ 85 with an inverted clock. Make a signal.

The second clock distribution generator 40 receives the DS3 clock to generate the CLK ÷ 170 signal and the NOT_CLK ÷ 170 signal. After extracting the value of the control bit with 85 and shifting it to (6) / (7) / (8) / (9) CLK ÷ 85, the values of the control bit are changed in units of 85TS and (6) / (7) / (8) The / (9) signals are values shifted in units of 85TS.

(10) is a signal for checking whether two F0 values are 00 in the F bit (F1-F0-F0-F1) after reading the values of (6) and (8) and reading them with CLK ÷ 170. If any one of the two F0 values is high, a high signal is sent to the DS3 block generator 20 block to clear the subframe counter.

(11) After XOR with 1SHIFT_DATA and (12) data, read into DS3_CLK to make output (13) which makes all bits related to F bits (F1-F0-F0-F1) high, and (14) generates CLK ÷ 170 signal. This is the logic that checks the F bit of each subframe as it reads twice and gets the effect of CLK ÷ 340, and (15) is a signal displayed as low when having a randomly selected value of F bit 1-0-0-1. If the signal is high, the randomly selected F bit is shifted by one clock.

(16) ends with 1SHIFT_CLK ÷ 85 and (1) data and NOR NOT_1SHIFT_CLK ÷ 85, and then clock shifts the F bit arbitrarily selected by the first block part 100 using the JK flip-flop to determine the F bit. Signal 18 has only the value of the control bit, and obtains the signals of (19) (20) and (21) which have shifted this value to 1SHIFT_CLK ÷ 85, respectively, which maintain the control bit values for one block time.

After XORing (20) and (11) and reading it with DS3_CLK, the value of the F bit determined by the second block part 200 is all low. If this value is high, a high signal is sent to the DS3 block generator 20. Clear the DS2 counter to shift the F bit to the next clock.

(24) and (25) shift the position of the F bit selected by the second block unit 200 again by 2SHIFT_CLK ÷ 85 and NOT_2SHIFT_CLK ÷ 85 by one clock, and (26) the control bit selected by the third block unit 300. Only the value of is displayed and again shifted to 2SHIFT_CLK ÷ 85 to maintain the values of the control bits by one block.

As with the second block unit 200, (27) keeps the values of the F bits (F1-F0-F0-F1) low, and if high, sends a high signal to the DS3 block generator 20 to send the DS2 counter. The part is cleared to shift the F bit to the next clock. Finally, the signal 28 NORING the signal from the first block part 100, the second block part 200, and the third block part 300. And output to the load side of the DS2 counter portion of the DS3 block generator 20.

Therefore, when searching for DS3 frame pattern when processing DS3 signal, first find the F bit (F1-F0-F0-F1) belonging to the control bit, and select the bits of F bits arbitrarily selected in finding the F bit as three consecutive bits. The F bit can be found within three times faster than the conventional 1 bit, so that DS3 signal processing can be performed quickly.

As described above, according to the present invention, DS3 signal processing can be performed quickly and efficiently by efficiently finding the position of the F bit in a faster time in finding the DS3 frame pattern to demultiplex the payload of the DS3 signal.

Claims (3)

An input unit for receiving DS (Digital Signal) 3 data and a DS 3 clock and reading DS 3 data with a DS 3 clock; M (Multi) frame counter for counting 7 subframes, subframe counter for counting 8 blocks, block counter for counting 85 TS (time slots), DS2 counter for counting 7 DS2 data And a bit search unit for searching for F (Frame) bits at a predetermined position to search for a DS3 frame pattern, the DS3 block generating unit having a size of one frame; A first clock distribution generator which divides the DS3 clock into 85; A second clock distribution generator which divides the DS3 clock into 170; And a shift unit for shifting the DS3 data of the first clock distribution generator to a DS3 clock. The bit search unit of claim 1, wherein the bit search unit A first block portion for considering the first of the DS3 data as F bits; A second block portion for considering the second of the DS3 data as F bits; And a third block portion that considers the third of the DS3 data to be F bits. The shift unit according to claim 1 or 2, wherein the shift unit A first shift unit for shifting DS3 data into a DS3 clock and inputting it to an input terminal of the first block unit; A second shift unit for shifting DS3 data into a DS3 clock and inputting it to an input terminal of the second block unit; And a third shift section for shifting DS3 data into a DS3 clock and inputting it to an input terminal of the third block section.