KR20020033849A - Method of manufacturing gateelectrode in semiconductor device - Google Patents
Method of manufacturing gateelectrode in semiconductor device Download PDFInfo
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- KR20020033849A KR20020033849A KR1020000063998A KR20000063998A KR20020033849A KR 20020033849 A KR20020033849 A KR 20020033849A KR 1020000063998 A KR1020000063998 A KR 1020000063998A KR 20000063998 A KR20000063998 A KR 20000063998A KR 20020033849 A KR20020033849 A KR 20020033849A
- Authority
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- South Korea
- Prior art keywords
- gate electrode
- composite
- doped polysilicon
- metal silicide
- film
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 46
- 239000002131 composite material Substances 0.000 claims abstract description 44
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 39
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 31
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 229920005591 polysilicon Polymers 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 22
- 229910017052 cobalt Inorganic materials 0.000 claims description 15
- 239000010941 cobalt Substances 0.000 claims description 15
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 15
- 239000007789 gas Substances 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 239000012299 nitrogen atmosphere Substances 0.000 claims 1
- 239000011800 void material Substances 0.000 abstract 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 229910008484 TiSi Inorganic materials 0.000 description 4
- 238000007669 thermal treatment Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- -1 Silicon ions Chemical class 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
- H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 실리사이드막을 이용하는 게이트전극의 산화 저항성(Oxidation resistance) 및 열적안정성(Thermalstability)을 개선시키도록 한 게이트전극의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a gate electrode to improve oxidation resistance and thermal stability of a gate electrode using a silicide film.
최근에 소자의 디자인룰이 감소함에 따라 텅스텐실리사이드(WSix)를 이용한 게이트전극 대신에 낮은 저항을 갖는 티타늄실리사이드(TiSi2), 코발트실리사이드 (CoSi2), 텅스텐(W)을 이용한 게이트전극을 이용하고 있다.Recently, as the design rule of the device is reduced, instead of the gate electrode using tungsten silicide (WSi x ), a gate electrode using titanium silicide (TiSi 2 ), cobalt silicide (CoSi 2 ), and tungsten (W) having low resistance is used. Doing.
특히, 텅스텐 게이트전극은 5.5μΩ·cm의 비저항으로 세가지 게이트물질 중 가장 낮은 저항을 보이지만 산화에 대한 위험성이 높아 공정의 집적도에는 많은 제약이 따르고, 18μΩ·cm의 비저항을 갖는 티타늄실리사이드 및 코발트실리사이드는 통상의 공정기술을 계속 사용할 수 있는 장점이 있지만 열공정에 따라 많은 단점을 보이고 있다.In particular, the tungsten gate electrode exhibits the lowest resistance among the three gate materials with a resistivity of 5.5 μΩ · cm, but it has a high risk of oxidation, which places a lot of restrictions on the integration of the process, and titanium silicide and cobalt silicide having a resistivity of 18 μΩ · cm There is an advantage that can continue to use the usual process technology, but shows a number of disadvantages according to the thermal process.
즉, 티타늄실리사이드는 좁은 라인(Narrow line)에서 막내에서 응집현상 (Agglomeration)이 발생됨은 물론 반응(Reactive)에 약한 열안정성(Thermal stability)이 저하되는 문제점이 있고, 코발트실리사이드는 코발트의 높은 확산 특성에 의한 트랜지스터의 특성 변화 가능성이 있다.That is, titanium silicide has a problem in that agglomeration occurs in a film in a narrow line, and thermal stability, which is weak in reaction, is lowered. Cobalt silicide has a high diffusion property of cobalt. There is a possibility of changing the characteristics of the transistor by
이러한 문제점을 해결하기 티타늄실리사이드와 도우프드 폴리실리콘의 계면(Interface)이 균일하게 유지되는 복합 티타늄실리사이드(Composite TiSi2)를 이용한다.In order to solve this problem, a composite titanium silicide (Composite TiSi 2 ) having a uniform interface between titanium silicide and doped polysilicon is used.
도 1은 종래기술에 따른 반도체소자의 게이트전극의 형성 방법을 간략히 나타낸 도면으로서, 반도체기판(11)상에 게이트산화막(12)을 형성한 후, 상기 게이트산화막(12)상에 도우프드 폴리실리콘(Doped polysilicon)(13)을 형성한 후, 상기도우프드 폴리실리콘(13)상에 복합 티타늄실리사이드(TiSix, x 〉2 )(14)을 증착한다. 이 때, 상기 복합 티타늄실리사이드(14) 증착시, 티타늄실리사이드 복합 타겟을 아르곤 스퍼터링(Ar sputtering)에 의해 증착한다.FIG. 1 is a view schematically illustrating a method of forming a gate electrode of a semiconductor device according to the related art. After forming a gate oxide film 12 on a semiconductor substrate 11, doped polysilicon is formed on the gate oxide film 12. After the doped polysilicon 13 is formed, a composite titanium silicide (TiSi x , x> 2) 14 is deposited on the doped polysilicon 13. At this time, when the composite titanium silicide 14 is deposited, the titanium silicide composite target is deposited by ar sputtering.
이어서, 상기 복합 티타늄실리사이드(14)의 결정화를 위한 급속열처리(RTP)를 실시한 후, 상기 복합 티타늄실리사이드(14) 및 도우프드 폴리실리콘(13)를 선택적으로 식각하여 게이트전극을 형성한다.Subsequently, after the rapid thermal treatment (RTP) for crystallization of the composite titanium silicide 14, the composite titanium silicide 14 and the doped polysilicon 13 are selectively etched to form a gate electrode.
그러나, 상술한 종래기술에서는 복합 티타늄실리사이드(14) 증착후 결정화를 위한 급속열처리후 복합 티타늄실리사이드(14)내에 보이드(Void)가 발생되는데, 상기 보이드는 복합 타겟을 스퍼터링한 후 티타늄실리사이드의 결정화를 위한 급속열처리동안에 티타늄(Ti)이 하부막인 도우프드 폴리실리콘(13)과 반응하여 발생하거나, 또는 복합 티타늄실리사이드(14) 자체의 밀도가 낮기 때문에 발생된다.However, in the above-described prior art, voids are generated in the composite titanium silicide 14 after rapid thermal treatment for crystallization after deposition of the composite titanium silicide 14, and the voids sputter the composite target and then crystallize the titanium silicide. Titanium (Ti) reacts with the doped polysilicon 13, which is a lower layer, during the rapid heat treatment, or because the composite titanium silicide 14 itself is low in density.
이러한 보이드로 인해 후속 게이트전극 식각 공정시, 반도체기판(11)에 핀홀(Pin hole)을 발생시키거나 열안정성을 크게 감소시켜 소자의 신뢰성을 저하시키는 문제점이 발생된다.Due to such voids, in the subsequent gate electrode etching process, pinholes are generated in the semiconductor substrate 11 or thermal stability is greatly reduced, thereby lowering the reliability of the device.
또한, 티타늄원자가 도우프드 폴리실리콘을 통과하여 게이트산화막까지 확산하므로써 게이트산화막, 예컨대 SiO2의 결함을 끊어 GOI(Gate Oxide Integrity)특성을 저하시키는 문제점이 있다.In addition, since titanium atoms diffuse through the doped polysilicon to the gate oxide layer, defects of the gate oxide layer, such as SiO 2 , are eliminated, thereby degrading GOI (Gate Oxide Integrity) characteristics.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 금속실리사이드를 이용한 게이트전극 형성시 보이드로 인한 핀홀 발생 또는 열안정성 저하를 방지하는데 적합한 게이트전극의 제조 방법을 제공하는데 목적이 있다.The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide a method of manufacturing a gate electrode suitable for preventing pinhole generation or thermal stability deterioration due to voids when forming a gate electrode using a metal silicide.
도 1은 종래기술에 따라 제조된 게이트전극을 도시한 도면,1 is a view showing a gate electrode manufactured according to the prior art,
도 2a 내지 도 2b는 본 발명의 실시예에 따른 게이트전극의 제조 방법을 도시한 도면.2A to 2B illustrate a method of manufacturing a gate electrode according to an exemplary embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 게이트산화막21 semiconductor substrate 22 gate oxide film
23 : 도우프드 폴리실리콘 24 : 복합 티타늄실리사이드막23: doped polysilicon 24: composite titanium silicide film
25 : 실리콘부화-티타늄실리사이드막25 silicon hatching-titanium silicide film
상기의 목적을 달성하기 위한 본 발명의 게이트전극 제조 방법은 반도체기판상에 게이트산화막을 형성하는 단계; 상기 게이트산화막상에 도우프드 폴리실리콘을 형성하는 단계; 상기 도우프드 폴리실리콘상에 복합 금속실리사이드막을 형성하는 단계; 상기 복합 금속실리사이드막에 실리콘원자를 이온주입시키는 단계; 급속열처리를 실시하여 상기 실리콘원자가 이온주입된 복합 금속실리사이드막을 결정화시키는 단계; 및 상기 결정화된 복합 티타늄실리사이드막 및 상기 도우프드 폴리실리콘을 선택적으로 패터닝하여 게이트전극을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The gate electrode manufacturing method of the present invention for achieving the above object comprises the steps of forming a gate oxide film on a semiconductor substrate; Forming doped polysilicon on the gate oxide film; Forming a composite metal silicide layer on the doped polysilicon; Ion implanting silicon atoms into the composite metal silicide layer; Performing a rapid heat treatment to crystallize the composite metal silicide film into which the silicon atoms are ion-implanted; And selectively patterning the crystallized composite titanium silicide layer and the doped polysilicon to form a gate electrode.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2b는 본 발명의 실시예에 따른 게이트전극의 형성 방법을 도시한 도면이다.2A to 2B illustrate a method of forming a gate electrode according to an exemplary embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체기판(21)상에 게이트산화막(22)을 형성하고, 상기 게이트산화막(22)상에 도우프드 폴리실리콘(23)을 형성한 후, 도우프드폴리실리콘(23)의 표면을 습식케미컬(Wet chemical)로 처리한다. 계속해서, 상기 도우프드 폴리실리콘(23)상에 조성비 2.0(x=2.0)을 가지는 복합 티타늄실리사이드막(TiSi2)(24)을 형성한다.As shown in FIG. 2A, after the gate oxide film 22 is formed on the semiconductor substrate 21 and the doped polysilicon 23 is formed on the gate oxide film 22, the doped polysilicon 23 is formed. ) Surface is treated with wet chemical. Subsequently, a composite titanium silicide film (TiSi 2 ) 24 having a composition ratio of 2.0 (x = 2.0) is formed on the doped polysilicon 23.
이 때, 상기 도우프드 폴리실리콘(23) 형성시, 500℃∼700℃의 온도와 0.1Torr∼10Torr의 압력에서 SiH4또는 SiH2Cl2중 어느 하나와 PH3가스를 이용한다.At this time, when the doped polysilicon 23 is formed, any one of SiH 4 or SiH 2 Cl 2 and a PH 3 gas are used at a temperature of 500 ° C. to 700 ° C. and a pressure of 0.1 Torr to 10 Torr.
그리고, 상기 복합 티타늄실리사이드막(24) 형성시, 티타늄실리사이드 복합 타겟을 아르곤으로 스퍼터링하여 진행하되, 0Torr∼10Torr의 압력과 0℃∼400℃의 온도에서 이루어진다.When the composite titanium silicide film 24 is formed, the titanium silicide composite target is sputtered with argon to proceed, and is made at a pressure of 0 Torr to 10 Torr and a temperature of 0 ° C. to 400 ° C.
이어서, 상기 복합 티타늄실리사이드막(24)에 실리콘 소스를 포함하는 SiH4, SiF4, SiH2Cl2의 가스를 이용하여 실리콘원자(Si)를 강제로 주입시킨다.Subsequently, silicon atom (Si) is forcibly injected into the composite titanium silicide layer 24 using gases of SiH 4 , SiF 4 , and SiH 2 Cl 2 including a silicon source.
한편, 복합 타겟에서 원자의 크기가 작은 실리콘원자를 증가시키면 막의 밀도는 증가시킬 수 있지만, 타겟자체의 실리콘원자의 함량을 증가시킴에 따라 스퍼터링동안에 실리콘이 파티클형태로 복합 티타늄실리사이드막(24)내에 함유되게 되어 후속 게이트 식각 공정을 어렵게 하므로 실리콘 이온(Si)을 강제로 이온주입시킨다.On the other hand, increasing the atomic size of silicon atoms in the composite target increases the density of the film, but increases the content of the silicon atoms in the target itself, thereby increasing the content of silicon atoms in the composite titanium silicide film 24 in the form of particles during sputtering. Silicon ions (Si) are forcibly implanted since they become difficult to carry out subsequent gate etching processes.
상기와 같은 실리콘원자의 이온주입시, 후속 열처리 공정 및 산화공정에 소모될 실리콘양을 고려하여 이온 주입 공정을 진행하며, 실리콘원자의 도즈량(Dose)을 증가시켜 막내의 실리콘 함량을 증가시킬 수 있다.When ion implantation of silicon atoms as described above, the ion implantation process is carried out in consideration of the amount of silicon to be consumed in the subsequent heat treatment and oxidation process, and the silicon content in the film can be increased by increasing the dose of silicon atoms. have.
도 2b에 도시된 바와 같이, 600℃∼900℃의 온도와 0.1Torr∼760Torr의 압력의 질소(N2) 분위기에서 급속열처리(RTP)를 실시하여 상기 실리콘원자가 이온주입된 티타늄실리사이드막, 예컨대 실리콘부화-티타늄실리사이드막(25)을 결정화시킨다. 여기서, 복합 티타늄실리사이드막(24)과 실리콘부화-티타늄실리사이드막(25)의 특성이 다르므로 서로 다른 부호를 부여한다.As shown in FIG. 2B, a rapid thermal treatment (RTP) is carried out in a nitrogen (N 2 ) atmosphere at a temperature of 600 ° C. to 900 ° C. and a pressure of 0.1 Torr to 760 Torr, such as a silicon silicide film in which a silicon atom is ion-implanted, such as silicon. The hatching-titanium silicide film 25 is crystallized. Here, since the characteristics of the composite titanium silicide film 24 and the silicon-enriched titanium silicide film 25 are different, they are assigned different codes.
즉, 스퍼터링 과정에서 발생된 티타늄원자를 이온주입된 실리콘원자(Si)와 반응시키거나 실리콘부화-티타늄실리사이드막(24) 자체의 밀도를 증가시킨다.That is, the titanium atoms generated in the sputtering process are reacted with the silicon atoms (Si) implanted with ions or the density of the silicon-enriched titanium silicide layer 24 itself is increased.
도 2b에 도시된 바와 같이, 상기 결정화된 실리콘부화-티타늄실리사이드막 (25)상에 하드마스크(도시 생략)를 형성한 후, 먼저 하드마스크를 선택적으로 식각하고 계쏙해서 하드마스크를 이용하여 하부의 실리콘부화-티타늄실리사이드막(25), 도우프드 폴리실리콘(23)을 식각하여 게이트전극을 형성한다.As shown in FIG. 2B, after forming a hard mask (not shown) on the crystallized silicon-enriched titanium silicide layer 25, first, the hard mask is selectively etched and arranged to obtain a lower portion of the lower portion using a hard mask. A silicon electrode-titanium silicide layer 25 and doped polysilicon 23 are etched to form a gate electrode.
상술한 실시예에서는 티타늄실리사이드를 예로 설명하였으나, 복합 코발트실리사이드막을 이용하는 경우도 동일한 방법을 적용하므로, 도면은 생략한다.In the above-described embodiment, titanium silicide has been described as an example, but the same method applies to the case of using the composite cobalt silicide film, and thus the drawings are omitted.
자세히 설명하면, 반도체기판상에 게이트산화막을 형성하고, 상기 게이트산화막상에 도우프드 폴리실리콘을 형성한 후, 도우프드 폴리실리콘의 표면을 습식케미컬로 처리한다. 계속해서, 상기 도우프드 폴리실리콘상에 복합 코발트실리사이드막을 형성한다. 이 때, 상기 도우프드 폴리실리콘(23) 형성시, 500℃∼700℃의 온도와 0.1Torr∼10Torr의 압력에서 SiH4또는 SiH2Cl2중 어느 하나와 PH3가스를 이용한다. 그리고, 상기 복합 코발트실리사이드막 형성시, 코발트실리사이드 복합 타겟을 아르곤으로 스퍼터링하여 진행하되, 0Torr∼10Torr의 압력과 0℃∼400℃의 온도에서 이루어진다.In detail, a gate oxide film is formed on a semiconductor substrate, and a doped polysilicon is formed on the gate oxide film, and then the surface of the doped polysilicon is treated with a wet chemical. Subsequently, a composite cobalt silicide film is formed on the doped polysilicon. At this time, when the doped polysilicon 23 is formed, any one of SiH 4 or SiH 2 Cl 2 and a PH 3 gas are used at a temperature of 500 ° C. to 700 ° C. and a pressure of 0.1 Torr to 10 Torr. In the formation of the composite cobalt silicide film, the cobalt silicide composite target is sputtered with argon to proceed, and is made at a pressure of 0 Torr to 10 Torr and a temperature of 0 ° C. to 400 ° C.
이어서, 상기 복합 코발트실리사이드막에 실리콘 소스를 포함하는 SiH4, SiF4, SiH2Cl2의 가스를 이용하여 실리콘원자(Si)를 강제로 주입시킨다. 한편, 복합 타겟에서 원자의 크기가 작은 실리콘원자를 증가시키면 막의 밀도는 증가시킬 수 있지만, 타겟자체의 실리콘원자의 함량을 증가시킴에 따라 스퍼터링동안에 실리콘이 파티클형태로 복합 코발트실리사이드막내에 함유되게 되어 후속 게이트 식각 공정을 어렵게 하므로 실리콘 이온(Si)을 강제로 이온주입시킨다.Subsequently, silicon atom (Si) is forcibly injected into the composite cobalt silicide layer using gas of SiH 4 , SiF 4 , SiH 2 Cl 2 including a silicon source. On the other hand, increasing the atomic size of silicon atoms in the composite target can increase the density of the film, but as the content of silicon atoms in the target itself increases, the silicon is contained in the composite cobalt silicide film in the form of particles during sputtering. Since the subsequent gate etching process is difficult, silicon ions (Si) are forcibly implanted.
상기와 같은 실리콘원자의 이온주입시, 후속 열처리 공정 및 산화공정에 소모될 실리콘양을 고려하여 이온 주입 공정을 진행하며, 실리콘원자의 도즈량(Dose)을 증가시켜 막내의 실리콘 함량을 증가시킬 수 있다.When ion implantation of silicon atoms as described above, the ion implantation process is carried out in consideration of the amount of silicon to be consumed in the subsequent heat treatment and oxidation process, and the silicon content in the film can be increased by increasing the dose of silicon atoms. have.
계속해서, 600℃∼900℃의 온도와 0.1Torr∼760Torr의 압력의 질소(N2) 분위기에서 급속열처리(RTP)를 실시하여 상기 실리콘원자가 이온주입된 코발트실리사이드막, 예컨대 실리콘부화-코발트실리사이드막을 결정화시킨다. 즉, 스퍼터링 과정에서 발생된 티타늄원자를 이온주입된 실리콘원자(Si)와 반응시키거나 실리콘부화-코발트실리사이드막 자체의 밀도를 증가시킨다.Subsequently, rapid thermal treatment (RTP) is carried out in a nitrogen (N 2 ) atmosphere at a temperature of 600 ° C. to 900 ° C. and a pressure of 0.1 Torr to 760 Torr to form a cobalt silicide film in which the silicon atoms are ion-implanted, such as a silicon-enriched cobalt silicide film. Crystallize. That is, the titanium atom generated in the sputtering process is reacted with the ion implanted silicon atom (Si) or the density of the silicon-enriched cobalt silicide layer itself is increased.
이어서, 결정화된 실리콘부화-코발트실리사이드막, 도우프드 폴리실리콘을 식각하여 게이트전극을 형성한다.Subsequently, the crystallized silicon-enriched cobalt silicide film and the doped polysilicon are etched to form a gate electrode.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 게이트전극의 제조 방법은 복합 티타늄실리사이드에 실리콘 원자를 강제로 이온주입시키므로써 티타늄실리사이드막의 밀도를 증가시켜 보이드의 발생을 억제시킬 수 있다.In the method of manufacturing the gate electrode of the present invention as described above, by forcibly ion implanting silicon atoms into the composite titanium silicide, the density of the titanium silicide film can be increased to suppress the generation of voids.
또한, 이온주입된 실리콘 원자에 의해 티타늄실리사이드막의 산화저항성을 증가시키고, 티타늄실리사이드막의 그레인경계면(Grain boundary)에 실리콘이 석출되어 후속 열공정에서 그레인경계면의 이동을 방해하므로써 티타늄실리사이드막의 열안정성을 향상시킬 수 있는 효과가 있다.In addition, the ion-implanted silicon atoms increase the oxidation resistance of the titanium silicide film, and silicon precipitates at the grain boundary of the titanium silicide film, thereby impeding the movement of the grain boundary in subsequent thermal processes, thereby improving the thermal stability of the titanium silicide film. It can be effected.
그리고, 실리콘원자의 이온주입에 의해 막내의 실리콘 함량을 증가시키므로써 스퍼터링에 의한 티타늄원자의 게이트산화막으로의 확산을 방지하여 소자의 GOI특성을 개선시킬 수 있는 효과가 있다.In addition, by increasing the silicon content in the film by ion implantation of silicon atoms, it is possible to prevent the diffusion of titanium atoms into the gate oxide film by sputtering to improve the GOI characteristics of the device.
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