KR20020033288A - Correlation apparatus and method for code acquisition in cdma system - Google Patents

Abstract

PURPOSE: A correlation apparatus and method for code acquisition in a CDMA(Code Division Multiple Access) communication system is provided to effectively perform the code acquisition by decreasing a hardware size, removing an initialization operation of a scrambling code generator, maintaining a same phase, and randomly selecting a correlation interval. CONSTITUTION: A code generator(92) masks an x sequence by a provided mask value and generates a scrambling code. A correlator(91) correlates a receiving signal and the generated scrambling code. The code generator(92) comprises a generator for generating a primary scrambling code of a code group obtained through a synchronization channel, a memory for storing mask values for masking the x sequence of a primary scrambling code, and a masking unit for operating the primary scrambling code from the generator and the mask value from the memory and generating scrambling codes of the code group.

Description

Correlation Apparatus and Method for Code Acquisition in Code Division Multiple Access Communication System {CORRELATION APPARATUS AND METHOD FOR CODE ACQUISITION IN CDMA SYSTEM}

TECHNICAL FIELD The present invention relates to a code division multiple access (CDMA) communication system, and more particularly, to an initial code acquisition apparatus and method.

Hereinafter, a UMTS / 3GPP (Universal Mobile Telecommunication System / 3rd Generation Partnership Project) will be described as an example.

The UMTS allocates different downlink scrambling codes for each base station. The forward link scrambling code includes a first scrambling code and a second scrambling code, and a code scrambling code is a first scrambling code. Hereinafter, the first scrambling code will be referred to as a scrambling code. The scrambling code uses 512, which is divided into 64 groups and 8 groups are assigned to each group.

Meanwhile, the base station transmits a synchronization channel (SCH) spread as a synchronization code separately from the scrambling code. The SCH has a first synchronous channel (Primary-SCH) and a second synchronous channel (Secondary-SCH), the P-SCH provides slot synchronization, the S-SCH is frame synchronization (code phase synchronization) and code Provide group information. Upon obtaining the above information from the SCH, the mobile station identifies the final scrambling code using a common pilot channel (CPICH).

That is, as described above, the scrambling code group and the frame synchronization may be obtained through the first synchronization channel and the second synchronization channel. Since the frame period is the same as the scrambling period, code phase information is also acquired when frame synchronization is performed. However, in this case, since the mobile station does not know which of the eight scrambling codes belonging to the code group is the scrambling code of its base station, the code synchronization is not completed. Which of the 8 scrambling codes belonging to the code group is the base station code can be identified by correlating to the common pilot channel. That is, the correlation is performed on the eight possible scrambling codes in the group, and then the scrambling code having the largest correlation energy is selected.

Here, the hypothesis checking for the eight scrambling codes includes a parallel search method that performs correlation on eight scrambling codes simultaneously, a serial search method that performs correlation on eight scrambling codes sequentially, and the parallel search. This is done by using a combination of a method and a serial search method.

Here, the parallel search method has the fastest search speed but a large burden on hardware complexity. Therefore, serial search method is preferred. When the serial search method is correlated for one scrambling code and then correlated for the next scrambling code, it must be correlated with the same code phase as previously correlated. Here, the same code phase means that the starting point of the scrambling code period is the same. Meanwhile, the offset refers to a state after the scrambling code is generated by a predetermined chip, and the zero offset refers to an initial condition. In general, the scrambling code is generated by loading an initial condition into the scrambling code generator, and it is common to remember the initial condition of the scrambling code for high speed initialization.

On the other hand, since the scrambling code generated after loading the initial condition always starts at the frame boundary, after the correlation of one scrambling code has been completed in the serial search method, it must wait until the next frame boundary to correlate the next scrambling code. Since the initial condition of the scrambling code can be loaded and the code can be generated and correlated, the search time is increased. In order to solve this problem in the serial search method, it is necessary to start correlation of the scrambling code at an arbitrary time point rather than a frame boundary, and the following method can be considered as a conventional technology for this.

FIG. 3 shows a correlation device (or search device) storing an initial condition and an offset condition for all scrambling codes according to the prior art. Meanwhile, the correlator shown in FIG. 3 uses a serial search method. Here, the offset condition means the state of the shift register of the scrambling code generator when the initial condition of a specific scrambling code is input to the scrambling code generator and generated for a specific number of times.

Referring to FIG. 3, the scrambling generator 32 generates and outputs a scrambling code corresponding to a given offset condition. The code generator 32 has a configuration as shown in FIG. 2, and sets a offset condition of a scrambling code to be generated in the shift register to generate a code sequence having different offsets of the corresponding code. The correlator 31 correlates the received signal with the scrambling code output from the code generator 32 and outputs the correlation.

The operation of the correlator of FIG. 3 will now be described with reference to FIG. 4. Here, assume that correlation for the first scrambling code starts at the frame boundary. First, the correlator 31 correlates a received signal during the A chip at a frame boundary with a first scrambling code generated from the code generator 32. Thereafter, an offset condition having an offset as much as A chips is loaded into the code generator 32 at the frame boundary of the second scrambling code, and the code generator 32 generates a code sequence (second scrambling code) corresponding to the offset. Then, the correlator 31 correlates the received signal and the second scrambling code outputted from the code generator 32 from the time point A for the given chip period as in the first correlation. In this way, iterate up to the eighth scrambling code. In order to correlate an eighth scrambling code, an offset condition having an offset of B chips is loaded into the code generator 32 at the frame boundary of the eighth scrambling code, and the code generator 32 generates a code sequence corresponding to the offset (the eighth scrambling code). ). The correlator 31 correlates the received signal from the time point B and the eighth scrambling code output from the code generator 32 for a given chip interval as in the case of correlation with other codes.

In such a scheme, there is a burden of storing the initial conditions and the conditions for possible offsets for all the scrambling codes. In addition, the correlation section for each scrambling code is limited to only a section corresponding to a given offset. As another method of the serial search method, a masking method may be used for the scrambling code. Referring to FIG. 5, the code generator 52 generates a scrambling code according to a given initial condition. At this time, the scrambling code is generated and output with a mask value corresponding to a given offset. The correlator 51 correlates and outputs the received signal with the code output from the selector 52. The code generator 52 is shown in more detail in FIG.

The operation of the serial search apparatus of FIG. 5 will be described with reference to FIG. 6. It is assumed here that the correlation for the first scrambling code starts at the frame boundary. First, the code generator 52 is initialized by the initial condition of the first scrambling code. The correlator 51 correlates the received signal with the scrambling code output from the code generator 52 during the A chip period. Thereafter, the code generator 52 is re-initialized according to the initial condition of the second scrambling code, and generates and outputs a second scrambling code by masking a mask value corresponding to an A chip offset for the X sequence and the Y sequence, respectively. Then, the correlator 51 correlates the received signal and the second scrambling code outputted from the code generator 52 from the time point A for the given chip period as in the first correlation. In this way, iterate up to the eighth scrambling code. In order to correlate the eighth scrambling code, the initial condition of the eighth scrambling code is loaded into the code generator 52, and the scrambling code is generated by masking with a mask value corresponding to the B chip offset. The correlator 51 correlates the received signal from the time point B and the eighth scrambling code output from the code generator 52 for a given chip interval as in the case of correlation with other codes.

As described above, in the method of using masking to load the initial condition and change the code phase, since the offset conditions for all the scrambling codes do not need to be stored as shown in FIG. 3, the amount of memory is considerably reduced, but the mask value stored in the correlation section There is a burden of having to match the offset period corresponding to and still remembering the initial condition and mask value of all scrambling codes.

In addition to the above methods, there is also a method using a plurality of scrambling code generators as shown in FIG. Referring to FIGS. 7 and 8, the code generators 73 are initialized by given initial conditions (initial condition 1-initial condition 8) respectively at the frame boundary. Here, the selector 72 selects and outputs one of the code generators by the selection signal. First, the output of the first code generator that generates the first scrambling code is selected and provided to the correlator 71. The correlator 71 then correlates the received signal with the first scrambling code during the A chip period from the frame boundary. The selector 71 then selects the output of the second code generator that generates the second scrambling code and provides it to the correlator 71. Then, the correlator 71 correlates the received signal and the second scrambling code outputted from the selector 71 from the time point A for the given chip period as in the first correlation. In this way, iterate up to the eighth scrambling code. This method can maintain the same phase regardless of the initial condition because the plurality of code generators all operate the same. This method can solve the problem that the memory size problem and the correlation interval are limited to the offset period stored as shown in FIGS. 3 and 5, but the eight scrambling code generators have to be driven at the same time. There is a burden to remember the initial condition.

That is, as described above, the conventional correlator (or search apparatus) requires an initialization operation to check for one scrambling code and then check for the next scrambling code, and the initial condition and correlation section of all scrambling codes are required. The corresponding offset condition (or mask value) must be stored, and there is a problem in that the correlation section is also limited thereto. On the other hand, the structure as shown in Figure 7 can solve the problem of the memory capacity and the correlation interval required for the storage of the offset condition (or mask value), but there is a hardware burden to run the eight code generators at the same time.

Accordingly, an object of the present invention is to provide a correlation device and a method that can solve the problem of reducing the hardware burden of the serial search method and the correlation interval is limited.

Another object of the present invention is to provide a correlation apparatus and method for code synchronization in a code division multiple access communication system.

It is another object of the present invention to provide a correlator and method for generating a scrambling code by masking an x sequence for base station code acquisition.

It is still another object of the present invention to provide a correlation apparatus and method for converting a scrambling code and generating a code by controlling an x sequence of two m sequences at a faster or lower speed than a chip clock for base station code acquisition.

According to a first aspect of the present invention for achieving the above objects, there is a correlator for base station code acquisition in a code division multiple access communication system, the scrambling code is composed of x sequence and y sequence, and the x sequence is a mask And a scrambling code generator for generating a scrambling code by masking by a value, and a correlator for correlating the received signal with the generated scrambling code.

According to a second aspect of the present invention, in a code division multiple access communication system, a correlator for base station code acquisition includes an x sequence generator and a y sequence generator, and includes a code group obtained through a synchronization channel under the control of a through controller. And a generator for generating scrambling codes, the slew controller for controlling the two sequence generators to operate at different speeds, and a correlator for correlating the received signal with the scrambling code from the generator. .

1 is a diagram illustrating a transmission structure of an SCH and a CPICH in a universal mobile telecommunication system (UMTS).

2 is a diagram illustrating a configuration of an apparatus for generating a forward link scrambling code in UMTS.

3 illustrates a correlator storing offset values of all scrambling codes according to the prior art.

4 is a view for explaining the code correlation operation of the correlation device of FIG.

5 illustrates a correlator using a masking technique according to the prior art.

6 is a view for explaining the code correlation operation of the correlation device of FIG.

7 illustrates a correlator using a plurality of scrambling code generators according to the prior art.

8 is a view for explaining the code correlation operation of the correlation device of FIG.

9 illustrates a correlator storing a phase offset for an xsequence according to one embodiment of the invention.

10 is a view for explaining the code correlation operation of the correlation device of FIG.

11 illustrates a correlator for code acquisition according to another embodiment of the present invention.

12 is a view for explaining the code correlation operation of the correlator of FIG.

FIG. 13 illustrates a scrambling code generator of the correlator of FIG. 5. FIG.

14 illustrates a scrambling code generator of the correlator of FIG.

Fig. 15 is a diagram showing an embodiment of a method of changing a scrambling code by x sequence high speed control.

Fig. 16 is a diagram showing an embodiment of a method of changing a scrambling code by x sequence low speed control.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, if it is determined that the detailed description of the related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

FIG. 1 illustrates a transmission structure of a primary synchronization channel, a secondary synchronization channel, and a common pilot channel described above.

Referring to FIG. 1, CP1, which is a first synchronization code (PSC), is transmitted from the base station by 1/10 cycles, i.e., 256 chips of each slot, for each slot constituting the first synchronization channel. Receiving the first synchronization channel and synchronizing a base station slot time with a first synchronization code CP. (Cell search step 1)

Code group information of a base station is mapped and transmitted to a second synchronization channel (CSi, 1 to CSi, 16), and the mobile station synchronized with the time slot in the cell search step 1 transmits the code group information and the frame through the second synchronization channel. Detect synchronization. Here, the base station code group information is information for determining a code group to which the base station belongs. The base station code group information is designated according to a comma free code in which 15 synchronization codes of 16 synchronization codes SSC1 to SSC16 are selected and combined. (Cell navigation step 2)

The P-SCH is a modulation symbol spread with a primary synchronization code (PSC) of 256 lengths. The first synchronization code is used separately from the forward link scrambling code and is used the same in all base stations. Accordingly, the first synchronization channel provides slot synchronization information using this characteristic. The second synchronous channel is a symbol sequence having a length of 15, and each symbol is spread with a 256 second synchronous code (SSC), and 16 second synchronous codes are used. The second synchronization channel depends on 64 comma precodes, each of which refers to a code group including 8 scrambling codes. In addition, since the period of the second synchronization channel coincides with the frame period, the frame synchronization information is provided. The common pilot channel consists of 300 bits per frame and is spread with a predetermined channelization code (spreading factor = 256). The common pilot channel is spread with the forward link scrambling code.

The forward link scrambling code may generate a total of 262,143 (218-1) scrambling codes numbered from 0 to 262,142. However, not all scrambling code is used. The scrambling code is divided into 512 sets, each set consisting of one first scrambling code and 15 second scrambling codes. Among them, the first scrambling code, which is related to code acquisition, is configured as follows.

First scrambling code (n) = 16 * i where i = 0..511

The first scrambling code set is divided into 64 code groups. Each group consists of eight first scrambling codes. The k-th scrambling code number of the j-th code group is expressed as "16 * 8 * j + 16 * k". Where j = 0..63 and k = 0..7. Each cell is assigned one first scrambling code.

The scrambling code sequence combines two real sequences into one complex sequence. The two real sequences are made up of a modulo 2 sum of 38400 chip segments for two m-sequences. The two m-sequences are generated by polynomials of a degree 18 generator. The scrambling code sequence thus produced is a gold sequence. The scrambling code is repeated in 10 ms radio frame units.

Here, the two m sequences are called x sequence and y sequence, respectively. The x sequence is made by primitive polynomial 1 + X7 + X18 and the y sequence is generated by 1 + X5 + X7 + X10 + X18.

Initial conditions are as follows.

X (0) = 1, X (1) = X (2) = ... + X (16) = X (17) = 0

Y (0) = Y (1) = ... = Y (16) = Y (17) = 1,

The recursive definition is

X (i + 18) = (i + 17) + X (i) modulo 2, i = 0, ..., 2 ¹⁸ -20

Y (i + 18) = y (i + 10) + y (i + 7) + y (i + 5) + y (i) modulo 2, i = 0, ..., 2 ¹⁸ -20,

The n th gold code sequence zn (n = 0,1,2, ..., 218-2) is represented by Equation 1 below.

The binary sequence obtained as described above is converted into a sequence Zn of a real value through a transform as shown in Equation 2 below.

Finally, the n-th complex scrambling code sequence Sdl, n is expressed by Equation 3 below.

In Equation 3, it can be seen that the pattern of phase 38399 is repeated at phase zero. 2 shows a scrambling code generator for generating a scrambling sequence as described above. As shown, the scrambling code generator is composed of two m-sequence generators, that is, the x-sequence generator and the y-sequence generator, and the scrambling code (n) uses a generation formula such as Equation 1 above.

Meanwhile, the y sequence of the scrambling code n has the same initialization condition as the other codes, and the x sequence has an offset of n. As described above, the k-th scrambling code number of the j-th code group is "16 * 8 * j + 16 * k". Therefore, two adjacent scrambling code numbers belonging to the same group have a difference of 16. That is, considering the initialization conditions of the scrambling codes, it can be seen that the initial condition of the y sequence is the same and only the initial condition of the x sequence has an offset of 16.

The present invention is to use the above and the initial conditions of the scrambling code. First, one method proposed by the present invention is to introduce a masking technique having an offset value of 16 chips for an x sequence and generate and correlate another scrambling code maintaining the same code phase. At this time, it is not necessary to load the initial condition of the scrambling code generator that was previously performed to check for the next scrambling code. Also, the initial condition of one (eg, the first) scrambling code in each code group and the offset of 16 chip units The mask value only needs to be stored as many as the number of codes in the code group, and the selection of the correlation section can be arbitrarily selected.

Another method of the present invention is to perform a slew control on the x sequence generator of the scrambling code generator to change to another scrambling code that maintains the same code phase and then generate and correlate the code. In this manner, the loading of the initial condition for checking the next scrambling code is omitted, and only the initial condition of the first (or eighth) scrambling code of each code group needs to be stored. Here, the slew control is divided into "negative slew control" (hereinafter referred to as "high speed control") and "positive slew control" (hereinafter referred to as "low speed control"), and the high speed control is a sequence faster than the chip clock speed. Control to generate, and the low speed control means controlling to generate a sequence at a lower speed than the chip clock. In order to generate another scrambling code in the code group, the code sequence of the y sequence is maintained, and only the x sequence code phase needs to be advanced by 16 chips.

First, a method of controlling an offset of an x sequence by masking among the methods proposed by the present invention will be described.

9 illustrates a correlator according to an embodiment of the present invention.

Compared with FIG. 5, FIG. 5 changes the phase of the scrambling code by applying a mask having the same offset to the X sequence and the Y sequence, whereas FIG. 9 changes the other scrambling code by applying the mask only to the X sequence. The code generator of FIG. 9 is shown in more detail in FIG.

Referring to FIG. 9, the scrambling code generator 92 generates the scrambling code according to an initial condition given from the frame boundary. The scrambling code generated by the scrambling code generator 92 corresponds to the first scrambling code in the code group obtained in the cell search step 2. The X sequence masking unit 93 masks and outputs the X sequence output from the code generator 92 with a given mask value, and the final scrambling code is generated using the Y sequence and the masked X sequence. The mask values are stored in memory in advance. The upper controller loads the mask value into the x-sequence masking unit 93 at a predetermined time point, and the masking unit 93 generates the corresponding X sequence by the mask value. Since two adjacent scrambling codes in the same code group have an offset of 16 chips, the mask values are predetermined in consideration of this.

The correlator 91 correlates the received signal with the code provided by the code generator 92 and outputs the correlated signal.

Mask values having an offset of 16 chip units used in the present invention are shown below.

X-Sequence Mask for I-Channel

Offset Mask Value bit 17 ... bit 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 116 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 032 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 048 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 064 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 080 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 196 0 1 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 112 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1

Y-Sequence Mask for I-Channel

Offset Mask Value bit 17 ... bit 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 116 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 032 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 1 048 0 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 164 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 1 1 080 1 1 0 1 1 1 1 0 1 0 1 0 1 1 1 0 1 096 1 1 1 0 0 1 0 0 0 1 0 1 0 0 1 1 0 1 112 0 1 1 0 0 1 0 1 1 1 0 0 1 0 1 1 0 0

X-Sequence Mask for Q Channel

Offset Mask Value bit 17 ... bit 00 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 016 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 032 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 148 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 164 1 1 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 080 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 096 0 1 0 1 1 1 1 1 1 1 1 0 0 0 1 1 0 1 1 112 0 0 1 0 1 1 1 0 0 1 0 1 0 0 1 1 0 1

Y-Sequence Mask for Q Channel

Offset Mask Value bit 17 ... bit 00 0 0 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 016 1 1 1 0 1 1 0 1 1 1 0 1 0 0 0 0 0 132 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 148 0 1 0 1 1 0 0 0 0 0 1 1 0 1 0 1 1 064 0 0 1 1 1 1 0 1 1 0 1 1 1 0 0 1 0 080 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0 0 1 096 1 1 1 1 1 0 0 1 0 0 1 1 0 1 1 1 0 1 112 0 1 0 1 1 1 0 0 0 0 0 0 0 1 0 1 1 0

The operation of the correlator of FIG. 9 will now be described with reference to FIG. 10. During initialization, the scrambling code generator 92 initializes the first scrambling code in the code group obtained in the cell search step 2 by a given initial condition and applies a mask having an offset of zero to the X sequence generator. The correlator then searches from the frame boundary. Here, although the initialization operation generates the x sequence by the above-described generation polynomial, the state is generally stored and initialized at high speed. Only the first scrambling code of each group needs to be remembered for initialization.

First, the correlator 91 correlates and outputs a received signal and a first scrambling code output from the code generator 92 during a predetermined chip period in a frame boundary. When the correlation with the first scrambling code is completed, a mask value for the x sequence is loaded into the X sequence masking unit 93 for correlation with the second scrambling code, and the X sequence masking unit 93 is the X sequence generator. Masking operation of the output and the mask value generates an X sequence for the second scrambling code. Here, the mask value for the x sequence of the second scrambling code has an offset of 16 chips with respect to the x sequence of the first scrambling code. The second scrambling code maintains the same code phase as the first scrambling code. The scrambling code is provided to the correlator 91, and the correlator 91 correlates the received signal with the second scrambling code output from the masking unit 93 and outputs the correlation. When the correlation with the second scrambling code is completed, a mask value having a 32 chip offset with respect to the x sequence is loaded into the X sequence masking unit 93 for correlation with the third scrambling code, and generates a third scrambling code. To correlate with the received signal. In this way iterates to the eighth scrambling code. When the frame boundary is encountered while performing the correlation operation, the scrambling code generator 93 is initialized again.

According to the present invention described above, the initial condition of the scrambling code only needs to be stored in the code group (for example, the first code) while the conventional technology stores the initial conditions of all the scrambling codes. In addition, the correlation interval is not fixed as in the prior art, there is an advantage that can be set flexibly according to the situation. In the present invention, the storage size of the mask value in units of 16 chips for the X sequence required for the scrambling code conversion is sufficiently compensated by the above advantages.

Next, we will look at how to control the slew of the x and y sequences.

11 illustrates a correlator according to another embodiment of the present invention.

Referring to FIG. 11, the scrambling code generator 112 generates the scrambling code according to a given initial condition. The scrambling code generated by the scrambling code generator 112 at initialization corresponds to the first scrambling code in the code group obtained in the cell search step 2. The scrambling code generator 112 is the same as that shown in Fig. 5-1, but there is slew control for the X sequence. The scrambling code generator 112 applies a mask value corresponding to the offset of the search starting point from the frame boundary. Applying masking is intended to reduce the search speed and may be omitted when starting at frame boundaries. On the other hand, when the correlation for the generated first scrambling code is completed, the scrambling code generator 112 performs the through control on the x sequence to generate the second scrambling code of the same code phase. If negative slew, the m-sequence generator runs twice during one chip cycle, that is, the m-sequence generator runs at twice the speed of the chip clock. I never do that. Through the above-described control, different scrambled codes are generated on the same code phase. The correlator 111 correlates the received signal with a code provided by the scrambling code generator 112 and outputs the correlated signal.

The operation of the correlator of FIG. 11 will now be described with reference to FIG. 12. Upon initialization, the scrambling code generator 93 is initialized to the first scrambling code in the code group obtained in the cell search step 2 by a given initial condition. The correlator then searches from the frame boundary. In this case, the initialization operation can be accomplished by generating the x sequence by the above-described generation polynomial, and the state can be stored in advance and initialized at high speed. Only the first scrambling code of each group needs to be remembered for initialization. This is the case of using the high speed control for the X sequence, and if the low speed control is used, only the eighth scrambling code of each group is stored.

The correlation for the first scrambling code is assumed to start at the frame boundary. However, the search operation may start at a point other than the frame boundary. If a search operation is started at an arbitrary slot boundary other than the frame boundary, the masked output may be used after the initializing is performed and a mask corresponding to the slot is applied to the x sequence and the y sequence.

First, the correlator 91 correlates and outputs a received signal and a first scrambling code output from the code generator 93 during a predetermined chip period in a frame boundary. When the correlation for the first scrambling code is completed, the second scrambling code of the same phase is controlled by controlling two m-sequences of the scrambling code generator 112 for a correlation with the second scrambling code. Create If negative slew, the m-sequence generator runs twice during one chip cycle, that is, the m-sequence generator runs at twice the speed of the chip clock. I never do that.

For example, if the inspection is completed for the first scrambling code, high-speed control is performed for the x sequence and normal operation for the y sequence for the next 16 chip periods. That is, the y sequence generator performs a normal operation of generating one chip in one chip period. As a result, during the 16-chip cycle, since x-sequence is generated 32 chips and y-sequence is 16 chips, the x-sequence has a code phase that is advanced by 16 chips with respect to the y-sequence. It is the second scrambling code on the code phase.

As shown, the correlator 111 completes the inspection for the first scrambling code, has a predetermined time for the through control, and then correlates the received signal with the second scrambling code generated by the through control. Output In this way iterates to the eighth scrambling code. 15 illustrates an embodiment of a method of changing a scrambling code by x sequence high speed control. The x and y sequences will generate a sequence by each generation clock. First assume that the scrambling code is currently generating K times. When the correlation for the K scrambling code is completed, 16-chip high speed control is performed for the x sequence. High-speed control uses a generation clock that doubles the chip clock for 16 chip intervals. When the above process is completed, it is ready to generate the scrambling code of K + 1 and the searcher correlates the received signal with the K + 1 scrambling code.

The above method is also possible in reverse. After checking the 8th scrambling code of the code group, check the next scrambling code (the 7th scrambling code in the code group). Then, the y sequence operates normally for 16 chips and the positive slew is performed for the x sequence. . As a result, the y sequence is advanced by 16 chips for the x sequence, that is, the x sequence has a code phase that is retarded by 16 chips for the y sequence, thereby obtaining a seventh scrambling code. When the inspection is completed for the seventh scrambling code, the sixth scrambling code is checked in the same manner as described above. That is, it repeats up to the first scrambling code in this manner. For clarity, FIG. 16 illustrates an embodiment of a method of changing a scrambling code by x sequence low speed control. The x and y sequences will generate a sequence by each generation clock. First assume that the scrambling code is currently generating K times. When the correlation on the K scrambling code is completed, the 16-chip low speed control is performed for the x sequence. Low speed control does not apply a generation clock for 16 chip segments. When the above process is completed, it is ready to generate the K-1 scrambling code, and the searcher correlates the K-1 scrambling code with the received signal.

According to the present invention described above, the initial condition of the scrambling code only needs to store the initial condition of the first code or the eighth code in the code group, while the conventional technology stores the initial conditions of all the scrambling codes. In addition, the correlation interval is not fixed as in the prior art, there is an advantage that can be set flexibly according to the situation. The slew control required in the present invention has little additional burden on implementation and is sufficiently compensated by the above advantages.

In addition, the present invention may use any of the through control schemes in which the code phases of the x sequence and the y sequence have an offset in units of 16 chips in addition to the above through control schemes. In addition to the initial search, the present invention is applicable to other situations in which code group information and code phase information are given.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by those equivalent to the scope of the claims.

As described above, the present invention can solve the problem of limitation in hardware burden and correlation interval of the conventional serial search method. That is, the present invention can reduce the hardware volume of the correlator, eliminate the initialization operation of the scrambling code generator that is performed at every correlation check, and can select the correlation section arbitrarily while maintaining the same phase so that the code capture can be effectively performed. can do.

Claims (19)

A correlator for base station code acquisition in a code division multiple access communication system, The scrambling code is composed of an x sequence and a y sequence, and a scrambling code generator for generating a scrambling code by masking the x sequence with a given mask value; And a correlator for correlating a received signal with the generated scrambling code. The method of claim 1, wherein the scrambling code generation unit, A generator for generating a first scrambling code of a code group obtained through a synchronization channel, A memory for storing mask values for masking an x sequence of the first scrambling code; And a masking unit for masking the first scrambling code from the scrambling code generator and mask values from the memory to generate scrambling codes of the code group. The method of claim 1, And wherein the correlation for the first scrambling code is at a frame boundary. The method of claim 1, And two adjacent scrambling codes of the code group have an offset of 16 chips with respect to an x sequence, and the mask values are determined based on the offset. A correlator for base station code acquisition in a code division multiple access communication system, a generator having an x sequence generator and a y sequence generator, which generates scrambling codes of a code group obtained through a synchronization channel under the control of a through controller; A slew control unit for controlling the two sequence generators to operate at different speeds; And a correlator for correlating the received signal with the scrambling code from the generator. The method of claim 5, wherein the through control unit, The scrambling codes of the generated code group maintain the same code phase and differently control the operating speeds of the two sequence generators so that x sequences of two consecutive scrambling codes have an offset of 16 chips. Device characterized in that. The method of claim 5, And the correlation of the first scrambling code of the code group is at a frame boundary or at a stored offset time point. The method of claim 5, And if the correlation for one scrambling code is complete, the through control unit controls the x sequence generator to operate at twice the rate of the chip clock and the y sequence generator to operate at the normal chip rate. The method of claim 5, And if the correlation for one scrambling code is completed, the through control unit controls the x sequence generator to stop operating and the y sequence generator to operate at a normal chip speed. A correlation method for base station code acquisition in a code division multiple access communication system, The scrambling code is composed of x sequence and y sequence, and masking the x sequence by a given mask value to generate a scrambling code; And correlating a received signal with the generated scrambling code. The method of claim 10, wherein the scrambling code generation process, Generating a first scrambling code of a code group obtained through a synchronization channel, Providing mask values for masking an x sequence of the first scrambling code; Masking the generated first scrambling code and the provided mask values to generate scrambling codes of the code group; Selecting one of the first scrambling code and the scrambling code generated by the masking operation for correlation. The method of claim 10, Wherein the correlation for the first scrambling code is at a frame boundary. The method of claim 10, Two adjacent scrambling codes of the code group have an offset of 16 chips with respect to an x sequence, and the mask values are determined based on the offset. A correlation method for base station code acquisition in a code division multiple access communication system, Generating a predetermined scrambling code of a code group obtained through a synchronization channel through a code generator having two m-sequence generators, Generating the remaining scrambling codes of the code group by controlling the two sequence generators at different speeds; And correlating a received signal with the generated scrambling code. The method of claim 14, And wherein the scrambling codes of the generated code group have the same code phase. The method of claim 15, And the x sequences of two scrambling codes generated successively among the scrambling codes of the code group have an offset of 16 chips. The method of claim 14, And the correlation of the first scrambling code of the code group is at a frame boundary. The method of claim 14, And when the correlation for one scrambling code is complete, control the x sequence generator to operate twice as fast as the chip clock and the y sequence generator to operate at normal chip speed. The method of claim 14, And when the correlation for one scrambling code is complete, the x sequence generator stops operating and controls the y sequence generator to operate at a normal chip rate.