JPH06177856A - Spread spectrum multiple communication equipment - Google Patents

Abstract

PURPOSE:To reduce an inter-channel interference resulted from an inter-channel phase difference by rearranging spread spectrum modulated codes by a block interleave. CONSTITUTION:An exclusive logical sum circuit 19 performs the exclusive logical sum of a data signal read from a two port RAM 13 according to the algorithm of the block interleave and spreading codes rearranged according to the algorithm of the same block interleave read from an ROM 17, and prepares a spread spectrum modulated signal to which the block interleave is operated. An output is converted into a serial signal by a parallel/serial conversion circuit 20, and transmitted to a modulated signal output terminal 21. At a transmission side, a spread spectrum modulation is operated by using a prescribed spreading signal, and the block interleave corresponding to the spread spectrum modulation is operated, so that the continuous time of one chip of the spreading code can be enlarged to an appropriate value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum multiplex communication device for performing multiplex communication of n channel spread spectrum modulated signals.

[0002]

2. Description of the Related Art In spread spectrum communication, a transmitting side modulates a data signal with a high-speed spreading code (pseudo-random code), spreads the spectrum of the modulated signal into a wide frequency band, and spreads the same at the receiving side. This is a communication method for transmitting a data signal by demodulating (despreading) a received signal with a code.

FIG. 5 is a block diagram showing a configuration example of a conventional spread spectrum multiplex communication apparatus using direct spread. In the figure, on the transmitting side, a data signal of each channel input from a plurality of input terminals 51 and a spreading code corresponding to each channel output from a plurality of spreading code generators 52 are respectively exclusive OR circuits 53. Entered in. The exclusive OR circuit 53 performs an exclusive OR operation with 1 bit of the spread code (1 chip is 1 bit of the spread code) and 1 bit of the data signal to generate a spread spectrum modulation signal. The spread spectrum modulation signal of each channel is sent to the E / O converter 54 and converted into a light intensity modulation signal. The light intensity modulation signal output from each E / O converter 54 is multiplexed by a branch node 55 such as a star coupler or the like, and sent to one optical transmission path 56.

On the receiving side, the optical intensity modulated signal input from the optical transmission line 56 to the branch node 57 is distributed and output to a plurality of O / E converters 58. The output of each O / E converter 58 and the spread code corresponding to each channel output from the plurality of spread code generators 59 are input to the correlator 60 to be correlated with each other and demodulated as respective correlation values. A signal is output from each output terminal 61.

[0005]

In the conventional spread spectrum multiplex communication device, there is a distance difference between transmission and reception of each communication path. Since the inter-channel phase difference caused by this distance difference causes inter-channel interference, conventionally, P used for the spreading code is used.
This problem has been dealt with by setting the code length of the N series or the like large or by synchronizing the spread codes.

However, P which can reduce the inter-channel interference
The code length of N sequences and the like became enormous, and it could not be said to be a practical countermeasure. Further, in order to shorten the code length required for the PN sequence, in the synchronous multiplex communication in which the orthogonal sequence whose cross-correlation value between the codes is zero is used as the spreading code, the spreading code cannot be synchronized or an error occurs in the synchronization. In the case of occurrence, there is a problem that inter-channel interference rather increases.

An object of the present invention is to provide a spread spectrum multiplex communication device capable of reducing inter-channel interference caused by a phase difference between channels in multiplex communication of spread spectrum modulated signals.

[0008]

A spread spectrum multiplex communication apparatus of the present invention includes a cyclic matrix as a spreading code assigned to each of continuous k data on the transmitting side.
From one code sequence, a predetermined row corresponding to the data position within the number of multiplex channels n and k is assigned to perform spread spectrum modulation, and the spread spectrum modulated signals of continuous k data are equalized. Transmission means is provided for generating a transmission signal by block interleaving in which chips at positions are extracted and arranged.

Further, on the receiving side, re-block interleaving in which the chips rearranged by the block interleaving of the transmitting means are rearranged in the original order is performed, and the reconstructed spread spectrum modulated signal is assigned by the transmitting means. A demodulation unit for performing spread spectrum demodulation using a spreading code equal to the spreading code is provided.

[0010]

In the transmission side of the spread spectrum multiplex communication device, spread spectrum modulation is performed using a predetermined spread code, and block interleaving corresponding to spread spectrum modulation is performed, so that the number of multiple channels and the expected channel spacing are increased. With respect to the phase difference, the duration of one chip of the spreading code can be expanded to an appropriate value.

[0011]

1 is a block diagram showing the configuration of an embodiment of a spread spectrum multiplex communication apparatus of the present invention. (a) shows a configuration example of a transmitter that generates a transmission signal by spread spectrum modulation and block interleaving, and (b) shows a configuration example of a receiver that performs spread spectrum demodulation and reblock interleaving corresponding to the transmitter.

The transmitter of this embodiment is replaced with a conventional transmitter composed of a spread code generator 52 and an exclusive OR circuit 53 shown in FIG. 5, and the receiver of this embodiment is shown in FIG. The spread spectrum multiplex communication device of the present invention is constructed by replacing the conventional receiver composed of the spread code generator 59 and the correlator 60 shown in FIG.

In FIG. 1A, reference numeral 11 is a data signal input terminal in the transmitter. The serial / parallel conversion circuit 12 converts the input data signal into a y-bit parallel signal and supplies it to the input port of the 2-port RAM 13. The counter 14 generates a write address to be given to the 2-port RAM 13. The writing / reading designation circuit 15 divides the storage area of the 2-port RAM 13 into two, and alternately designates the writing side and the reading side for each cycle of the block interleaving algorithm. ROM1
6 stores an address for reading the data signals sequentially stored in the 2-port RAM 13 according to the block interleaving algorithm. The ROM 17 stores spread codes rearranged by the same block interleaving algorithm.

The counter 18 gives read addresses to the ROMs 16 and 17, and the ROMs 16 and 17 respectively read the read address and spread code from the 2-port RAM 13.
And the exclusive OR circuit 19. Further, the counter 18 sends a clear pulse generated in each cycle of block interleaving to the counter 14 and the write / read designation circuit 15. The exclusive OR circuit 19 is 2
The data signal read from the port RAM 13 and RO
Exclusive-OR with the spreading code read from M17. The parallel / serial conversion circuit 20 converts the output of the exclusive OR circuit 19 into a serial signal and sends it to the modulation signal output terminal 21.

The operation of the transmitter configured as described above is as follows. The length of the spreading code used in this transmitter is M, and the speed of the spread spectrum modulation signal is fc (b
ps), and the speed of the input data signal is fc / M (bps)
As described below.

First, the operation on the write side of the 2-port RAM 13 will be described. The data signal input from the data signal input terminal 11 and converted into a y-bit parallel signal by the serial / parallel conversion circuit 12 is a 2-port RA signal.
The data is input to the input port (y-bit input) of M13 and sequentially written in one storage area divided into two by the write / read designation circuit 15. The output of the counter 14 is used as the write address at this time. The operation clock of the counter 14 is the data signal clock fc /
The speed fc / (M · y) (bps) obtained by dividing M (bps) by the bit number y of the input port of the 2-port RAM 13 is used. This operation clock is also used as a write pulse.

When data is being written from the input port of the 2-port RAM 13, the data written one cycle before is read to the output port from the other storage area. This switching between writing and reading is performed by switching the MSB of the writing and reading addresses in the writing / reading designation circuit 15 according to a clear pulse given from the counter 18 every cycle of the block interleaving rearrangement algorithm. . Therefore, the counter 14 to which the same clear pulse is input
Is cleared at the same time as the MSB is switched by the write / read designation circuit 15.

Next, the operation of the read side of the 2-port RAM 13 will be described. Data written in sequence from the input port for each cycle of block interleaving is RO
It is read from the output port according to the block interleaving algorithm by the address output from M16. If the block interleaving is performed for a fixed number of k blocks with 1 bit of the data signal as one block, for example, the 0th to (k-1) th data are read out in sequence and the length of the spread code M Repeat only once. The read address of the 2-port RAM 13 is changed by designating the output of the counter 18 as the address of the ROM 16.

Therefore, the operation clock of the counter 18 becomes the read clock from the 2-port RAM 13,
Speed obtained by dividing the clock fc (bps) of the spread spectrum modulation signal by the bit number y of the output port of the 2-port RAM 13.
fc / y (bps) is used. Further, one cycle of the block interleaving algorithm is (1 / fc) · M · k = M · k / fc (sec) because one cycle of the spread spectrum modulation signal is 1 / fc. Therefore, the counter 18 is M · k / fc (se
It is cleared every c) and its output is 0- (Mk / y-
Repeat 1). The clear pulse generated every one cycle of the block interleave becomes a clock of the write / read designation circuit 15 that switches the MSB of the write and read addresses, and is used as the clear pulse of the counter 14 that designates the address on the write side.

In the exclusive OR circuit 19, the data signal thus read from the 2-port RAM 13 according to the block interleaving algorithm and the ROM 1
By taking the exclusive OR with the spreading code rearranged by the same block interleaving algorithm read out from 7, it is possible to generate a spread spectrum modulated signal subjected to block interleaving. Further, this output is converted into a serial signal by the parallel / serial conversion circuit 20 having an operating speed fc (bps) and sent to the modulation signal output terminal 21.

The spreading code at this time is a complete cyclic matrix such as M sequence of M rows and M columns, or its (M-1) rows (M-1) such as a cyclic Hadamard matrix of M rows and M columns. ) A code of L rows and M columns including one or more cyclic matrices of L rows and L columns, such as a code series whose core matrix (core) of columns is a complete cyclic matrix, or a code series formed by arranging such code series Use sequences (M ≧ L). The cyclic code of L rows and L columns is a codeword (x
₀ , x ₁ , x ₂ , ..., X _L-1 ) is cyclically replaced in the right direction, and can be expressed as follows. Here, assuming that the number of multiplexed channels is n, the j-th data in the k continuous data (k is a multiple of n) of the i-th channel (i = 0, 1, 2, ..., N-1) (J = 0,
1, 2, ..., K−1), the h-th row is used from the code sequence of L rows and M columns including this cyclic matrix of L rows and L columns. However, h is a value obtained by rounding up (L · k · i / n−j) / k after the decimal point. The spreading code having the length M determined in this way is rearranged by the block interleaving algorithm, that is, the first chip of each spreading code assigned to k pieces of data is k pieces, and then the second chip is 2 pieces. It is stored in the ROM 17 in the state of k eyes. An example of the spread code stored in the ROM 17 is shown in FIG.

FIG. 2A shows the case where each row of the 15 × 15 cyclic matrix is allocated to a total of 8 channels and the i-th row of the cyclic matrix is allocated to the i-th channel. Indicates the case where the spreading code is assigned according to the above rule.

In the allocation of (a), if there is no phase difference between the channels, the spread codes used for the spread spectrum modulation signals transmitted from the respective channels will not match. However, if there is a phase difference between channels even for one chip, there will be a portion where the spreading codes used match. This is because the phase difference for one chip corresponds to the code shift of the adjacent row by using the adjacent rows of the cyclic matrix.

On the other hand, in the allocation of (b), if the phase difference between the channels is within (15 / 8-1) k chips, the spreading codes allocated to the respective channels do not match. That is, when block interleaving of k blocks is performed using a code including a cyclic matrix of L rows, the maximum phase difference in which the spreading codes assigned to each channel do not match is (L / n−1) k chips. , For each channel (L /
n) The allowable phase difference can be maximized by allocating spreading codes that are shifted by k chips.

Next, with reference to FIG. 1 (b), a receiver that performs spread spectrum demodulation and reblock interleaving corresponding to the transmitter will be described. In FIG. 1 (b), reference numeral 31 is a modulation signal input terminal to which the transmitted spread spectrum modulation signal is input. A / D conversion circuit 32
Converts the input spread spectrum modulation signal into an x-bit digital signal and supplies it to the input port of the 2-port RAM 33. The counter 34 generates a write address to be given to the 2-port RAM 33 and an address to be given to the ROMs 35 and 36. ROM35 has 2 port RAM
Addresses at the time of reading the data sequentially stored in 33 according to the reverse algorithm of block interleaving (reblock interleaving) used on the transmission side are stored, and a read address corresponding to the address given by the counter 34 is given to the 2-port RAM 33. The spreading code rearranged by the same re-block interleaving algorithm is stored in the ROM 36, and the spreading code corresponding to the address given by the counter 34 is given to the multiplication accumulator 38.

The write / read designation circuit 37 divides the storage area of the 2-port RAM 33 into two, and alternately designates the write side and the read side for each cycle of the re-block interleaving algorithm. The multiplication accumulator 38 stores the data signal read from the 2-port RAM 33 in the ROM 3
The signals are accumulated with the polarity corresponding to the spread code read out from No. 6, and sent to the synchronization determination circuit 39 and the MSB selection circuit 40.
The synchronization determination circuit 39 determines synchronization from the output of the multiplication accumulator 38, and when the synchronization is achieved, sends a clear pulse to the counter 34 and the write / read designation circuit 37.
The MSB selection circuit 40 receives the MS from the output of the multiplication accumulator 38.
B is selected and sent to the demodulation signal output terminal 41 as a spread spectrum demodulation signal.

The operation of the receiver configured as described above is as follows. The speed of the input signal to the receiver is equal to the speed fc (bps) of the spread spectrum modulation signal and also the speed of the spread spectrum demodulation signal. The spreading code used by the receiver is equal to the spreading code assigned by the transmitter according to the above rule.

First, the operation on the write side of the 2-port RAM 33 will be described. The speed fc (b
The spread spectrum modulation signal input at ps) is converted into an x-bit digital signal at the sampling frequency fc (Hz). Further, this digital signal is a 2-port RA
It is input to the input port (x-bit input) of M33, and is sequentially written in one storage area divided into two by the write / read designation circuit 37. As the write address at this time, the output of the counter 34 by the operation clock of the speed fc (bps) is used. This operation clock is also used as a write pulse.

When writing is performed from the input port of the 2-port RAM 33, the data written one cycle before the re-block interleaving is read to the output port from the other storage area. This switching between writing and reading is performed by switching the MSB of the writing and reading addresses in the writing / reading designation circuit 37. Therefore, the counter 34 is cleared simultaneously with the switching of the MSB by the write / read designation circuit 37. This MSB switching is performed for one cycle of re-block interleaving ((1 / fc) · M · k (sec)).
Therefore, the output of the counter 24 is 0 to (M · k−
Repeat 1).

Next, the operation on the read side of the 2-port RAM 33 will be described. The output of the counter 34 is the ROM 3
By specifying the read address of 5, the read address of the 2-port RAM 33 is created. 2 port R
From the output port of the AM 33, the data written one cycle before according to the read address is read at the operation speed fc (bps) of the counter 34. The read address algorithm stored in the ROM 35 uses a signal of k chips obtained by exclusive OR with a position (chip) having the same spread code in the transmitter as one block,
The operation of sequentially arranging the signals corresponding to equal positions in each block from each of the blocks is repeated k times for all chips of the block (reblock interleaving).

The data read from the 2-port RAM 33 is multiplied / accumulated by a predetermined constant every 1 / fc (sec) in the multiplication accumulator 38, and the accumulated value is set to the 1-bit interval of the data signal before modulation. It is cleared every corresponding M / fc (sec). The clear timing of the accumulated value and the positive and negative polarities at the time of accumulation are stored in the ROM 36, and the output of the counter 34 is used as a read address of the ROM 36. Further, in the ROM 36, the spreading code assigned from the code sequence of L rows and M columns according to the above rule is stored in the ROM 36 as it is. The output of the multiplication accumulator 38 is sent to the synchronization determination circuit 39, and when demodulation is performed by the number of blocks k for each cycle of block interleaving, a clear pulse is sent to the counter 34 and the transmitted spread spectrum modulation signal. Block interleaving rearrangement algorithm applied to
5, 36, and is synchronized with the re-block interleaving permutation algorithm stored at 5, 36. Also, MSB
The selection circuit 40 can obtain the spread spectrum demodulation signal by selecting the MSB from the output of the multiplication accumulator 38.

FIG. 3 is a diagram showing a code error rate characteristic (theoretical value) according to the prior art and the present invention when two channels are multiplexed. In the figure, the horizontal axis represents the transmission distance difference between the two channels, and the vertical axis represents the code error rate. 32 for the spreading code
It is assigned from the × 32 cyclic Hadamard matrix. Also, depending on the transmission distance difference between channels, 200
The code phase difference between chips and the reception level difference of 2 dB per km are set.

The code error rate characteristics of the prior art are represented by thin lines, but it can be seen that the code error rate deteriorates rapidly in places. On the other hand, although the code error rate characteristic by the block interleaving of the present invention is represented by A, it is clear that the code error rate characteristic is improved. This is done by applying block interleaving with the number of blocks k = 2000,
The duration of one chip of spreading code exceeds the phase difference corresponding to the transmission distance, and the phase difference between codes of spreading codes between channels is set to a small value of 1 chip at the maximum, so the orthogonality between cyclic Hadamard matrices is effective. And the interference between channels due to the phase difference is suppressed to a small value.

FIG. 4 is a diagram showing the relationship between the number of blocks k and the number of multiplex channels n when 31 × 31 M sequences are used for spreading codes. In the figure, the horizontal axis represents the number of multiplexed channels n, and the vertical axis represents k / d when the inter-channel phase difference δ is d × 1 chip time. Also, is M for one channel
This is a case where one line of the series is assigned as it is,
In the present invention, spread codes are assigned according to the number of channels, but it can be understood that the maximum number of blocks k can be reduced by about 45% even when the same number of channels is assigned according to the present invention.

In the method of allocating one row of the code sequence of L rows to one channel, L / 2 (31/31 in this example) is used.
It is not possible to multiplex channels beyond 2). On the other hand, according to the present invention, multiplexing can be performed even when the number of channels exceeds L / 2. The reason for this can be explained as follows.

That is, when spreading codes are assigned to channels from one sequence over L / 2, adjacent rows are always assigned. However, for a given phase difference, the number of blocks in block interleaving k
No matter how large is set, data having a phase difference of 1 chip exists between the signals rearranged by block interleaving. Therefore, if one row is assigned to one channel, the codes of the data having the phase difference of one chip will match and the demodulation will not be possible. On the other hand, in the spreading code allocation according to the present invention, the spreading codes allocated within the k blocks of the block interleave are changed so that the codes of the data having the phase difference of 1 chip do not match. This is because it becomes possible.

[0037]

As described above, according to the present invention, by spreading the spread spectrum modulated signal by block interleaving, the duration of one chip of the spread code can be sufficiently extended. This makes it possible to perform spread spectrum multiplex communication in which the codes are synchronized with each other without delay control for multiplexing a plurality of channels having a phase difference. That is, it is possible to reduce inter-channel interference caused by the inter-channel phase difference.

When performing block interleaving,
Compared to the case where one spreading code is assigned to one channel by changing the row to be assigned as a spreading code from a cyclic sequence or a sequence including this according to the number of multiple channels in a block of block interleave. , Block interleaving of an appropriate number of blocks can be performed according to the phase difference between multiple channels. further,
Multiple communication can be enabled even for the number of channels exceeding 1/2 of the number of rows of the cyclic sequence, which is impossible when one spread code is assigned to one channel.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a spread spectrum multiple communication device of the present invention.

FIG. 2 is a diagram showing an example of spread codes stored in a ROM 17.

FIG. 3 is a diagram showing code error rate characteristics according to a conventional technique and the present invention when two channels are multiplexed.

FIG. 4 is a diagram showing a relationship between the number of blocks k and the number of multiplex channels n when a 31 × 31 M sequence is used as a spreading code.

FIG. 5 is a block diagram showing a configuration example of a conventional spread spectrum communication apparatus using direct spread.

[Explanation of symbols]

 11 data signal input terminal 12 serial / parallel conversion circuit 13,33 2-port RAM 14, 18, 34 counter 15, 37 write / read designation circuit 16, 17, 35, 36 ROM 19 exclusive OR circuit 20 parallel / serial conversion Circuit 21 Modulation signal output terminal 31 Modulation signal input terminal 32 A / D conversion circuit 38 Multiply accumulator 39 Synchronization determination circuit 40 MSB selection circuit 41 Demodulation signal output terminal

Claims (1)

[Claims] 1. A spread spectrum multiplex communication device that multiplexes and transmits an n-channel spread spectrum modulated signal generated using a predetermined spread code, and performs spread spectrum demodulation on the receiving side using the same predetermined spread code. In spread-spectrum modulation, a spreading code assigned to each of continuous k data is assigned a predetermined row from one code sequence including a cyclic matrix according to the number of multiplex channels n and the data position within k. And transmitting means for generating a transmission signal by block interleaving in which chips at equal positions are extracted and arranged from each of the spread spectrum modulation signals of continuous k data, and rearranged by the block interleaving of the transmitting means. Re-block interleave to rearrange the chips in their original order And a demodulation means for performing spread spectrum demodulation on the reconstructed spread spectrum modulated signal using a spreading code equal to the spreading code assigned by the transmitting means. .