KR20020028279A - Fabrication method of SrTiO3 SMD-type varistor-capacitor multifunctional device - Google Patents
Fabrication method of SrTiO3 SMD-type varistor-capacitor multifunctional device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
- H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
- H01C7/105—Varistor cores
- H01C7/108—Metal oxide
- H01C7/115—Titanium dioxide- or titanate type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/06—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
- H01C17/065—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thick film techniques, e.g. serigraphy
- H01C17/06506—Precursor compositions therefor, e.g. pastes, inks, glass frits
- H01C17/06513—Precursor compositions therefor, e.g. pastes, inks, glass frits characterised by the resistive component
- H01C17/06553—Precursor compositions therefor, e.g. pastes, inks, glass frits characterised by the resistive component composed of a combination of metals and oxides
Abstract
Description
본 발명은 SrTiO3계 SMD(Surface Mountable Device)형 바리스터-캐패시터 복합기능소자 제조기술에 관한 것으로, 보다 상세하게는 소결시 환원분위기로 입내(grain)를 반도체화한 후 열처리를 통하여 입계(grain boundary)를 절연화하며, 내부전극으로 Ag/Pd 또는 Ni 전극을 이용하기 위해 소결 온도를 1200℃로 낮추는 제조기술에 관한 것이다.The invention SrTiO 3 based SMD (Surface Mountable Device) type varistor-capacitor composite function as devices on the manufacturing technology, more particularly to a grain boundary (grain boundary through an after heat-treatment the semiconductor screen of halitosis (grain) in a reducing atmosphere during sintering Insulation) and to reduce the sintering temperature to 1200 ℃ in order to use the Ag / Pd or Ni electrode as an internal electrode.
기존의 바리스터는 산화아연(ZnO)를 기본 원료로 하여 산화비스머스(Bi2O3),산화코발트(CoO), 산화망간(CrO3) 등의 원소를 소량첨가하여 혼합한 다음 건조, 조립 및 성형공정을 거쳐 소결하여 제조되는 것이 일반적이다. 이러한 바리스터는 외부에서 갑자기 인입되는 과전압이나 노이즈로부터 기기 및 회로를 보호하는 소자로써 널리 이용되고 있다.Conventional varistors use zinc oxide (ZnO) as a basic raw material, add a small amount of elements such as bismuth oxide (Bi 2 O 3 ), cobalt oxide (CoO), and manganese oxide (CrO 3 ), and then dry, assemble and It is generally manufactured by sintering through a molding process. Such varistors are widely used as devices for protecting devices and circuits from sudden overvoltage or noise that may be introduced from the outside.
최근에는 이러한 소자를 SrTiO3를 원료로 하여 제조하는 기술이 개발되었는데 이러한 SrTiO3계 바리스터는 유전율이 기존의 ZnO계 바리스터에 비하여 100배 내지는 1000배정도 크기 때문에 캐패시터로 적용도 가능하며 급격히 인입되는 노이즈나 과전압을 흡수하는 효율이 월등하다.Recently, a technology for manufacturing such devices using SrTiO 3 has been developed. Since SrTiO 3 varistors have a dielectric constant of about 100 to 1000 times larger than conventional ZnO based varistors, they can be applied as capacitors and can be rapidly introduced into noise. The efficiency of absorbing overvoltage is superior.
SrTiO3계 바리스터는 입내(grain)의 전도성을 향상시키고 입계(grain boundary)를 절연화시켜 제조되는 것이 일반적인 제조 방법이다. 최근에는 회로의 소형화와 집적화로 인하여 SMD형 적층칩의 개발이 진행되었다.SrTiO 3 -based varistors are generally manufactured by improving grain conductivity and insulating grain boundaries. Recently, due to the miniaturization and integration of circuits, development of SMD type stacked chips has been in progress.
이러한 적층칩의 경우 기존의 입계 저항층 형성방법인 산화물 확산을 이용할 수 없기 때문에 환원소결 후 산화를 통하여 입계의 저항을 제어하여야 한다.In the case of such a stacked chip, since the oxide diffusion, which is a conventional method of forming the grain boundary layer, cannot be used, the resistance of the grain boundary must be controlled through oxidation after reduction sintering.
SrTiO3바리스터-캐패시터 복합기능 소자를 개발함에 있어서 가장 중요한 부분이 재산화과정이다. 일반적으로, SrTiO3계 바리스터가 특성을 나타내기 위해서는 입내(grain)는 반도체화하여야 하고 입계(grain boundary)는 절연화되어야 한다. 환원 소결 후 세라믹이 완전히 환원된 상태에서는 입내 및 입계의 저항차이가 작을뿐만 아니라 각각의 저항치도 낮아 캐패시터 특성은 존재할 수 없다. 또한, 바리스터 특성을 기대할 수 없게 된다.The most important part in the development of SrTiO 3 varistor-capacitor composite functional devices is the reoxidation process. In general, grains must be semiconductorized and grain boundaries must be insulated for SrTiO 3 -based varistors to be characterized. In the state in which the ceramic is completely reduced after reduction sintering, not only the resistance difference between the grains and grain boundaries is small, but also the resistance of each is low so that the capacitor characteristics cannot exist. In addition, varistor characteristics cannot be expected.
따라서, 전술한 점을 감안한 본 발명의 목적은 SrTiO3계 바리스터의 특성을 나타내기 위하여 소결시 환원분위기로 입내(grain)를 반도체화한 후 열처리를 통하여 입계(grain boundary)를 절연화함으로써 산화아연(ZnO)바리스터에 비하여 유전율이 10000 이상이고 유전손실이 5%미만인 바리스터 및 캐패시터 특성을 동시에 나타내는 바리스터-캐패시터 복합기능소자를 제조하는 방법을 제공함에 있다.Accordingly, an object of the present invention in view of the foregoing is to zinc oxide by insulating grain boundaries through heat treatment after semiconductorizing grains with a reducing atmosphere during sintering in order to exhibit the characteristics of SrTiO 3 -based varistors. The present invention provides a method for manufacturing a varistor-capacitor composite functional device which simultaneously exhibits varistor and capacitor characteristics having a dielectric constant of 10000 or more and a dielectric loss of less than 5% compared to a (ZnO) varistor.
본 발명의 다른 목적은 생산단가를 낮추기 위해 Ag/Pd 또는 Ni 전극을 내부전극으로 이용하며, 이를 위해 소결 온도를 기존의 1440℃이상에서 1200℃로 낮추는 바리스터-캐패시터 복합기능소자 제조기술을 제공함에 있다.Another object of the present invention is to use a Ag / Pd or Ni electrode as an internal electrode in order to lower the production cost, to provide a varistor-capacitor composite functional device manufacturing technology for this purpose to lower the sintering temperature from the existing 1440 ℃ to 1200 ℃ have.
도 1은 본 발명이 적용된 소자의 형상을 나타낸 도면.1 is a view showing the shape of the device to which the present invention is applied.
도 2는 본 발명의 제조공정을 나타내는 순서도.2 is a flow chart showing a manufacturing process of the present invention.
도 3은 본 발명에 따른 시편의 온도에 따른 유전특성을 나타내는 그래프.Figure 3 is a graph showing the dielectric properties according to the temperature of the specimen according to the present invention.
도 4는 본 발명에 따른 시편의 전류-전압 특성을 나타내는 그래프.4 is a graph showing the current-voltage characteristics of the specimen according to the present invention.
위와 같은 목적을 달성하기 위한 본 발명의 제조기술은 SrTiO3를 기본 조성으로 하고 Ag/Pd 또는 Ni 전극을 내부 전극으로 하여 환원분위기 소결과 재산화공정을 통하여 캐패시터 특성 및 바리스터 특성을 갖는 소자를 제조하는 것이다.The manufacturing technology of the present invention for achieving the above object is to manufacture a device having a capacitor characteristics and varistor characteristics through the reduction atmosphere sintering and reoxidation process using SrTiO 3 as a basic composition and Ag / Pd or Ni electrode as an internal electrode It is.
이러한 바리스터 및 캐패시터의 특성을 동시에 갖는 복합소자를 제조하기 위한 제조기술은, 원료분말 및 유기매체를 혼합하여 슬러리를 제조하는 단계, 제조된 슬러리를 캐스팅하여 세라믹 시트를 제조하는 단계, 세라믹 시트를 적정크기로 절단하여 내부전극을 인쇄하는 단계, 내부전극이 인쇄된 세라믹 시트를 적층하는 단계, 적층된 세라믹 적층체를 환원분위기로 소결하는 단계, 소결에 의한 소결체를재산화하는 단계 및 재산화된 소결체에 외부전극을 형성하는 단계로 이루어진다.The manufacturing technology for manufacturing a composite device having the characteristics of the varistor and the capacitor at the same time, a step of preparing a slurry by mixing the raw powder and the organic medium, casting the prepared slurry to prepare a ceramic sheet, titrating the ceramic sheet Printing the internal electrode by cutting to size, laminating ceramic sheets printed with the internal electrode, sintering the laminated ceramic laminate in a reducing atmosphere, reoxidizing the sintered body by sintering, and reoxidized sintered body Forming an external electrode on the substrate.
이하, 예시된 도면들을 참조하여 실시예를 통해 본 발명의 제조기술을 상세하게 설명한다.Hereinafter, the manufacturing technology of the present invention will be described in detail with reference to the illustrated drawings.
도 1은 본 발명에 의해 제조된 소자의 형상을 나타내는 것으로, 도 2의 제조공정에 따라 제조된다.Figure 1 shows the shape of the device manufactured by the present invention, is manufactured according to the manufacturing process of FIG.
본 발명에 따른 실시예에서 슬러리 제조를 위한 원료분말의 기본 조성은 Sr0.9Ca0.1TiO3으로 고정하였다. 이때, 원료분말의 혼합물에 첨가되는 반도체화물 Nb2O5는 0.4 ∼ 0.6 mol%씩 첨가하였다. 하소는 1100℃에서 2시간동안 수행하여 합성하였으며, 저온소결을 위해 SiO2및 MnO를 각각 0.1 ∼ 0.3mol% 및 0.1 ∼ 0.3 mol%씩 첨가한 후 다시 48시간 동안 습식 밀링하였다. 밀링이 끝난 분말을 충분히 건조한 후 시트성형을 위해 적절한 유기매체(Organic vehicle)을 첨가하여 다시 48시간 동안 혼합하여 슬러리(slurry)를 제조하였다. 이러한 슬러리제조는 산화물 혼합법으로 제조하였는데 배치(Batch)량은 600g 정도로 고정하였으며, 칭량은 10-3g정도의 범위로 조절하였다.In the embodiment of the present invention, the basic composition of the raw material powder for slurry production was fixed to Sr 0.9 Ca 0.1 TiO 3 . In this case, the semiconductor storage Nb 2 O 5 is added to a mixture of raw material powder was added by 0.4 ~ 0.6 mol%. Calcination was carried out at 1100 ° C. for 2 hours to synthesize, and 0.1 to 0.3 mol% and 0.1 to 0.3 mol% of SiO 2 and MnO were added for low temperature sintering, and then wet milling for 48 hours. After the milled powder was sufficiently dried, a slurry was prepared by adding an appropriate organic vehicle for sheet molding and mixing for 48 hours. The slurry was prepared by an oxide mixing method, but the batch amount was fixed at about 600 g, and the weighing was adjusted in the range of about 10 -3 g.
이때, 유기매체의 고체량과 원료분말간의 비율은 40 : 60의 비율로 고정하여 제조하였다. 이와 같이 제조된 슬러리를 닥터 블레이드(doctor blade)법을 응용한 테이프 케스터(tape caster)장비로 두께가 80㎛정도로 성형하여 세라믹 시편을 제조 한 후에 12시간 정도 충분히 건조하였다. 이때, 슬러리의 점도 및 비중 그리고 테이프캐스팅 속도 등을 조절하여 세라믹 시트의 제반특성을 조절한다.At this time, the ratio between the solid amount of the organic medium and the raw material powder was prepared by fixing at a ratio of 40:60. The slurry thus prepared was molded to a thickness of about 80 μm by a tape caster device using a doctor blade method, and then dried sufficiently for about 12 hours after preparing ceramic specimens. At this time, by adjusting the viscosity and specific gravity of the slurry and the tape casting speed and the like to adjust the overall characteristics of the ceramic sheet.
충분히 건조된 세라믹 시트를 적정크기로 절단한 후 내부전극을 인쇄하는데, 이러한 내부전극은 Ag/Pd 또는 Ni 전극을 이용하며, 그린쉬트(Green Sheet)위에 내부전극을 인쇄한 후 이를 3 ∼ 5 층으로 겹쳐 쌓아서 적층하였다. 적층이 끝난 적층체를 3216 사이즈로 커팅(cutting)한 후 바인더번아웃(binder-burn-out)은 24시간 동안 일정온도에서 충분히 행하였다. 바인더번아웃이 끝난 세라믹 시편은 1100℃에서 1시간 가소결(pre-sintering)하였다. 소결분위기는 N2및 H2의 혼합비율을 10 : 1로 고정하여 진행한다. 소결분위기 조절은 자동화된 MFC(Mass Flow Controller)를 이용하였으며, 튜브는 고순도의 알루미늄으로 제작된 것을 이용하였다. 다음에, 세라믹 소결체를 재산화 하는데, 이러한 재산화 공정은 분위기로를 사용하였으며, 공기를 이용하여 재산화하였다. 이때, 재산화 온도는 900℃ ∼ 1100℃까지 조절하며 진행하였다.The internal electrode is printed after cutting a sufficiently dried ceramic sheet to an appropriate size. This internal electrode uses Ag / Pd or Ni electrode, and after printing the internal electrode on the green sheet, it is 3 to 5 layers. Stacked and stacked. After the laminate was cut to 3216 size, the binder burnout was sufficiently performed at a constant temperature for 24 hours. The ceramic specimens after binder burnout were pre-sintered at 1100 ° C. for 1 hour. The sintering atmosphere is carried out by fixing the mixing ratio of N 2 and H 2 to 10: 1. The sintering atmosphere was controlled using an automated mass flow controller (MFC), and the tube was made of high purity aluminum. Next, the ceramic sintered body was reoxidized, and this reoxidation process was used as an atmosphere furnace and reoxidized with air. At this time, the reoxidation temperature was adjusted to 900 ~ 1100 ℃.
내부 전극의 종류에 따라 외부 전극형성은 다르게 진행되며 본 발명에서는 Ag/Pd 또는 Ni 내부 전극을 이용한 진행과정이 상세하게 후술된다.External electrode formation proceeds differently according to the type of internal electrode, and the process using Ag / Pd or Ni internal electrodes will be described later in detail.
우선, Ag/Pd 내부 전극을 이용하는 경우에 있어서, Ag/Pd 전극은 혼합비율이 각각 30 : 70인 조성을 이용하여 내부전극을 형성하였다. Ag/Pd 내부전극의 경우 재산화시 내부전극 산화에 따른 영향이 없는 귀금속 전극이므로, N2및 H2의 비율이 90 : 10인 환원분위기하에서, 1175℃에서 1시간동안 소결한 후 공기중에서 재산화하였다.First, in the case of using an Ag / Pd internal electrode, the Ag / Pd electrode formed an internal electrode using a composition having a mixing ratio of 30:70, respectively. Ag / Pd internal electrode is a noble metal electrode that has no effect of internal electrode oxidation during reoxidation, so it is sintered for 1 hour at 1175 ℃ under reduced atmosphere with N 2 and H 2 ratio of 90: 10 It was done.
재산화공정은 900℃ ∼ 1100℃까지 변화하며 진행하였으며, 유지시간도 변화하며 제조하였다.Reoxidation process was carried out varying from 900 ℃ to 1100 ℃, was also manufactured with a change in holding time.
이러한 재산화 온도 및 유지시간의 변화에 따른 유전특성 및 바리스터의 특성은 표 1에 나타나 있다.The dielectric properties and varistor characteristics of the reoxidation temperature and the retention time are shown in Table 1.
(K:유전율, tan δ: 유전손실, α: 0.1㎃에서 1㎃까지의 비선형계수)(K: dielectric constant, tan δ: dielectric loss, α: nonlinear coefficient from 0.1㎃ to 1㎃)
재산화 공정까지 끝난 세라믹 시편은 연마하여 내부전극을 노출시킨 후 Ag 전극을 도포시켜 외부전극을 형성하였다.The ceramic specimens finished up to the reoxidation process were polished to expose the internal electrodes and then coated with Ag electrodes to form external electrodes.
다음으로, Ni 내부 전극을 이용하는 경우에 있어서, Ni 내부 전극은 비금속 전극이므로 재산화 공정시 내부 전극이 산화되어 전극으로써의 기능을 상실할 위험성이 있다. 따라서, 본 발명에서는 환원 소결이전에 가소결된 시편을 연마하여 내부 전극을 노출시킨 후 Ni 전극을 도포시켜 외부전극을 형성하였다.Next, in the case of using the Ni internal electrode, since the Ni internal electrode is a non-metal electrode, there is a risk that the internal electrode is oxidized during the reoxidation process and loses its function as an electrode. Therefore, in the present invention, the pre-sintered specimen was polished prior to reduction sintering to expose the internal electrode, and then the Ni electrode was applied to form the external electrode.
소결은 N2: H2의 비율이 10 : 1인 환원분위기하에서 1200℃에서 1시간동안 하였으며, 재산화는 Ag/Pd 전극 시편과 동일하게 900℃ ∼ 1100℃까지 변화하며 진행하였다.Sintering was carried out at 1200 ° C. for 1 hour under a reducing atmosphere of N 2 : H 2 ratio of 10: 1, and reoxidation proceeded from 900 ° C. to 1100 ° C. in the same manner as the Ag / Pd electrode specimens.
이러한 재산화 온도 및 유지시간의 변화에 따른 유전특성 및 바리스터의 특성은 표 2에 나타나 있다.The dielectric properties and varistor characteristics of the reoxidation temperature and the retention time are shown in Table 2.
(K:유전율, tan δ: 유전손실, α: 0.1㎃에서 1㎃까지의 비선형계수)(K: dielectric constant, tan δ: dielectric loss, α: nonlinear coefficient from 0.1㎃ to 1㎃)
재산화 공정이 끝난 세라믹 시편은 연마하여 재산화 공정시 산화된 NiO층을 제거한 외부 전극을 노출시켰다.After the reoxidation process, the ceramic specimens were polished to expose the external electrode from which the oxidized NiO layer was removed during the reoxidation process.
제조가 끝난 각각의 시편에 대한 온도에 따른 특성 및 전류-전압특성은 각각 도 3 및 도 4에 나타나 있다.The temperature-dependent characteristics and the current-voltage characteristics for each prepared specimen are shown in FIGS. 3 and 4, respectively.
상술된 공정으로 모든 과정이 종료되면 최종적으로 제조된 소자를 테스트한다.When all processes are completed by the above-described process, the finally manufactured device is tested.
본 발명에 따른 소자는 상술된 내부 전극의 종류에 관계없이 평균 유전율이 10000 이상이고, 유전손실이 5% 미만인 캐패시터 특성을 나타내며, 비선형계수 10이상인 바리스터 특성을 나타낸다. 특히, 도 3에 나타난 바와 같이 -25℃ ∼ 85℃의 온도범위에서 정전 용량 변화율이 15%미만인 X7R 조성의 특성을 지님을 알 수 있다.The device according to the present invention exhibits a capacitor characteristic with an average dielectric constant of 10000 or more, a dielectric loss of less than 5%, and a varistor characteristic of a nonlinear coefficient of 10 or more, regardless of the type of the internal electrodes described above. In particular, as shown in Figure 3 it can be seen that the characteristics of the X7R composition of the capacitance change rate less than 15% in the temperature range of -25 ℃ to 85 ℃.
본 발명의 SrTiO3를 기본조성으로 하고 적층칩 형태의 바리스터-캐패시터 복합기능소자는 적층칩으로 제조하기 위하여 적정한 저온 소결제를 첨가함으로써 소결온도를 1200℃까지 낮출 수 있다. 또한, 내부 전극으로써 Ag/Pd 및 Ni 내부 전극을 사용하여 생산단가를 줄이는 효과가 있다. 특히, 본 발명에 따르면 유전율이 10000 이상이며, 유전손실이 5%미만이고, -25℃ ∼ 85℃의 온도범위에서 정전 용량 변화율이 15%미만인 X7R 조성의 캐패시터 특성을 구현함과 동시에 비선형계수가 10이상인 바리스터 특성을 나타냄으로써 복합기능 소자를 제조할 수 있다. 이러한 특성을 지닌 복합기능소자는 기존의 바리스터 및 캐패시터 소자를 대체하여 기기의 보호는 물론 전기적 특성을 향상시킬 수 있다.In the SrTiO 3 of the present invention as a basic composition, the varistor-capacitor composite functional device in the form of a laminated chip can lower the sintering temperature to 1200 ° C. by adding an appropriate low temperature sintering agent to produce a laminated chip. In addition, there is an effect of reducing the production cost by using Ag / Pd and Ni internal electrodes as the internal electrode. In particular, according to the present invention, the dielectric constant and the nonlinear coefficient of the X7R composition with the dielectric loss less than 5% and the capacitance change rate less than 15% in the temperature range of -25 ° C to 85 ° C are realized. By exhibiting varistor characteristics of 10 or more, a composite function device can be manufactured. This multifunctional device can replace the existing varistor and capacitor devices to improve the electrical properties as well as the protection of the device.
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KR100716137B1 (en) * | 2005-03-28 | 2007-05-10 | 조인셋 주식회사 | Surface mount typed chip array and Method for making the same |
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JP3265126B2 (en) * | 1994-07-20 | 2002-03-11 | 松下電器産業株式会社 | Electronic components and their manufacturing method |
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