KR20020019626A - Conditional-capture flip-flop operating at a low power consumption - Google Patents

Abstract

PURPOSE: A conditional capture flipflop for reducing power consumption is provided to minimize power consumption by preventing unnecessary discharge. CONSTITUTION: A delay/inversion portion(410) receives a clock, delays and inverts the received clock, receives the first and the second output signals from an S-R latch portion(430), and inverts the first and the second output signals. The delay/inversion portion(410) is formed with the first and the second inverters(411,412), the first NOR gate(413), and the second NOR gate(414). A differential circuit portion(400,420) is controlled by the clock and an output signal of the delay/inversion portion(410). The differential circuit portion(400,420) is used for detecting a difference between data(A) and a data bar(AB). The S-R latch portion(430) is used for latching an output signal of the differential circuit portion(400,420).

Description

Conditional-capture flip-flop operating at a low power consumption

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to a flip-flop capable of minimizing power consumption without affecting operating speed.

In general, a flip-flop is a type of register and is a semiconductor device used in an internal circuit of a semiconductor integrated device having a need for storing and outputting an input state or maintaining a state before it. There are many types of flip-flops and they must be selected to meet the needs.

Conventional flip-flops include hybrid latch flip-flops (HLFF), semi-dynamic flip-flops (SDFF), and sense amplifier-based flip-flops (SAFF). flip-flop).

The hybrid latch flip-flop is published in a paper presented at the International Solid State Circuit Conference (ISSCC) in February 1996 under the heading "Flow-Through Latch and Edge-Triggered Flip-flop Hybrid Element."

1 is a circuit diagram illustrating a conventional hybrid latch flip-flop (HLFF).

Referring to FIG. 1, a hybrid latch flip-flop HLFF receives a clock CLK as a gate terminal and a first pull-up transistor having a source-drain path formed between a power supply voltage terminal Vcc and a first node X. 100 and a delay / inverting unit 110 that receives the clock CLK and delays and inverts the signal for a predetermined time, and output signals of the clock CLK, the data D, and the delay / inverting unit 110, respectively. The first to third NMOS transistors 120, 121, and 122, which are connected to the gate terminal and connected in series between the first node X and the ground terminal GND, and the data D are received. The first precharge transistor 130 formed between the first node X and the power supply voltage terminal Vcc and the output signal of the delay / inverting unit 110 are input to the gate terminal, and the source-drain path is input to the first node. The second precharge transistor 140 formed between the X and the power supply voltage terminal Vcc and the signal of the first node An in-path is formed between the second pull-up transistor 150 and the clock CLK, the first node X, and the delay / inversion unit 110 formed between the power supply voltage terminal Vcc and the second node Y. The fourth to sixth NMOS transistors 160, 161 and 162 connected in series between the second node Y and the ground terminal GND, respectively, and the output signal of the second node It consists of a latch unit 170 for latching and outputting Q).

Referring to the operation of the hybrid latch flip-flop HLFF, when the clock CLK is logic low, the first pull-up transistor 100, the third en-MOS transistor 122, and the sixth en-MOS transistor 162 are operated. It is turned on, and the first NMOS transistor 120 and the fourth NMOS transistor 160 are turned off. As a result, the first node X is precharged to the power supply voltage level and the output signal Q has the previous data value stored in the latch unit 170.

At the rising edge of the clock CLK, the first NMOS transistor 122 and the sixth NMOS transistor 162 wait for the clock signal delayed and inverted by the delay / inversion unit 110. The transistor 120 and the fourth NMOS transistor 160 are turned on. At this time, the data D is stored in the latch unit 170 during the above period. Once the output signal of the delay / inverting unit 110 transitions from logic high to logic low, the first node X is precharged to the power supply voltage level by the second precharge transistor 140 and the data D ) Is logic low, and is precharged to the power supply voltage level by the first precharge transistor 130.

On the falling edge of the clock CLK, the first node X is fully charged to the power supply voltage level by the first pull-up transistor 100 as long as the clock CLK remains at logic low.

Second, Semi-Dynamic Flip-Flops (SDFF) are published in the 1998 Symposium on VLSI Circuit Digest of Technical Papers, entitled "Semi-Dynamic and Dynamic Flip-Flops with Embeded Logic."

2 is a circuit diagram showing a conventional semi-dynamic flip-flop (SDFF).

Referring to FIG. 2, the semi-dynamic flip-flop SDFF receives a clock CLK as a gate terminal and a precharge transistor having a source-drain path formed between the power supply voltage terminal Vcc and the first node X. 200, a delay / inverting unit 210 for receiving and delaying and inverting a signal of the clock CLK and the first node X, an output signal of the delay / inverting unit 210, data D, and The first to third NMOS transistors 220, 221, and 222 that are connected in series between the first node X and the ground terminal GND and receive the clock CLK, respectively, and the first node A first latch unit 230 for latching a signal of X), and a pull-up transistor having a source-drain path formed between a power supply voltage terminal Vcc and an output node Q when a signal of the first node is input to the gate terminal; 240 and the fourth and the fourth signals connected in series between the output node Q and the ground terminal GND, respectively, with the clock CLK and the signal of the first node X being input to the gate terminal. 5 n MOS transistors 250 and 251, and a second latch unit 260 for latching and inverting the signal of the output node Q.

Referring to the operation of the semi-dynamic flip-flop SDFF, the flip-flop enters the precharge mode at the falling edge of the clock CLK. At this time, the precharge transistor 200 which receives the clock CLK as the gate terminal is turned on to precharge the first node X to the power supply voltage level. When the first node X is precharged to a logic high, the signal of the output node Q is separated from the input terminal and continues to hold the previously latched value by the second latch unit 260. If the clock CLK is at a logic low during the precharge, the output signal of the delay / inverting section 210 is at a logic high to turn on the first NMOS transistor 220.

On the rising edge of the clock, the flip-flop enters evaluation mode. When the data D is logic low, the first node X remains logic high by the first latch unit 230. Then, the fourth and fifth NMOS transistors 250 and 251 are turned on to discharge the signal of the output node Q, to make the output node Q logic low, and to the second latch unit 260. This causes the output signal QB to be logic high. After the clock CLK rises, the output signal of the delay / inversion unit 210 goes from logic high to logic low and the first NMOS transistor 220 is turned off. When the data D is logic high, the first node X is discharged through the pull down paths of the first to third enMOS transistors 220, 221, and 222. Even if the data D drops to a logic low, the first node X continues to latch the logic low value by the first latch unit 230. Then, the pull-up transistor 240 is turned on to make the signal of the output node Q logic high.

Third, the conventional Sense Amplifier-Based Flip-Flop (SAFF) is published in a paper published at the International Solid State Circuit Conference (ISSCC) in February 1999 under the title "Sense Amplifier-Based Flip-Flop."

3 is a circuit diagram illustrating a conventional sense amplifier-based flip-flop (SAFF).

Referring to FIG. 3, the sense amplifier-based flip-flop SAFF includes a sense amplifier 300 that receives data D and DB and is controlled by a clock CLK, and an output signal of the sense amplifier 300. It is provided with a SR latch unit 310 for receiving and latching.

The sense amplifier unit 300 has a structure of a conventional sense amplifier and is composed of a plurality of PMOS transistors 301 to 304 and nMOS transistors 305 to 310. The sense amplifier unit 300 senses and amplifies the signal level difference between the data D and DB. When the clock CLK is logic low, the output node of the sense amplifier 300 is precharged to the power supply voltage level. When the clock CLK is logic high, the sense amplifier 300 is driven to receive the differential input.

The two output signals from the sense amplifier unit 300 are input to the S-R latch unit 310 and latched. The first input SB of the S-R latch unit 310 is a set input and the second input RB is a reset input. Due to the characteristics of the output signal of the differential amplifier constituting the sense amplifier unit 300, the case where both the first input SB and the second input RB are logic low is not allowed. If the first input SB is logic low, the first output signal Q of the SR latch unit 310 is set to a logic high, and if the second input RB is logic low, the second of the SR latch unit 310 is The output signal QB is set to logic high.

The above mentioned hybrid latch flip-flop (HLFF), semi-dynamic flip-flop (SDFF) and sense amplifier-based flip-flop (SAFF) are transmission gate master-slave flip-flops (TGFF) in terms of operating speed. Better than flip-flops such as flip-flop. On the other hand, since the internal nodes are precharged and discharged every clock cycle, there is a problem of causing unnecessary power consumption.

The present invention has been made to solve the above problems of the prior art, an object of the present invention to provide a flip-flop that can minimize the power consumption by preventing unnecessary discharge without affecting the operation speed.

1 is a circuit diagram showing a basic circuit of the hybrid latch flip-flop of the prior art;

2 is a circuit diagram showing a detailed circuit of the semi-dynamic flip-flop of the prior art;

3 is a detailed circuit diagram of the sense amplifier-based flip-flop of the prior art;

4 is a detailed circuit diagram illustrating a Conditional-Capture Flip-Flop of the present invention;

5 is a circuit diagram of a single-ended version showing another embodiment of the present invention;

6A is a timing diagram showing waveforms simulated with respect to the flip-flop of FIG. 4;

6B is a timing diagram showing waveforms simulated with respect to the flip-flop of FIG. 5;

7 is a view comparing power consumption according to a data pattern between a flip-flop (CCFF) and a prior art sense amplifier-based flip-flop (SAFF) of the present invention;

8 shows a flip-flop (CCFF) of the present invention and a hybrid latch flip-flop (HLFF), a semi-dynamic flip-flop (SDFF), and a transmission gate master-slave flip-flop (TGFF) of the prior art. Power consumption according to the data pattern)

Fig. 9 is a diagram comparing power consumption when a counter using a flip-flop (CCFF) of the present invention and a counter using a flip-flop (SAFF) of the prior art are driven.

* Description of the symbols for the main parts of the drawings *

400, 420: differential circuit portion

410 delay / invert

420: S-R latch part

In order to achieve the above object, the flip-flop of the present invention is a flip-flop of a semiconductor integrated circuit, comprising: delay / inverting means for receiving a clock to delay / invert and receiving and inverting first and second output signals; Differential circuit means which is controlled by an output signal of the clock and the delay / inverting means and detects and amplifies a signal level difference between the positive data and the negative data signals; And S-R latch means for receiving and latching an output signal of the differential circuit means and outputting the first and second output signals.

In addition, a flip-flop of the present invention is a flip-flop of a semiconductor integrated circuit, comprising: a PMOS transistor having a clock input to a gate terminal and a source-drain path formed between a power supply voltage terminal and a precharge node; Delay / inverting means for receiving a clock and delaying the signal and inverting the signal of the output node; First to third enMOS transistors each of which receives the clock, data, and output signals of the delay / inverting means through a gate terminal and is connected in series between the precharge node and a ground terminal; A first precharge transistor having the data input to a gate terminal and a source-drain path formed between a power supply voltage terminal and the precharge node; A second precharge transistor having an output signal of the delay / inverting means input to a gate terminal, and a source-drain path formed between a power supply voltage terminal and the precharge node; A pull-up transistor receiving the signal of the precharge node as a gate terminal and having a source-drain path formed between a power supply voltage terminal and an output node; An inverter receiving the data; Fourth to sixth enMOS transistors each of which receives the clock, an output signal of the inverter, and an output signal of the delay / inverting means and is connected in series between the output node and a ground terminal; And a latch unit configured to receive a signal of the output node and latch and invert the signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4 is a circuit diagram illustrating a differential version of a conditional-capture flip-flop (CCFF) according to the present invention.

Referring to FIG. 4, the conditional-captured flip-flop CCFF according to the present invention receives and delays / inverts a clock CLK, and outputs the first and second output signals Q and QB of the SR latch unit 430. ) Is controlled by the delay / inverting unit 410 and the output signal of the clock CLK and the delay / inverting unit 410, and receives the data A and the data bar AB to detect a difference. The differential circuit unit 400 and 420 in operation, and the SR latch unit 430 for receiving and latching the output signals of the differential circuit unit 400 and 420 are provided.

In detail, the delay / inverting unit 410 may include first and second inverters 411 and 412 for delaying the clock CLK, and output signals of the second inverter 412 and the SR latch unit 430. The first NOR gate 413 receiving the first output signal Q, the second NOA gate receiving the output signal of the second inverter 412 and the second output signal QB of the SR latch unit 430. 414.

In detail, the differential circuit unit 400 receives the clock CLK as the gate terminal and the first precharge transistor 401 having a source-drain path formed between the power supply voltage terminal Vcc and the first output node SB. The first and second NMOS transistors 402 connected to the output terminal and the data A of the delay / inverting unit 410 through a gate terminal, respectively, and connected in series between the first output node SB and the common node NC. , 403, a first latch unit 404 for inverting and latching the first output node SB to generate a first final output signal S, and a clock CLK as a gate and receiving a source-drain path. Consists of a third NMOS transistor 409 formed between the common node NC and the ground terminal GND.

The differential circuit unit 420 receives the clock CLK as a gate terminal, and a second precharge transistor 405 having a source-drain path formed between the power supply voltage terminal Vcc and the second output node RB, and delay / Fourth and fifth enMOS transistors 406 and 407 that receive the output signal of the inverting unit 410 and the data bar AB through the gate terminal, respectively, and are connected in series between the second output node RB and the common node NC. And a second latch unit 408 which inverts and latches the second output node RB to generate a second final output signal R.

The SR latch unit 430 receives a signal of the first output node SB as a gate terminal, and has a first source-drain path formed between the power supply voltage terminal Vcc and the first node Q, which is its output node. The first MOS transistor 422 having the PMOS transistor 421 and the second final output signal R input to the gate terminal, and having a source-drain path formed between the first node Q and the ground terminal GND. And a second PMOS transistor 423 having a first node Q as a gate terminal and having a source-drain path formed between the first output node SB and the second node QB which is its output node. A second NMOS transistor 424 having a source-drain path formed between the second final output signal R and the second node QB and receiving a signal of the first node Q at a gate end thereof; A third PMOS transistor 425 having a signal of the node QB input to the gate terminal and having a source-drain path formed between the second output node RB and the first node Q; And a third NMOS transistor 426 having a source-drain path formed between the first final output node S and the first node Q and receiving a signal of the second node QB at the gate end thereof, and the second node QB. The fourth PMOS transistor 427 and the first final output node, in which a signal of the output node RB is input to the gate terminal and a source-drain path is formed between the power supply voltage terminal Vcc and the second node QB. The signal of S) is input to the gate terminal and includes a fourth NMOS transistor 428 having a source-drain path formed between the second node QB and the ground terminal GND.

The S-R latch unit 420 performs a high speed operation as a normal cross connection circuit.

Referring to the operation, when the clock CLK is logic low, the set bar signal SB, which is a signal of the first output node SB, and the reset bar signal RB, which is a signal of the second output node, are connected to the differential circuit unit 400. Transition from logic low to logic high by the first and second precharge transistors 401 and 405 is disabled and the SR latch unit 430 is disabled. When the first and second signals Q and QB are logic low and logic high, respectively, the second PMOS transistor 423 and the third NMOS transistor 426 of the SR latch unit 430 are turned on and output states. Preserve it. In addition, the first and second signals Q and QB may pass through the first and second MOS transistors 402 of the differential circuit unit 400 through the first and second NOR gates 413 and 414 of the delay / inverting unit 410. The fourth NMOS transistor 406 of the differential circuit unit 420 is turned on. Looking at the flip-flop operation after the clock CLK rises, the operation is determined according to the state of the input data A and the data bar AB.

When the data A is logic high, the set bar signal SB is pulled down, and the first PMOS transistor 421 and the fourth enMOS transistor 428 of the SR latch unit 430 are activated. Switch the output state. During this time, the second PMOS transistor 423 and the third NMOS transistor 426 of the SR latch unit 420 are turned off and do not cause signal fighting between the signal values of the previous state and the current state. Do not. When the input of the data A is logic low, the reset bar signal RB is not pulled down because the third NMOS transistor 406 of the differential circuit unit 400 is turned off. This is because the output has the same value as the data A value already input. When the clock CLK transitions from logic high to logic low, the setbar signal SB is precharged if it is discharged. The output signals of the first and second inverters 411 and 412 of the delay / inverting unit 410 are based on the pull-down output values of the first and second enMOS transistors 402 and fourth enMOS transistors 406 of the differential circuit unit 400. Turn on).

As described above, when both the first output signal Q and the input data A signal of the SR latch unit 430 are logic high, the flip-flop is turned off by turning off the first NMOS transistor 402. Does not discharge and remains in its original state. When both the first output signal Q and the input data A signal are logic low, unnecessary discharge is prevented by turning off the second NMOS transistor 403.

FIG. 5 is a circuit diagram illustrating a single-ended version of a conditioning-capture flip-flop (CCFF), representing another embodiment of the invention.

Referring to FIG. 5, the single-ended version of the flip-flop of the conditioning-capture flip-flop (CCFF) has a clock CLK input to the gate terminal, and the source-drain path has a power supply voltage terminal Vcc and a precharge node. A PMOS transistor 500 formed between (X), a delay / inverting unit 540 which receives and delays the clock CLK and inverts the output signal Q, a clock CLK, and data D ) And the first to third NMOS transistors 510 which receive the output signal NB of the delay / inverting unit 540 to the gate terminal and are connected in series between the precharge node X and the ground terminal GND. 511 and 512 and a first precharge transistor 530 having data D input to a gate terminal and a source-drain path formed between the power supply voltage terminal Vcc and the precharge node X, and delay / half. The output signal CKDB of the whole 540 is input to the gate terminal, and a source-drain path is connected between the power supply voltage terminal Vcc and the precharge node X. The pull-up transistor 560 having the second precharge transistor 550 and the signal of the precharge node X supplied to the gate terminal, and having a source-drain path formed between the power supply voltage terminal Vcc and the output node Q. In addition, the inverter 520 receiving the data D, the clock CLK, the output signal of the inverter 520, and the output signal of the delay / inverting unit 540 are respectively input to the gate terminal and output node Q. ) And the fourth to sixth n-MOS transistors 570, 571, and 572 connected in series between the ground terminal GND and a latch unit 580 for receiving and latching and inverting a signal of the output node Q. .

Referring to FIG. 5, the operation of the single-ended version of the conditioning-capture flip-flop (CCFF) will be described. The delay / inverting unit 540 is a delay / inverting unit of the flip-flop of FIG. Used for the same purpose as 410. The precharge node X is discharged on the rising edge of the clock when the signal of the output node Q is logic low and the data D is logic high.

When the clock CLK is logic low, the logic high is maintained because the second and third enMOS transistors 511 and 512 are prevented from discharging the precharge node X. When the data D is logic low, the fifth NMOS transistor 571 is turned on and the signal of the output node Q is maintained in the current state or pulled down to the ground level. Once the signal input from the delay / inverting unit 540 to the third NMOS transistor 510 is logic low, the precharge node X is separated from the data D. When the signal input from the delay / inverting section 540 to the sixth NMOS transistor 572 is a logic low, the output node Q also operates separately from the data D. The precharge node X is precharged to the power supply voltage level as long as the clock CLK maintains a logic low level from the falling edge of the clock CLK.

FIG. 6A is a timing diagram showing waveforms of simulation results of the flip flops of FIG. 4 for each signal, and FIG. 6B is a timing diagram showing waveforms simulated for the flip flops of FIG.

The simulated waveforms of the flip-flop shown in FIGS. 6A and 6B are obtained using 0.35um CMOS technology in a typical device using a power supply of 2.5V, a temperature of 25 degrees Celsius, and an output load of 400fF. Obtained.

FIG. 7 is a diagram comparing power consumption according to a data pattern between a conditional-captured flip-flop (CCFF) and a conventional sense amplifier-based flip-flop (SAFF).

Referring to FIG. 7, the conditional-capture flip-flop (CCFF) of the present invention is compared to the conventional sense amplifier-based flip-flop (SAFF) when there is no change of adjacent data, such as the data pattern of (11001100). The power saving effect is about 20%, and when there is no data change every clock like the data pattern of 11111111, it can be seen that the power saving effect is about 60%.

8 illustrates a conventional flip-flop (CCFF), a conventional hybrid latch flip-flop (HLFF), a semi-dynamic flip-flop (SDFF), and a very low power consumption transmission gate master-slave flip-flop (TGFF). The figure compares power consumption according to data patterns with master-slave flip-flop.

Referring to FIG. 8, the conditional-captured flip-flop (CCFF) of the present invention saves more power than other flip-flops when not only there is a change in data in the data pattern but also there is no change in data every clock. It can be seen that the effect is excellent.

FIG. 9 is a diagram comparing power consumption when the counter is implemented using the conditional-capture flip-flop (CCFF) and the conventional sense amplifier-based flip-flop (SAFF). In the drawing, " FLIP-FLOP " represents power consumed inside the counter, " CLOCK " represents power consumed when the clock is toggled, and " GATE " The power consumed by logic gates such as the AND gate and the NOA gate is shown, respectively.

Referring to Fig. 9, the counter using the conditional-captured flip-flop (CCFF) of the present invention and the counter using the conventional sense amplifier-based flip-flop (SAFF) are divided into "CLOCK" power consumption and "GATE" power consumption. There is no big difference, but when comparing the power consumed inside the counter, it can be seen that the power of about 51% is reduced. Overall, the counter using the conditional-capture flip flip (CCFF) according to the present invention can reduce the power consumption by about 30% compared to the conventional method.

FIG. 10 is a setup time and a hold time for comparing the operating speeds of the conventional sense amplifier-based flip-flop (SAFF) and the conditional-capture flip-flop (CCFF) of the present invention. This is a table comparing. As can be seen from the diagram, it can be seen that the operating speed of the conditional-captured flip-flop (CCFF) of the present invention also does not decrease compared to the conventional flip-flop.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention has an effect of reducing power consumption by preventing unnecessary discharge when the previous state and the input data state are the same by using the delay / inversion part while using the differential input.

Claims (6)

In flip-flops of semiconductor integrated circuits, Delay / inverting means for receiving a clock to delay / inverting and receiving and inverting the first and second output signals; Differential circuit means which is controlled by an output signal of the clock and the delay / inverting means and detects and amplifies a signal level difference between a positive data signal and a negative data signal; And S-R latch means for receiving and latching an output signal of the differential circuit means and outputting the first and second output signals Flip-flop made of The method of claim 1, The delay / inversion means, First and second inverters configured to receive and delay the clock; A first NOR gate receiving an output signal of the second inverter and a first output signal from the S-R latch means; And A second NOR gate receiving an output signal of the second inverter and a second output signal of the S-R latching means; Flip-flop, characterized in that consisting of. The method of claim 1, The differential circuit means, A first precharge transistor having the clock input to a gate terminal and a source-drain path formed between a power supply voltage terminal and a first output node; First and second enMOS transistors each having an output signal and data of the delay / inverting means input to a gate terminal and connected in series between the first output node and the common node; A first latch unit for inverting and latching a signal of the first output node to generate a first final output signal; A second precharge transistor having the clock input to a gate terminal and a source-drain path formed between a power supply voltage terminal and a second output node; Third and fourth NMOS transistors receiving the output signal and the sub data signal of the delay / inverting means through a gate terminal and connected in series between the second output node and the common node; A second latch unit for inverting and latching a signal of the second output node to generate a second final output signal; And A fifth NMOS transistor having the clock input to a gate terminal and a source-drain path formed between the common node and a ground terminal Flip-flop, characterized in that consisting of. The method according to claim 1 or 3, The S-R latch unit, A first PMOS transistor receiving a signal of the first output node through a gate terminal and having a source-drain path formed between a power supply voltage terminal and a first node which is an output node thereof; A first NMOS transistor receiving the second final output signal as a gate terminal and a source-drain path formed between the first node and a ground terminal; A second PMOS transistor receiving a signal of the first node through a gate terminal and having a source-drain path formed between the first output node and a second node whose output node is a second node; A second NMOS transistor receiving a signal of the first node through a gate terminal and a source-drain path formed between the second final output signal and the second node; A third PMOS transistor receiving a signal of the second node through a gate terminal and having a source-drain path formed between the second output node and the first node; A third NMOS transistor receiving a signal of the second node through a gate terminal and having a source-drain path formed between the first final output node and the first node; A fourth PMOS transistor receiving a signal of the second output node through a gate terminal and a source-drain path formed between a power supply voltage terminal and the second node; And A fourth NMOS transistor receiving a signal of the first final output node through a gate terminal and a source-drain path formed between the second node and a ground terminal Flip-flop, characterized in that consisting of. In flip-flops of semiconductor integrated circuits, A PMOS transistor having a clock input to a gate terminal and a source-drain path formed between a power supply voltage terminal and a precharge node; Delay / inverting means for receiving a clock and delaying the signal and inverting the signal of the output node; First to third enMOS transistors each of which receives the clock, data, and output signals of the delay / inverting means through a gate terminal and is connected in series between the precharge node and a ground terminal; A first precharge transistor having the data input to a gate terminal and a source-drain path formed between a power supply voltage terminal and the precharge node; A second precharge transistor having an output signal of the delay / inverting means input to a gate terminal, and a source-drain path formed between a power supply voltage terminal and the precharge node; A pull-up transistor receiving the signal of the precharge node as a gate terminal and having a source-drain path formed between a power supply voltage terminal and an output node; An inverter receiving the data; Fourth to sixth enMOS transistors each of which receives the clock, an output signal of the inverter, and an output signal of the delay / inverting means and is connected in series between the output node and a ground terminal; And A latch unit for latching and inverting the signal of the output node Flip-flop made including. The method of claim 5, The delay / inversion means, First and second inverters configured to receive and delay the clock; A first NOR gate receiving an output signal of the second inverter and a first output signal from the S-R latch means; And A third inverter for inverting the output signal of the second inverter Flip-flop, characterized in that consisting of.