KR20020018902A - driving method for plasma display panel - Google Patents

Abstract

PURPOSE: A method is provided to minimize voltage drop owing to a loading effect by sufficiently lowering a component of displacement current required at discharging. CONSTITUTION: If a sustain discharge period comes, a common driver control part controls an X common driver and a Y common driver in turn and applies sustain pulses to each of X and Y sustain electrodes in turn. A rising pulse of each sustain pulse is increased from a zero voltage to the first voltage(V1) in proportion to a time between t1 and t2, and instantly from the second voltage(V2) from the first voltage(V1) at a time(t2). A falling pulse of each sustain pulse is decreased from a zero voltage to the first voltage(-V1) in proportion to a time between t3 and t4, and instantly from the second voltage(-V2) from the first voltage(-V1) at a time(t4).

Description

Driving method for plasma display panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method of driving a plasma display panel to minimize a voltage drop due to a loading effect during maintenance discharge, thereby improving the characteristics of the maintenance discharge.

Recently, various problems about the function of the CRT (Cathode Ray Tube) have been raised, and various kinds of display apparatuses capable of overcoming the disadvantages of the CRT have been developed. Among such display devices, interest in PDP is increasing especially because PDP has an excellent advantage of displaying a large screen more clearly than the existing CRT. PDP according to the prior art is described in US Patent No. 6078139 "Front panel for plasma display", US Patent No. 6075319 "Plasma display panel device and method of manufacturing the same (Plasma display panel device and method) for fabricating the same ", US Patent No. 6069446" Plasma display panel with ring-shaped loop electrodes, US Patent No. 6066917 "Plasma display panel ), US Patent Publication No. 6034656, "Plasma display panel and method of controlling brightness of the same." In addition, various driving methods of the PDP are described in US Patent Publication No. 6054970, "Method for driving an AC-driven PDP, US Patent Publication No. 5952986", and a display apparatus (Driving). method of an AC-type PDP and the display device ".

In general, the PDP is composed of a combination of front and rear base plates that are integrally sealed and coupled to each other, and in this case, a plurality of X and Y sustain electrodes are formed in a stripe shape on one surface of the front base plate. Similarly, a plurality of address electrodes are arranged on one surface of the rear base plate to form individual ends of a stripe shape. The X and Y sustain electrodes and the address electrodes receive a predetermined voltage pulse from the control circuit block, thereby rapidly discharging the gas sealed between the front base plate and the rear base plate.

On the other hand, various researches for smoothly driving the conventional PDP have been actively conducted, and a PDP driving method called an address and display period separated method (hereinafter, referred to as an "ADS" method) has recently been introduced. I am in the limelight. In the case of this ADS method, since the display period and the address period are strictly separated, when this ADS method is actually applied to the driving of the PDP, the production line can obtain the advantage of driving the multi-gradation of 256 or more gradations at high speed. have. Generally, in the conventional ADS system, a time for displaying and maintaining one image on the entire screen, that is, a frame is divided into several sub-fields, and each sub-field is reset ( The drive is divided into a reset period, an address discharge period, a sustain discharge period, and an erase period.

According to this conventional ADS method, when the above-mentioned erasing period arrives, the control circuit block maintains a separate discharge erasing pulse having a long rising time of, for example, 100ms, and having a wide width, for example, Y. By applying to the electrode, the wall charges of the specific display cells during the sustain discharge are lowered to a value similar to the wall charges of the other display cells without the sustain discharge. In this case, the wall charges of all the display cells are made uniform, so that each display cell can be more stably performed with the address discharge proceeding later.

However, PDPs mostly use square waves as driving pulses. When using these square waves, the peak power supply capacity that can be supplied from the power source must be very high. However, since the power consumption from the power supply has a certain limitation, the power supply does not sufficiently follow the discharge of the PDP cell, causing a problem of voltage drop due to the loading effect at the output of the voltage. This is because the rise time of the sustain discharge pulse is so fast that the sum of the discharge current component and the displacement current component exceeds the power supply capability of the power source. This voltage drop can lead to instability in sustain discharge and prevent the formation of proper wall charge in each cell.

Accordingly, an object of the present invention is to provide a driving method to minimize the voltage drop due to the loading effect by sufficiently lowering the component of the displacement current required by the power supply during discharge.

Another object of the present invention is to provide a driving method for improving the discharge characteristics in sustain discharge.

It is still another object of the present invention to provide a driving method for preventing damage to a driving circuit caused by a large peak current.

1 is a block diagram showing a general plasma display panel.

FIG. 2 is a detailed block diagram illustrating the control circuit block of FIG. 1. FIG.

3 is a driving waveform timing diagram of a plasma display panel according to the present invention;

Figure 4 is an exemplary waveform diagram showing a sustain discharge pulse according to the present invention.

Figure 5 is another exemplary waveform diagram showing a sustain discharge pulse according to the present invention

Figure 6 is another exemplary waveform diagram showing a sustain discharge pulse according to the present invention.

The present invention for achieving the above object

A driving method of a plasma display panel in which a reset period, an address discharge period, and a sustain discharge period are sequentially performed,

It characterized in that to minimize the voltage drop due to the loading effect during the discharge by applying a sustain discharge pulse variable voltage in proportion to the time at least once in the sustain discharge period.

Preferably, the sustain discharge pulse may be increased in proportion to time until the first voltage, and then may be instantaneously increased from the first voltage to a second voltage which is the sustain discharge pulse voltage. The first voltage may be limited to a voltage of 120V or less to prevent the discharge current from flowing.

In addition, the sustain discharge pulse is instantaneously raised to the first voltage, and the voltage is increased in proportion to time from the first voltage to the second voltage and then applied in the form of rising immediately to the third voltage which is the sustain discharge pulse voltage from the second voltage. can do.

Therefore, the present invention can minimize the effect of voltage drop and further improve the sustain discharge characteristics by deforming the sustain discharge pulse to sufficiently reduce the displacement current component. In addition, it is possible to prevent damage of the driving circuit due to the instantaneous peak current.

Hereinafter, a method of driving a PDP according to the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1, the PDP 50 for implementing the present invention, for example, an indirect discharge type PDP, consists of a combination of a front substrate unit 10 and a rear substrate unit 30 facing each other. A series of seal lines (not shown) are formed outside the front substrate unit 10 and the rear substrate unit 30, so that the front substrate unit 10 and the rear substrate unit 30 are sealed in a smooth state. To keep them on track. A discharge gas, for example, a penning gas, is accommodated between the front substrate unit 10 and the rear substrate unit 30 sealed by the seal line. The phenning gas has a configuration in which argon (Ar), xenon (Xe), and the like are mixed with neon gas, and have a characteristic of easily discharging even at a low voltage.

The front substrate unit 10 is, for example, indium tin oxide (ITO) formed in pairs with each other on one surface of the front base plate 11 made of glass and on the rear substrate unit 30 side of the front base plate 11. The material is made of a combination of the X and Y sustain electrodes 12 and 14 and the front dielectric layer 13. In this case, the X and Y sustain electrodes 12 and 14 are spaced apart from each other by a front end of the front base plate 11 facing the rear substrate unit 30 to form a continuous structure in parallel. The front dielectric layer 13 has a structure in which a front surface of the front base plate 11 is coated with a predetermined thickness so that the front X and Y sustain electrodes 12 and 14 are covered.

At this time, the X sustain electrodes 12 receive a write pulse, a sustain pulse, and the like from the control circuit block 100, and then use the write pulse, the sustain pulse, and the like to separate the individual display cells 36 to be described later. It plays a role of generating wall charge therein and also maintains a discharge state of the discharge gas contained in the individual display cells 36. In addition, the Y sustain electrodes 14 receive scan pulses, sustain pulses, and the like from the control circuit block 100, and then use the scan pulses, the sustain pulses, and the like, and output image data to individual display cells 36. In addition to scanning and similarly to the aforementioned X sustaining electrodes 12, the display device serves to continuously maintain the discharge state of the discharge gas contained in the individual display cells 36.

At this time, a protective film layer (not shown), for example, an MgO layer is further disposed on the outermost surface of the front dielectric layer 13, and the protective film layer serves to improve the discharge characteristics of the front dielectric layer 13 described above.

Meanwhile, the rear board unit 30 corresponding to the front board unit 10 mentioned above is similar to the front board unit 10 of the front, for example, the rear base plate 31 made of glass, and the rear base plate. And a combination of the address electrodes 32 and the rear dielectric layer 33 formed on the upper side of the front base plate 11.

The address electrodes 32 are arranged on one surface of the rear base plate 31 facing the front base plate 11 in a state perpendicular to the arrangement direction of the X and Y sustain electrodes 12 and 14 described above. Spaced apart from each other in a shape to form a continuous structure in parallel, the rear dielectric layer 33 forms a structure that is applied to one surface of the rear base plate 31 so as to cover the address electrodes 32. In this case, the address electrodes 32 serve to selectively designate the individual display cells 38 to be subjected to the actual display discharge by receiving, for example, an address pulse from the control circuit block 100. Here, a plurality of partition walls 34 are erected on one surface of the rear dielectric layer 33 and arranged in a line. These barrier ribs 34 are formed of the front substrate unit 10 and the rear substrate unit 30, if the aforementioned front substrate unit 10 and rear substrate unit 30 are integrally sealed by seal lines. By partitioning the interface space therebetween to a certain size, the plurality of display cells 36 corresponding to the above-described X and Y sustain electrodes 12 and 14 between the front substrate unit 10 and the rear substrate unit 30. ) Are defined individually. In this case, the above-described discharge gas is accommodated in the individual display cells 36.

In this case, R, G, and B phosphors 35 are further coated inside the individual display cells 36 covering the inner surfaces of the partition walls 34, and the R, G, and B phosphors 35 are described above. When the discharge gas contained in each of the display cells 38 is discharged by driving one of the X and Y sustain electrodes 12 and 14 and the address electrodes 32, the ultraviolet rays of a predetermined size are emitted. By colliding with the ultraviolet rays, R, G, and B colors serve to induce light to be emitted toward the front substrate unit 10, for example. Here, the R, G, and B phosphors 35 are continuously arranged in the color order of, for example, "RGB, RGB, ...." along the transverse direction of each of the individual display cells 36. When the B phosphor 35 emits ultraviolet rays by the above-described discharge process of the discharge gas, the B phosphor 35 collides with the ultraviolet rays so that the R, G, and B colors of light are discharged to the front substrate unit 10. ) Will emit light. The color arrangement of the R, G and B phosphors 35 may be variously modified according to the situation of the production line.

In this case, when the front dielectric layer 13 is discharged in each of the display cells 36 to generate a plurality of discharge ions, each of the X and Y sustain electrodes 12 and 14 is discharged. Similarly, the rear dielectric layer 33 discharges each of the display cells 36 to generate a plurality of discharge ions, and thus, each of the address electrodes 32 is discharged. Play a role in protecting them.

Meanwhile, as shown in FIG. 2, the aforementioned control circuit block includes the address driver 101, the X common driver 103, the Y scan driver 102, the Y common driver 104, and the control unit 109. In combination.

Here, the address driver 101 is configured to input an address pulse to the address electrodes 32 while being electrically connected to the address electrodes 32. The X common driver 103 ) Serves to input a write pulse and a sustain pulse to the X sustain electrodes 12 while being electrically connected to the X sustain electrodes 12.

In addition, the Y scan driver 102 serves to input a scan pulse to the Y sustain electrodes 14 while the Y scan electrodes 102 are electrically connected to the Y sustain electrodes 14. 104 serves to input a sustain pulse to the Y sustain electrodes 14 while being electrically connected to the Y sustain electrodes 14 via the Y scan driver 102. In this case, the aforementioned Y scan driver 102 is not only electrically connected to the Y sustain electrodes 14 but also forms an electrical connection relationship with the auxiliary scan electrodes 60 forming the gist of the present invention. For example, a scan pulse is input to the scan electrodes 60.

On the other hand, the preceding control unit 109 is electrically connected to the address driver 101, the X and Y common drivers 103 and 104, and the Y scan driver 102, from an external electric device such as a computer (not shown). The address driver 101, the X and Y common drivers 103 and 104, and the Y scan driver 102 are simultaneously controlled by a series of input clock signals, display data signals, and horizontal and vertical signals.

In this case, the control unit 109 is dedicated to the display data control unit 105 which exclusively controls the address driver 101, the Y scan driver 102, the X common driver 103, and the Y common driver 104. It consists of a combination of the panel drive control unit 106 to control, in this case, the panel drive control unit 106 is a scan driver control unit 107 and X common driver 103, Y dedicated to control the Y scan driver 102 It consists of a combination of the common driver control unit 108 which exclusively controls the common driver 104.

On the other hand, as mentioned above, the PDP 50 of the present invention has a plurality of display cells at the intersections of the X and Y sustain electrodes 12 and 14 and the address electrodes 32 respectively formed in directions perpendicular to each other. (36) For example, in a state where the display cell 36a is provided, a series of electrical connections are formed with the above-described control circuit block, thereby quickly displaying a series of image information.

At this time, in the present invention, each display cell 36 emits light once and is maintained, that is, the frame is divided into a plurality of subfields, and each subfield is divided into a reset period, an address discharge period, and a sustain discharge period. After dividing again, the reset period, the address discharge period, and the sustain discharge period are repeated at predetermined cycles to proceed to selectively adjust the light emission states of the display cells 36.

First, when the reset period arrives, the common driver control unit 108 controls the X common driver 103 to input the full screen write pulse P1 at the time T1 to T2 as shown in FIG. The display cells 36 are turned on. Subsequently, the common driver control unit 108 controls the Y common driver 104 to turn off all display cells 36 by inputting the full-screen erase pulse P2 at the time points T3 to T4. By this on / off process, all the display cells 36 of the PDP 50 are maintained in an initializing state as a whole.

Next, when the address discharge period arrives, the scan driver control unit 107 controls the Y scan driver 102 so that the Y sustain electrodes 14 corresponding to the first line among the display lines of the PDP 50 can be controlled. Apply scan pulse P4. In addition, the display data control unit 105 controls the address driver 101 so that the specific display cells 36, e.g., required by the sustain discharge, of all the address electrodes 32 located on the first first line are controlled. The address pulse P5 is applied to the address electrodes 32 corresponding to the display cells 36a.

In this case, so-called address discharge occurs between the Y sustain electrodes 14 located on the first line and the specific address electrodes 32, and thus, display cells located on the first first line. The wall charges of a predetermined size are generated on the surfaces of the specific display cells 36 of 36. The wall charge generation process is sequentially performed on all display lines in the order of the Y sustain electrodes 14 located on the second line and the Y sustain electrodes 14 located on the second line. Proceed. At this time, the common driver control unit 108 controls the X common driver 103 and inputs the X sustain electrodes 12 to the X sustain electrodes 12, for example, the Shelf pulse P3, so that the X sustain electrodes are electrically stable. Keep it going.

On the other hand, when the above-described series of wall charge formation processes proceed, the trace electrons in the discharge gas are rapidly accelerated, and these electrons strongly collide with the neutral particles included in the discharge gas, thereby causing each neutral particle to be separated from the electrons. Ionize with discharge ion. At this time, the ionized electrons are accelerated once again by the previous electric field to participate in collision with the neutral particles, and as a result, the discharge gas contained in the selected specific display cells 36 changes into a plasma state. Done. As described above, when the discharge gas is converted into plasma, at the same time, a certain amount of ultraviolet light is generated from the discharge gas, and the ultraviolet light collides with the R, G, and B phosphors 37 applied inside the display cells 38. For example, light of R color can be quickly emitted to the display surface of the PDP 50.

Thereafter, when the sustain discharge period arrives, the common driver control unit 108 alternately controls the X common driver 103 and the Y common driver 104, such that the X sustain electrodes 12 and the Y sustain electrodes 14 are disposed. For example, alternately apply sustain pulses P6, P7, and P9 for positive potential having a magnitude of about 180V. Here, the rising portions A, B, and C of the rising pulses of the sustain discharge pulses P6, P7, and P9 are shown as a square wave like instantaneous rise without time delay as in the prior art, but in reality, as shown in FIG. After rising from the voltage of zero to the first voltage V1 in proportion to the time between t2, the voltage rises from the first voltage V1 to the second voltage V2 which is the sustain discharge pulse voltage at the time point t2. Therefore, almost all of the charging may occur at a time between the times t1 and t2. In addition, the dropping portions D, E, and F of the dropping pulses of the sustain discharge pulses P6, P7, and P9 are shown as if they fall instantaneously without time delay as in the prior art, but in reality, as shown in FIG. After dropping from the voltage of 0 to the first voltage -V1 in proportion to time, the voltage drops immediately from the first voltage -V1 to the second voltage -V2 at the time point t4.

Therefore, since the rise time of the sustain discharge pulse is considerably slower than in the prior art, the displacement current component decreases as much as possible from the first voltage V1 to the second voltage V2, and as a result, the sum of the displacement current component and the discharge current component is Since the power supply capacity of the power supply is not exceeded, the power supply can sufficiently follow the discharge of the cell, and the problem of voltage drop due to the loading effect at the output terminal of the voltage can be solved. This ensures stability in discharge and makes it possible to form an appropriate wall charge in each cell. Here, it is preferable that the first voltage V1 has a value between about 0V and 120V and has a value and a slope at which the discharge current does not flow.

Of course, the waveform of the sustain discharge pulse of Figure 4 may be modified as shown in FIG. That is, as shown in FIG. 5, the rising pulse of the sustain discharge pulse instantaneously rises from the voltage of zero at the time t1 to the first voltage V3 and is proportional to the time between the times t1 and t2 and the second voltage at the first voltage V3. After rising to V1, it instantaneously rises from the 2nd voltage V2 to the 3rd voltage V2 which is a sustain discharge pulse voltage at time t2. In addition, the drop pulse of the sustain discharge pulse instantaneously drops from the voltage of 0 at the time point t3 to the first voltage -V3, and then drops from the first voltage -V3 to the second voltage -V1 in proportion to the time between the time points t3 and t4. At t4, the voltage drops immediately from the second voltage -V1 to the third voltage -V2, which is the sustain discharge pulse voltage. In addition, since the frequency of the sustain discharge pulse can be increased by applying the voltage difference between the first voltage V3 and the second voltage V1 to a voltage within a range where self-erasing does not occur, the luminance can be increased. In particular, the slope of the voltage difference between the first voltage V3 and the second voltage V1 may be formed in one step or in several steps as shown in the drawing.

6, the rising pulse of the sustain discharge pulse rises from the voltage of 0 to the first voltage V1 in proportion to the time between the time points t1 and t2, and is the sustain discharge pulse voltage at the first voltage V1 at the time point t2. The voltage rises momentarily to the second voltage V2. In addition, the falling pulse of the sustain discharge pulse drops in proportion to the time between the time points t4 and t5 and falls from the voltage of zero to the first voltage V1 and at the point in time t5 from the first voltage -V1 to the sustain discharge pulse voltage -V2. As a result, the frequency of the applied voltage can be increased, so that the luminance can be increased.

Therefore, according to the present invention, so-called sustain discharge occurs whenever the voltage is changed between the X sustain electrodes 12 and the Y sustain electrodes 14 by using the sustain discharge pulses shown in FIGS. 4, 5, and 6. In this case, the R, G, and B phosphors 37 may maintain the previous emission state by the ultraviolet rays generated at this time.

Furthermore, the present invention can minimize the voltage drop by minimizing the displacement current during discharge, thereby improving the sustain discharge characteristics. In addition, damage to the driving circuit due to a large instantaneous peak current can be prevented.

As described in detail above, in the driving method of the PDP according to the present invention, a sustain discharge pulse is applied by varying the voltage in proportion to a time at least once during discharge to have only a displacement current until discharge.

Therefore, the present invention can achieve stable sustain discharge characteristics by minimizing a voltage drop generated due to the loading effect of applying a sustain discharge pulse during sustain discharge, and can form an appropriate wall charge in each cell. In addition, since the frequency of the applied voltage can be increased, the luminance can be increased. In addition, damage to the driving circuit due to a large instantaneous peak current can be prevented.

On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be made without departing from the spirit of the invention. .

Claims (4)

A driving method of a plasma display panel in which a reset period, an address discharge period, and a sustain discharge period are sequentially performed, And a sustain discharge pulse whose voltage is changed in proportion to the time at least once in the sustain discharge period. The plasma display panel of claim 1, wherein the sustain discharge pulse is increased in proportion to time until a first voltage, and is then instantaneously raised from the first voltage to a second voltage which is a sustain discharge pulse voltage. Driving method. 3. The method of driving a plasma display panel according to claim 2, wherein the first voltage is limited to a voltage at which a discharge current does not flow. The method of claim 1, wherein the sustain discharge pulse is instantaneously raised to a first voltage and is increased in proportion to time from the first voltage to the second voltage, and then is instantaneously raised from the second voltage to a third voltage which is a sustain discharge pulse voltage. And a plasma display panel for driving the plasma display panel.