KR20020017738A - A method for forming a transistor of a semiconductor device - Google Patents
A method for forming a transistor of a semiconductor device Download PDFInfo
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- KR20020017738A KR20020017738A KR1020000051250A KR20000051250A KR20020017738A KR 20020017738 A KR20020017738 A KR 20020017738A KR 1020000051250 A KR1020000051250 A KR 1020000051250A KR 20000051250 A KR20000051250 A KR 20000051250A KR 20020017738 A KR20020017738 A KR 20020017738A
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- hard mask
- mask layer
- gate electrode
- semiconductor device
- pulse modulation
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 19
- 239000010937 tungsten Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 241000270281 Coluber constrictor Species 0.000 claims description 3
- OQZCSNDVOWYALR-UHFFFAOYSA-N flurochloridone Chemical compound FC(F)(F)C1=CC=CC(N2C(C(Cl)C(CCl)C2)=O)=C1 OQZCSNDVOWYALR-UHFFFAOYSA-N 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 abstract description 3
- 239000007789 gas Substances 0.000 description 7
- 238000010849 ion bombardment Methods 0.000 description 5
- 229920000642 polymer Polymers 0.000 description 5
- 229910052799 carbon Inorganic materials 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 238000000059 patterning Methods 0.000 description 2
- 238000005513 bias potential Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Abstract
Description
본 발명은 반도체소자의 게이트전극 형성방법에 관한 것으로, 특히 게이트전극으로 사용되는 텅스텐 상부에 하드마스크층을 형성하고 이들의 패터닝 공정을 용이하게 실시할 수 있도록 하여 후속 공정에서 자기정렬적인 콘택공정을 용이하게 실시할 수 있도록 하는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate electrode of a semiconductor device. In particular, a hard mask layer is formed on a tungsten used as a gate electrode and a patterning process thereof can be easily performed. It is to make it easy to implement.
반도체소자가 고집적화될수록 게이트전극 형성공정에서의 저항을 해결하기 위한 대안으로 텅스텐 게이트전극을 적용하는 중에 있다.As semiconductor devices become more integrated, a tungsten gate electrode is being applied as an alternative to solve the resistance in the gate electrode forming process.
그리고, 이후 공정인 자기정열적인 콘택 공정 적용시 마진 확보를 위해 하드마스크층을 적용하고 있다.In addition, a hard mask layer is applied to secure a margin when applying a self-aligned contact process.
그러나, 상기 하드마스크층을 사용하는 경우 식각 타겟이 높아지고 감광막과의 식각선택비가 좋지 않으며, SF6베이스 가스로 텅스텐을 식각하게 되면 패턴 낫칭 현상이 유발된다.However, when the hard mask layer is used, the etching target is high and the etching selectivity with the photoresist film is not good. When tungsten is etched with SF 6 base gas, pattern hardening occurs.
이상에서 설명한 바와같이 종래기술에 따른 반도체소자의 게이트전극 형성방법은, 텅스텐을 게이트전극 물질로 사용하여 패턴 낫칭이 유발되고 그로 인하여 반도체소자의 수율, 특성 및 신뢰성이 저하되며 반도체소자의 고집적화가 어렵게 되는 문제점이 있다.As described above, in the method of forming a gate electrode of a semiconductor device according to the related art, pattern hardening is induced by using tungsten as a gate electrode material, thereby lowering the yield, characteristics and reliability of the semiconductor device, and making it difficult to integrate the semiconductor device. There is a problem.
본 발명의 상기한 종래기술의 문제점을 해결하기위하여, 하드마스크층 식각공정시 소오스 전력과 바이어스 전력의 아웃 페이스 펄스 모듈레이션 ( out phase pulse modulation )을 이용하여 감광막 과의 식각선택비 차이를 높임으로써 낫칭 유발을 최소화시켜 반도체소자의 수율, 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 게이트전극 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art of the present invention, by hardening the etching selectivity with the photosensitive film by using out phase pulse modulation of source power and bias power during hard mask layer etching process It is an object of the present invention to provide a method for forming a gate electrode of a semiconductor device which minimizes the occurrence of the semiconductor device, thereby improving the yield, characteristics, and reliability of the semiconductor device, thereby enabling high integration of the semiconductor device.
도 1a 내지 도 1d 는 본 발명의 실시예에 따른 반도체소자의 게이트전극 형성방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11 : 반도체기판 15 : 텅스텐막11 semiconductor substrate 15 tungsten film
17 : 하드마스크층 19 : 감광막패턴17: hard mask layer 19: photosensitive film pattern
21 : 탄소 리치막21: carbon rich film
본 발명에 따른 반도체소자의 게이트전극 형성방법은, 반도체기판 상부에 게이트전극용 텅스텐막, 하드마스크층을 적층하는 공정과, 상기 하드마스크층 상부에 감광막패턴을 형성하는 공정과, 상기 감광막패턴을 마스크로 하여 상기 하드마스크층을 식각하되, 아웃 페이스 펄스 모듈레이션을 이용하여 실시하는 공정과, 상기 텅스텐막을 식각하되, 상기 하드마스크층과 인슈트로 실시하는 공정과, 상기 감광막패턴을 제거하는 공정을 포함하는 것을 특징으로한다.A method of forming a gate electrode of a semiconductor device according to the present invention includes the steps of laminating a tungsten film for a gate electrode and a hard mask layer on a semiconductor substrate, forming a photoresist pattern on the hard mask layer, and forming the photoresist pattern. Etching the hard mask layer using a mask, using an out-face pulse modulation, etching the tungsten film with the hard mask layer and an in-shoot, and removing the photoresist pattern. It is characterized by.
본 발명의 원리는, 아웃풋 페이스 펄스 모듈레이션을 이용하여 감광막과 하드마스크층과의 식각선택비 차이를 크게 함으로써 낫칭 현상을 개선하고자 하는 것이다.The principle of the present invention is to improve the knocking phenomenon by increasing the difference in etching selectivity between the photoresist film and the hard mask layer by using output face pulse modulation.
여기서, 상기 펄스 모듈레이션이란, 플라즈마 턴온 ( plasma turn on ) 에 중요한 역할을 하는 전력을 주기적으로, 예를들면 200 - 400 μ초 간격으로 온/오프 시키는 것을 말한다.Here, the pulse modulation refers to turning on / off power which plays an important role in plasma turn on periodically, for example, at intervals of 200 to 400 μs.
상기 펄스 모둘레이션은 여러종류가 있는데 대표적으로 ICP 형이 있다.There are several types of pulse modulation, and typically ICP type.
상기 ICP 형 펄스 모듈레이션은, 듀티 레이셔 ( duty ratio ) 50 퍼센트에 소오스 전력과, 바이어스 전력 간에 같은 주기로 RF 전력을 온/오프 시키는 인 페이스 펄스 모둘레이션 ( in phase pulse modulation ) 과, 페이스 디퍼런스 ( phase difference ) 파이 (π)의 간격으로 소오스전력이 온일 때 바이어스 전력이오프이고 소오스 전력이 오프일 때 바이어스 전력이 온인 아웃풋 페이스 펄스 모듈레이션이 있다. 그리고, RF 전력에 펄스를 주지 않는 경우를 연속파 ( continuous wave, 이하에서 CW 라 함 ) 가 있다.The ICP-type pulse modulation includes in-phase pulse modulation for turning on / off the RF power at the same period between the source power and the bias power at a duty ratio of 50 percent, and a phase reference ( phase difference) There is an output phase pulse modulation where the bias power is off when the source power is on and the bias power is on when the source power is off at intervals of pi (π). In addition, there is a continuous wave (hereinafter referred to as CW) that does not give a pulse to the RF power.
바이어스 전력이 온일 때 웨이퍼 상부에 바이어스 전위 ( bias potential ) 는 CW, 인 페이스, 아웃 페이스 순서로 증가하고 또한 Vdc ( self-dc bias ) 의 경우도 CW, 인 페이스, 아웃 페이스 순서로 증가하게 된다.When the bias power is on, the bias potential at the top of the wafer increases in the order of CW, in-phase, and out-phase, and also in the case of Vdc (self-dc bias) in order of CW, in-face, and out-face.
예를들면, CW 상태에서 Vdc 가 -300 V 정도가 되면 아웃 페이스의 경우는 -600 V 정도로 높아지게 된다.For example, in the CW state, when Vdc reaches -300 V, the phase increases to about -600 V.
아웃 페이스의 경우 소오스 전력이 오프일 때 바이어스 전력이 온 되므로 Vdc 의 값이 상대적으로 증가되는 것으로 판단된다.In the case of the out phase, the bias power is turned on when the source power is off, so the value of Vdc is relatively increased.
Vdc 값이 증가하게 되면 이온 밤바드먼트 ( ion bombardment ) 가 증가하게 되는데 본 발명에 주요 가스인 C4F8 의 경우 이온 밤바드먼트로 중성의 C4F8 가 F2, CF4의 휘발성 ( volatile ) 이 강한 가스로 분리되고 나머지 성분들이 탄소 결합 ( C-C bonding ) 되어 탄소 리치 막 ( C-rich film )과 같은 무거운 폴리머가 성장된다.When the value of Vdc increases, ion bombardment increases.4F8 In the case of neutral C as an ion bombardment4F8 Fall F2, CF4Volatile gases are separated into strong gases, and the remaining components are carbon-bonded to produce heavy polymers such as carbon-rich films.
이러한 무거운 폴리머가 패턴 측벽 또는 상단에 만들어지면 식각시 이방성, 등방성에 대한 식각 선택비가 휠씬 높아지는 장점이 있다.If such a heavy polymer is made on the pattern sidewall or the top, there is an advantage that the etching selectivity for anisotropy and isotropy is much higher during etching.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d 는 본 발명의 실시예에 따른 반도체소자의 게이트전극 형성방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 반도체기판(11) 상부에 텅스텐막(15), 하드마스크층(17)을 각각 적층한다.Referring to FIG. 1A, a tungsten film 15 and a hard mask layer 17 are stacked on the semiconductor substrate 11, respectively.
그리고, 상기 하드마스크층(17) 상부에 감광막패턴(19)을 형성한다.The photoresist pattern 19 is formed on the hard mask layer 17.
이때, 상기 텅스텐막(15)은 게이트전극용 도전층으로 구비된 것이고, 상기 하드마스크층(17)은 산화막으로 형성한다.In this case, the tungsten film 15 is provided as a conductive layer for the gate electrode, and the hard mask layer 17 is formed of an oxide film.
그리고, 상기 감광막패턴(19)은 상기 하드마스크층(17) 상부에 감광막을 도포하고 이를 게이트전극용 노광마스크를 이용한 노광 및 현상공정으로 패터닝한 것이다.The photoresist pattern 19 is formed by applying a photoresist on the hard mask layer 17 and patterning the photoresist using an exposure mask for a gate electrode.
도 1b 및 도 1c 를 참조하면, 상기 감광막패턴(19)을 마스크로 하여 상기 하드마스크층(17)을 식각한다.1B and 1C, the hard mask layer 17 is etched using the photoresist pattern 19 as a mask.
이때, 상기 하드마스크층(17)의 식각공정은 아웃 페이스 펄스 모듈레이션으로 C4F8/Ar를 베이스로 하는 가스를 이용하여 실시하되, 압력은 10 mtorr 이하, C4F8가스는 10 - 20 sccm의 유량, Ar 은 30 - 40 sccm 의 유량으로 하여 실시한다.At this time, the etching process of the hard mask layer 17 is performed using a gas based on C 4 F 8 / Ar as the out-face pulse modulation, the pressure is 10 mtorr or less, C 4 F 8 gas is 10-20 The flow rate of sccm, Ar is carried out at a flow rate of 30-40 sccm.
상기 아웃 페이스 펄스 모듈레이션은 ICP 형의 장비를 이용하되, 듀티 레이셔 50 퍼센트, 주기 200 - 400μ초, 페이스 디퍼런스 π 인 조건으로 이용한다.The out-face pulse modulation uses equipment of the ICP type, but under conditions of 50 percent duty racer, period 200-400 μs, and phase difference π.
여기서, 상기 듀티 레이셔 50 페센트는 소오스 전력이 온일 때 바이어스 전력이 오프 상태이고 나머지 50 퍼센트는 소오스 전력오프일 때 바이어 전력이 온인 것이다. 그리고, Vdc 가 -500 ∼ -700 V 정도로 나타나, 종래의 -200 ∼ -400 V 보다 높고 이는 이온 밤바드먼트를 증가시킨다. 그리고, 상기 이온 밤바드먼트는 C4F8를 F2, CF4와 같은 휘발성 성분으로 분리시키고 나머지 성분들은 탄소결합을 만들어 탄소 리치막(21)을 성장시킨다.Here, the duty racer 50 percent is the bias power is off when the source power is on and the remaining 50 percent is the buyer power is on when the source power off. And, Vdc appears to be about -500 to -700 V, which is higher than conventional -200 to -400 V, which increases the ion bombardment. The ion bombardment separates C 4 F 8 into volatile components such as F 2 and CF 4, and the remaining components form a carbon bond to grow the carbon rich film 21.
또한, 소오스 전력이 오프이고 바이어스 전력이 온일 때 이온 밤바드먼트가 훨씬 증대하여 무거운 폴리머가 형성되게 된다.In addition, when the source power is off and the bias power is on, the ion bombardment is much increased resulting in the formation of heavy polymers.
상기 무거운 폴리머는 상기 하드마스크층의 식각공정시 감광막의 손상을 감소시킬뿐아니라 상기 텅스텐막(15)의 식각공정시에도 상기 감광막패턴(19)이 충분히 남아있게 되어 패턴의 낫칭현상을 방지할 수 있다. 또한, 상기 무거운 폴리머는 후속공정에서 유발될 수 있는 언더컷 ( under cut )을 사전에 방지할 수 있다.The heavy polymer not only reduces the damage of the photoresist film during the etching process of the hard mask layer, but also allows the photoresist pattern 19 to be sufficiently left during the etching process of the tungsten film 15, thereby preventing the curing of the pattern. have. In addition, the heavy polymer can prevent in advance undercuts that may be caused in subsequent processes.
그 다음, 인슈트 ( in-situ ) 로 상기 텅스텐막(15)을 식각한다.Next, the tungsten film 15 is etched with an in-situ.
이때, 상기 텅스텐막(15)의 식각공정은 SF6를 베이스로 하는 가스를 이용하여 실시하되, 압력은 10 - 20 mtorr, SF6가스는 60 - 80 sccm의 유량으로 하여 실시한다.At this time, the etching process of the tungsten film 15 is carried out using a gas based on SF 6 , the pressure is 10-20 mtorr, SF 6 gas at a flow rate of 60-80 sccm.
도 1d를 참조하면, 상기 감광막패턴(19)을 제거하고 전체표면상부를 세정한다.Referring to FIG. 1D, the photoresist pattern 19 is removed and the entire upper surface portion is cleaned.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 게이트전극 형성방법은, 아웃 페이스 펄스 모듈레이션을 이용하는 인슈트 공정으로 하드마스크층의텅스텐막을 용이하게 식각하여 낫칭현상을 방지함으로써 반도체소자의 수율을 향상시키고 그에 다른 특성 및 신뢰성을 향상시키는 효과를 제공한다.As described above, the gate electrode forming method of the semiconductor device according to the present invention is an in-step process using an out-face pulse modulation to easily etch the tungsten film of the hard mask layer to prevent the hardening phenomenon, thereby improving the yield of the semiconductor device. Provide the effect of improving other properties and reliability.
Claims (4)
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