KR20020017105A - Method for isolating semiconductor devices - Google Patents

Abstract

PURPOSE: An isolation method for a semiconductor device is provided to reduce junction capacitance, by forming an additional buried insulation layer in the periphery of an isolation layer so that the size of a doping region is physically decreased and a source/drain junction area is reduced. CONSTITUTION: An isolation region and an active region are defined in a semiconductor substrate(31). The isolation region is eliminated to form a trench. An oxygen ion buried layer is formed in the active region adjacent to the trench. The oxygen ions are reacted with the semiconductor substrate to form a buried oxide layer(370) extending to the active region. The trench is filled with an insulation material.

Description

Device isolation method for semiconductor devices {Method for isolating semiconductor devices}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device. In particular, a buried oxide layer is formed by oxygen ion implantation around a trench of a semiconductor substrate for device isolation, and then a device isolation film is completed to reduce the size of an impurity diffusion region of a transistor device. The present invention relates to a trench type device isolation method of a semiconductor device, which reduces the junction capacitance and improves device characteristics.

As the integration of semiconductor devices continues, technology development for reducing the device isolation region occupying a considerable area of the semiconductor device is actively progressing.

BOX (buried oxide) type shallow trench isolation technology for device isolation is provided by forming a trench in a semiconductor substrate and not doped with silicon oxide or impurities by chemical vapor deposition (CVD). Has a structure in which polycrystalline silicon is embedded. Therefore, no buzz beaking occurs, there is no loss of the active region, and a flat surface can be obtained by embedding and etching back the oxide film.

However, as the device size decreases in inverse proportion to the increase in device density, the doping concentration of the impurity doped region forming the source / drain increases, so that the capacitance in the junction increases. This causes the high speed operation of the device to be difficult.

1A to 1D are process diagrams illustrating a device isolation method using a shallow trench according to the prior art.

Referring to FIG. 1A, a buffer oxide film 13 is formed on a semiconductor substrate 11 by a thermal oxidation method, and chemical vapor deposition (hereinafter referred to as CVD) is performed on the buffer oxide film 13. Silicon nitride is deposited to form a pad nitride film 15.

The pad nitride film 15 and the buffer oxide film 13 are sequentially patterned to expose the semiconductor substrate 11 by a photolithography method to define the device isolation region and the active region.

Referring to FIG. 1B, the trench T1 is formed by etching the exposed device isolation region of the semiconductor substrate 11 to a predetermined depth by using the remaining pad nitride film 15 as a mask. The trench T1 is formed by anisotropic etching by reactive ion etching (hereinafter referred to as RIE) or plasma etching.

Referring to FIG. 1C, silicon oxide is deposited on the pad nitride film 15 by CVD to fill the trench. The silicon oxide is exposed to the pad nitride film 15 to be etched back by chemical-mechanical polishing (hereinafter referred to as CMP) method or RIE method so as to remain only in the trench. At this time, the silicon oxide remaining in the trench becomes a field oxide film 17 separating the elements.

Referring to FIG. 1D, the pad nitride layer 15 and the buffer oxide layer 13 are sequentially removed by a wet etching method to expose the active region of the semiconductor substrate 11. At this time, a portion higher than the surface of the semiconductor substrate 11 of the field oxide film 17 is also etched to reduce the level difference.

In addition, a gate oxide film (not shown), a gate (not shown), and an impurity doped region 19 are formed on the exposed surface of the substrate to fabricate a transistor device. At this time, the depth of the impurity doped region 19 formed by conducting impurity ion implantation, annealing, etc. opposite to the substrate is determined by the doping profile determined at the time of ion implantation.

Therefore, in the prior art, it is difficult to physically control the expansion of the doped region 19 which affects the magnitude of the junction capacitance.

The device isolation method of the conventional semiconductor device described above has a problem in that it is not possible to prevent an increase in section capacitance caused by an increase in the doping concentration of the doped region as the device size decreases.

Accordingly, an object of the present invention is to form a buried oxide layer by implanting oxygen ions around the trench of the semiconductor substrate for device isolation, and then complete the device isolation film to reduce the capacitance capacitance and reduce the device capacitance by reducing the size of the impurity diffusion region of the transistor device. It is to provide a trench type device isolation method of a semiconductor device to improve the characteristics.

In order to achieve the above object, a device isolation method of a semiconductor device according to the present invention includes a first step of forming a trench by removing a portion of the device isolation region of a semiconductor substrate in which a device isolation region and a device active region are defined. A second step of forming an oxygen ion buried layer in an adjacent device active region of the substrate; and a third step of forming an buried oxide layer extended to the device active region by reacting the oxygen ions with a semiconductor of the substrate; And a fourth step of filling the trench with an insulating material.

1A to 1D are process cross-sectional views showing a device isolation method of a semiconductor device according to the prior art.

2A to 2E are process cross-sectional views showing a device isolation method for a semiconductor device according to the present invention.

The present invention physically reduces the size of the doped region by forming a separate buried insulating layer around the device isolating film in order to prevent the increase of the junction capacitance as the size of the device is reduced. At this time, the buried insulating layer is formed of silicon oxide reacted with oxygen ions and silicon of the substrate after the ion buried layer is formed on the bottom or side of the trench forming the device isolation film by oxygen ion implantation.

Therefore, by reducing the formation area of the impurity diffusion region, which is the source / drain region of the transistor, the section area is reduced and the capacitance of the parasitic capacitance is reduced.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are process cross-sectional views showing a device isolation method of a semiconductor device according to the present invention.

Referring to FIG. 2A, a buffer oxide film 33 is formed on a semiconductor substrate 31 by a thermal oxidation method, and chemical vapor deposition (hereinafter, referred to as CVD) is performed on the buffer oxide film 33. Silicon nitride is deposited to form a pad nitride film 35.

The pad nitride film 35 and the buffer oxide film 33 are sequentially patterned to expose the semiconductor substrate 31 by a photolithography method to define the device isolation region and the active region.

Referring to FIG. 2B, the trench T2 is formed by etching the exposed device isolation region of the semiconductor substrate 31 to a predetermined depth by using the remaining pad nitride layer 35 as a mask. The trench T2 is formed by anisotropic etching by reactive ion etching or plasma etching.

Oxygen ion implantation is then performed perpendicular to the exposed trench substrate to form the oxygen ion buried layer 37. In the exemplary embodiment of the present invention, the oxygen ion investment layer is formed on the substrate portion of the bottom portion of the trench T2. In another embodiment, the oxygen ion investment layer may be formed on the side of the trench by tilt ion implantation.

Referring to FIG. 2C, an oxide ion buried layer is heat-treated to form a buried oxide layer 370 at a predetermined depth from the surface of the active region substrate and at the same time on the bottom of the trench. Therefore, the buried oxide layer 370 extends to the source / drain region of the transistor to be formed in a subsequent process, so that the source / drain region is relatively reduced, thereby reducing the junction capacitance.

Then, silicon oxide is deposited on the pad nitride film 35 by CVD to fill the trench. Then, the silicon oxide is etched back by chemical-mechanical polishing (hereinafter referred to as CMP) method or RIE method so that the pad nitride film 35 is exposed to remain only in the trench. At this time, the silicon oxide remaining in the trench becomes a field oxide film 39 that separates the elements.

Referring to FIG. 2D, the pad nitride layer and the buffer oxide layer are sequentially removed by a wet etching method to expose the active region of the semiconductor substrate 31. At this time, a portion higher than the surface of the semiconductor substrate 31 of the field oxide film 390 is also etched to reduce the level difference.

Then, a gate oxide film (not shown), a gate (not shown), and a source / drain impurity doped region 41 are formed on the exposed surface of the substrate to fabricate a transistor device. At this time, the depth d2 of the impurity doping region 41 formed by conducting impurity ion implantation and annealing, which is opposite to the substrate, penetrates into the active region instead of the formation depth of the impurity doping region 41 determined by the ion implantation. It is determined by the buried oxide layer 370.

Therefore, in the embodiment of the present invention, it is easy to physically control the expansion of the doped region 41 which affects the magnitude of the junction capacitance.

In the same technical concept, as described above, even if the buried oxide layer is selectively formed on the trench side by inclined ion implantation, the same result is obtained.

Accordingly, the present invention reduces the source / drain junction area by physically reducing the doped region size by forming a separate buried insulating layer around the device isolation layer, thereby reducing the parasitic capacitance, which is the parasitic capacitance, to improve the high-speed operation of the device. There is an advantage.

Claims (5)

A first step of forming a trench by removing the device isolation region portion of the semiconductor substrate in which the device isolation region and the device active region are defined; A second step of forming an oxygen ion buried layer in the device active region of the substrate adjacent to the trench; Reacting the oxygen ions with the semiconductor of the substrate to form a buried oxide layer extended to the device active region; And a fourth step of filling the trench with an insulating material. The method according to claim 1, And the oxygen ion buried layer is formed by implanting oxygen ions so as to be inclined at a predetermined angle with the surface of the semiconductor substrate. The method according to claim 1, And the buried oxide layer is formed by supplying heat to the substrate. The method according to claim 1, And forming the oxygen ion buried layer on the side surface of the substrate exposed by the trench. The method according to claim 1, And depositing the oxygen ion buried layer in the bottom and side surfaces of the trench.