KR20020015088A - Apparatus and Method for clock error detection without external oscillator - Google Patents

Abstract

PURPOSE: An apparatus for detecting a clock error without an external clock source and an operation method thereof are provided, which can detect an error of a clock under the condition that an external oscillator can not be attached in a space in a board. CONSTITUTION: The first divider part(11A) divides a duplicated signal into two, and the second divider part(12A) divides the signal divided in the first divider part into two. An XOR gate(15A) performs an XOR operation by reading the signal divided in the second divider part and a signal divided in the first divider part(11B) of a block processing another side of the duplicated signal through two D-flip flops(13A,14A). A latch-inverter part(16A) latches an output of the XOR gate with the signal divided in the first divider part(B) and inverts it. And a count-comparison part(17A,18A) indicates whether an input signal has an error or not, by comparing a counting value of an inverted signal of the output signal of the latch-inverter part with an non-inverted signal of the output signal of the latch-inverter part.

Description

Apparatus and method for clock error detection without external oscillator}

The present invention relates to the detection of the normality of the clock in the unit, and in particular, it is possible to detect the error of the clock input into the unit from the outside without an external oscillator, so that the external oscillator cannot be attached to the space in the board. The present invention relates to a device for detecting a clock error without an external clock source that enables error detection of a clock even in a state and a method of operating the same.

In general, each unit in the board is supplied with a clock to process the input signal. However, when an error occurs in the clock, the signal processing result of the corresponding unit may not be reliable, and in some cases may cause a malfunction of the entire system.

Therefore, each unit is provided with means for detecting the error of the clock supplied from the outside to ensure the stability of the signal processing.

In this case, since the clock is supplied from the outside together with the signal to be processed, it is common to check whether there is an abnormality in the source clock by comparing the clock with an external clock source.

One of these methods is to attach a separate oscillator to the outside of the unit. Therefore, the source clock input to the unit is properly divided, and then read into the external oscillator clock to check the toggle state of the clock.

Checking the toggle state can detect errors in the clock.

Error checking of the source clock using the external oscillator is generally well known.

However, the above-described prior art has a problem in that a separate oscillator must be provided to check only a high / low state transition of a simple clock.

Therefore, there is a limit that the above method cannot be applied when there is no free space for adding an oscillator in the board.

Accordingly, the present invention has been proposed to solve the above-mentioned conventional problems, and an object of the present invention is to detect whether an error of a clock input into the unit from the outside is detected without an external oscillator. It is an object of the present invention to provide a device for detecting a clock error without an external clock source that enables the error detection of a clock even when an external oscillator cannot be attached to it.

In order to achieve the above object, an apparatus for detecting a clock error without an external clock source according to the present invention includes a first divider for dividing a redundant signal input from the outside; A second divider for re-dividing the signal divided by the first divider; An XOR gate that reads the signal divided by the second divider through a plurality of D-flips and performs an exclusive OR on the signal divided by the first divider of the block for processing the other side of the redundant signal; A latch-inverting portion for latching and inverting an output of the XOR gate with a signal divided in a first division portion of a block for processing the other side of the redundancy signal; Each block is duplicated by duplexing a block consisting of a count-comparison unit indicating whether an error of an input signal is obtained by comparing a value counted by the latch-inverting unit with a signal before the inversion of the latch-inverting unit. The technical feature is that each of them is configured to check whether or not an error of a given signal occurs.

In addition, in order to achieve the above object, a device for detecting a clock error without an external clock source according to the present invention includes a reset signal for outputting a clock active signal and an asynchronous reset signal using a read active signal and a test clock supplied from an external processor. Sweets; The technical configuration is characterized by being reset by the asynchronous reset signal output from the reset signal stage and generating an output according to the read active signal and the test clock, and consisting of a plurality of D-flip flops connected in series.

In order to achieve the above object, a method of operating an apparatus for detecting a clock error without an external clock source according to the present invention includes: performing an error check through mutual monitoring of a duplicated clock; If an error occurs in one of the duplicated clocks, checking whether the other error occurs through monitoring using an external processor; The technical configuration is characterized in that the step of taking an appropriate action is performed when an abnormality is detected on both sides of the redundant clock by performing the above steps.

1 is a block diagram of an apparatus for detecting a clock error without an external clock source and an operation method thereof according to an embodiment of the present invention;

2 is a timing diagram of each signal in the apparatus according to FIG.

3 is a block diagram of an apparatus for detecting a clock error without an external clock source and an operation method thereof according to another embodiment of the present invention;

4 is a timing diagram of each signal in the apparatus shown in FIG.

5 is a flowchart of an operating method for an apparatus according to the present invention.

Explanation of symbols on the main parts of the drawings

11A, 12A, 13A, 14A, 16A, 11B, 12B, 13B, 14B, 16B: D-Flip-Flop

13A, 13B: XOR Gate 17A, 17B: Counter

18A, 18B: JK-Flip Flop

Hereinafter, the configuration and operation of the present invention will be described in detail according to an embodiment of the present invention according to the technical concept of the apparatus for detecting a clock error without the external clock source and its operation method.

First, FIG. 1 is a block diagram of an apparatus for detecting a clock error and an operation method thereof without an external clock source according to an embodiment of the present invention. FIG. 2 is a timing diagram of each signal in the apparatus of FIG. 3 is a block diagram of an apparatus for detecting a clock error and an operation method thereof without an external clock source according to another embodiment of the present invention. FIG. 4 is a timing diagram of each signal in the apparatus of FIG. 2, and FIG. Flow chart of the operation method for the device by.

As shown in FIG. 1, a preferred embodiment of the present invention comprises: a first divider 11A for dividing an input redundant signal by two; A second divider 12A for dividing the signal divided by the first divider 11A into two; The signal divided by the second divider 12A is read through two D-flip flops 13A and 14A as a signal divided by the first divider 11B of the block for processing the other side of the redundant signal. An XOR gate 15A for performing an exclusive OR operation; A latch-inverting portion (16A) for latching and inverting the output of the XOR gate (15A) with a signal divided in the first division portion (11B) of the block for processing the other side of the redundancy signal; A count-comparison unit which compares the value of the inverted signal among the output signals of the latch-inverting unit 16A with an uninverted signal among the output signals of the latch-inverting unit 16A and indicates an error of the input signal. It consists of (17A, 18A).

As shown in FIG. 3, another embodiment of the present invention uses a read enable signal REN and a test clock TESTCLK of a MCU to output a clock enable signal CLOCKEN and an asynchronous reset signal ASYNCRST. Signal stages 25, 26, 27; A plurality of D-flip flops that are reset by the asynchronous reset signal ASYNCRST output from the reset signal stages 25, 26, and 27 and generate an output corresponding to the read active signal REN and the test clock TESTCLK, and are connected in series. (21, 22, 23, 24).

In addition, as shown in Figure 5, the operation method according to the present invention, the step of performing the error check through mutual monitoring for the duplicated clock (ST11 ~ ST12); If an error occurs in one of the redundant clocks, checking whether the other error is detected through monitoring using a processor (ST13 to ST14); If an abnormality is detected on both sides of the redundant clock by performing the above steps ST13 to ST14, steps (ST15 to ST17) of taking appropriate measures are performed.

The operation of the device configured as described above is as follows.

The present invention makes it possible to check for errors in the clock in the unit in the absence of an external oscillator or no space for attaching.

The present invention provides two alternatives for this operation.

First, in the first embodiment, since the system clock input from one unit is mostly duplicated, error checking is performed by mutually monitoring the duplicated clock. That is, it is possible to detect a case where the duplicated clock is normally input and there is no input of either clock or the clock frequency is severely shaken.

Such a device can be simply configured with a D-flip-flop and several gates, without increasing the burden on logic capacity.

In FIG. 1, the first divided clocks ADCK and BDCK are generated by dividing the duplicated source clocks ACLK and BCLK into two using the first D-flip flops 11A and 11B. The divided clock ADCK (BDCK) is further divided into two to generate a second divided clock ADDAT (BDDAT). In this case, second D-flip flops 12A and 12B are used.

The second divided clock ADDAT (BDDAT) is generated to determine whether errors of the duplicated clocks A and B are performed. The error determination of the clocks A and B is symmetric with each other, so only the error determination operation of the clock A is described. Let's do it.

The second division clock ADDAT reads the ADDAT twice into the BDCK through the third and fourth D-flip flops 13A and 14A. In the above, the input and the output of the fourth D flip-flop 14A are exclusive-OR at the XOR gate 15A.

The output of the XOR gate 15A is read back to BDCK in the fifth D-flip flop 16A. The output of the fifth D-flip flop 16A indicates whether an input clock has an error (ACLK_FAULT). In this case, when the redundant clock is normal, the input clock ACLK and BCLK have the same frequency, so that the input and the output of the fourth D-flop flop 14A have opposite phases.

On the other hand, when there is no ACLK input, the divided clocks do not change, so the input terminal and the output terminal of the fourth D-flop flop 14A have the same phase and the output of the XOR gate 15A becomes '0'. .

Then, the output of the sixth D-flip flop 16A (ACLK_FAULT) is inverted in phase and input to the LOAD terminal of the 161_counter 17A. The counter 17A outputs a carry out when the ACLK_FAULT lasts for some time and passes the count value.

The carry out of the counter 161_ counter 17A and the output signal ACLK_FAULT of the sixth D-flip flop 16A are input to the J terminal and the K terminal of the JK flip-flop 18A, respectively. The JK flip-flop 18A is set when the input of the J terminal is '1' and maintains an error state when the J terminal and the K terminal are '0' because of an error in the input clock.

When the input clock returns to normal, the K terminal input becomes '1' and the output of the JK flip-flop 18A becomes '0'. The output (ACLK_FAULT_TIMECON) of the JK-flip-flop 18A indicates an error of the input clock A, and when '0' indicates that the clock A is normal.

The above description relates to error checking of the input clock A, and performs error checking of the input clock B according to the same scheme as described above.

Figure 2 shows the results of simulating the timing diagram of each signal in such a device. It can be seen from the illustration that error detection of the input clock is possible.

However, the device described above has the advantage of simple configuration, but there is a disadvantage that no error detection is possible when there is an error in all of the redundant clocks. This disadvantage is overcome by another embodiment of the present invention.

The device according to another embodiment of the present invention basically requires an interface with a main control unit (hereinafter referred to as MCU) with a processor. The read active signal (REN) sent from the MCU is converted into the clock active signal of the flip-flop.

Considering the pulse width of the read active signal (REN), the timing at which the MCU buffers data on the data bus, and the target clock frequency, a multi-stage flip-flop is configured. Therefore, when the circuit is operated with the clock to be monitored, the pulse of the read active signal REN and the pulse of the read active signal REN, the circuit is operated, and the tabs at each end of the flip-flop are loaded onto the data bus. If the input clock is normally input, the data will always change. For example, the data might look like 101010 ... or 010101 ...

On the other hand, when there is no clock input, the data becomes 000000 ..., so that the error of the input clock can be detected by detecting a state without the clock input.

Referring to FIG. 3, the CLOCKEN signal is generated by inverting the read activation signal REN input from the MCU. The read activation signal REN is delayed by two D-flip flops 25 and 26, and is read as an error detection clock TESTCLK and outputted through the AND gate 27.

The output of the AND gate 27 is an Async Reset signal ASYNCRST, which is a signal for resetting the plurality of D-flip flops 21, 22, 23, and 24.

The CLOCKEN signal is divided into two and passes through a number of D-flip flops 21, 22, 23, 24. The plurality of D-flip flops 21, 22, 23, and 24 are reset by ASYNCRST to output '0', thereby operating normally when performing the next monitoring operation.

Four D flip-flops 21, 22, 23, and 24 read the CLOCKEN signal as TESTCLK, and the output signal of each flip-flop becomes the input of the flip-flop of the rear stage.

At this time, if the data Q0, Q1, Q2, and Q3 are extracted from the output terminals of each of the D-flip flops 21, 22, 23, and 24 and loaded on the data bus, the signal pattern that is constantly changed only when the input clock is normal Come out. For example, it becomes a pattern of 1010 or 0101.

On the other hand, if the input clock is abnormal, especially if there is no input clock signal signal of 0000 comes out on the data bus.

Since the MCU reads the data around the pulse of the read active signal REN, a signal pattern of 1010 or 0101 is read when the input clock is normal, and 0000 is read when the input clock is abnormal.

By repeatedly performing the above operation, the MCU may determine whether the input clock is normal or abnormal by reading the signal pattern of the data bus. At this time, the MCU interprets the signal pattern of the data bus in software to determine whether the input clock is in error.

Fig. 4 shows each signal timing diagram of the apparatus according to Fig. 3, and it is clear from this timing diagram that it is possible to determine whether an input clock is abnormal.

Meanwhile, in the case of the first embodiment of the present invention, since the error occurring in both clocks cannot be detected, the first device (hereinafter referred to as a mutual monitoring device) and the second device (hereinafter referred to as a monitoring device using a processor) It is efficient to operate variably. A monitoring device using a processor is applicable even when there is only one system clock.

Thus, in the method of operating the apparatus according to the present invention, as shown in FIG. 5, when the error check is performed by using the mutual monitoring apparatus, and both sides of the redundant clock are normally operated, if an error occurs in either clock, the processor is executed. Repeat the error check using the monitoring device used (ST11 ~ ST14).

If the error check using the monitoring device using the processor confirms that an error has occurred in all the duplicated clocks, an appropriate action is taken, such as notifying the operator or switching the unit (ST17). When it is confirmed that an error has occurred in only one clock (ST15), the input clock is periodically monitored by using a monitoring device using a processor to monitor whether an error occurs in a clock that operates normally.

At this time, if the abnormal operation of the input clock returns to normal while monitoring the clock abnormality using the monitoring device using the processor, the MCU stops the periodic monitoring and returns to the state where error checking using the mutual monitoring device is possible (ST15). To ST16).

As described above, the present invention uses a method applied to the device by constructing a simple device, and there is no clock source such as an external oscillator in the board, or a clock error input into the unit even when there is insufficient space for the clock source. You can check whether it is.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, an apparatus for detecting a clock error without an external clock source and an operation method thereof according to the present invention overcome the disadvantages of the prior art of checking whether an input clock is error by using a clock supplied from an external oscillator, It has the effect of detecting clock error even when no external oscillator can be attached because there is no space in the board.

In addition, the device according to the present invention can be simply configured with a few D-flip flops, logic gates, and the like, and can be easily applied to a unit requiring error detection of a clock.

Claims (9)

A first divider 11A for dividing the redundant signal input from the outside; A second dividing unit 12A for re-dividing the signal divided by the first dividing unit 11A; The signal divided by the second divider 12A as a signal divided by the first divider 11B of the block for processing the other side of the redundant signal is read through a plurality of D-flip flops 13A and 14A. An XOR gate 15A for performing an exclusive OR operation; A latch-inverting portion (16A) for latching and inverting the output of the XOR gate (15A) with a signal divided in the first division portion (11B) of the block for processing the other side of the redundancy signal; Count-comparing units 17A and 18A which indicate whether an input signal is error by comparing a value counted by the latch-inverting unit 16A with a signal before inverting in the latch-inverting unit 16A. 2) A device for detecting a clock error through mutual monitoring between duplicated clocks without an external clock source, wherein each block is configured to check whether each of the duplicated signals has an error. The method of claim 1, The first divider 11A and the second divider 12A divide the input signal into two by using a D-flip flop, respectively. Device to detect it. The method of claim 1, wherein the count-comparison portion 17A, 18A, A counter 17A set to send an output whenever the signal inverted in the latch-inverting section 16A is counted by a certain number; When the output value of the counter 17A is input to the J terminal and the signal before the inversion of the latch-reversal unit 16A is input to the K terminal, when the input signal to the corresponding unit is normal, '0' is output and abnormal. In the case of the device that detects the clock error through the mutual monitoring between the dual clock without an external clock source, characterized in that consisting of JK-flip-flop (18A) that outputs a '1'. A reset signal stage (25, 26, 27) for outputting a clock active signal and an asynchronous reset signal by using a read active signal and a test clock supplied from an external processor; A plurality of D-flip flops 21, 22, 23, 24, which are reset by an asynchronous reset signal output from the reset signal stages 25, 26, 27 and generate an output corresponding to a read active signal and a test clock, are connected in series. Apparatus for detecting a clock error through monitoring using an external processor without an external clock source, characterized in that consisting of. The method of claim 4, wherein the reset signal stage (25, 26, 27), Inverting the read active signal to generate a clock active signal, Through two series-connected D-flip flops 25 and 26, the read active signal is read and logically computed by a test clock to generate an asynchronous reset signal. The monitoring is performed using an external processor without an external clock source. Device that detects clock errors. The method of claim 4, wherein Each output of the plurality of D-flip flops 21, 22, 23, and 24 connected in series is read by an external processor, and when there is a constant transition pattern such as '0101' or '1010', a normal operation of the external input signal is performed. And determining, when the pattern is equal to '0000', a clock error through monitoring using an external processor without an external clock source, wherein the external input signal is abnormal. In operating a device that detects clock errors without an external clock source, Performing error checking on the redundant clock through mutual monitoring; If an error occurs in one of the duplicated clocks, checking whether the other error occurs through monitoring using an external processor; And performing an appropriate action when an abnormality is detected on both sides of the redundant clock by performing the above steps. The method of claim 7, wherein When it is confirmed that an abnormality occurs in only one clock as a result of monitoring using an external processor, a clock error is detected without an external clock source, by periodically monitoring the external processor to check whether each of the redundant clocks is in error. How to operate the device. The method of claim 8, If the error of the clock is eliminated as a result of performing periodic monitoring using the external processor, the method of operating an apparatus for detecting a clock error without an external clock source, returning to the step of performing error checking through mutual monitoring. .