KR20020013303A - Semiconductor device handler system - Google Patents

Abstract

PURPOSE: A semiconductor device handler system is provided, which enables a semiconductor device test process to be performed accurately by preventing an overload on a central processing unit, and also prevents a facility down. CONSTITUTION: According to the semiconductor device handler system(200), a test unit(210) performs a reliability test for testing a semiconductor device in a worse environment after other processes like a silicon substrate fabrication process, a semiconductor chip fabrication process and a packaging process are ended. A device transport unit(220) loads the semiconductor device onto the test unit or unloads the semiconductor device from the test unit. A manual operation unit(240) performs a change of the internal environmental condition in the test unit or a processing sequence. A central processing unit(260) applies an optimum control signal to each component, thus it can reduce an exhaustion time of the semiconductor device after its test is ended.

Description

Semiconductor device handler system

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device handler system, and more particularly, to temperature control of a semiconductor device handler, which has a great influence on the processing load of a central processing unit that manages a series of processes of externally loading, testing, and unloading a semiconductor device. The present invention relates to a semiconductor device handler system in which an area and a manual operation area are divided and controlled by an integrated sub-controller to reduce the load of the central processing unit so that a test process failure and a test process down due to a malfunction of the central processing unit do not occur.

Recently, with the rapid development of the industry, the enormous amount of data to be processed gradually increases, and the necessity of processing the enormous data faster and storing the enormous data in a very small area is gradually increasing.

This need is overcome by semiconductor devices, which test the process of fabricating a plurality of semiconductor chips with highly integrated semiconductor elements on pure silicon wafers, packaging semiconductor chips, and whether the packaged semiconductor chips are operating normally. It is produced through a test process.

In particular, the test process includes verification of whether the semiconductor device operates normally in a room temperature environment, as well as verification whether the semiconductor device operates normally in a special environment, for example, a high temperature environment or a low temperature environment.

This testing process is usually done by a test facility called a test handler.

Such a test facility 100 is a test unit 110, the test unit 110 of the test unit 110 to be tested under a predetermined environment, for example, a semiconductor device that has completed the preceding process, for example, the packaging process, as conceptually shown in FIG. The semiconductor device is loaded and tested in the test unit 110 with the test environment setting unit 120, the test unit 120, which sets the environment, that is, maintains the test environment appropriately such as the internal temperature of the test unit 110. A device transfer unit group 130 for allowing the loaded semiconductor device to be unloaded and transferred to a subsequent process, a manual operation unit 140 arranged to change a test operation including a change in a test environment, and a central processing unit 150 for controlling the whole thereof It consists of.

In this case, the test environment setting unit 120 is a heater unit (not shown) that heats the interior of the test unit 110 so that the test is performed under the environment designated by the test unit 110, and is currently inside the test unit 110. It needs a temperature sensor 110 to detect the temperature of the.

At this time, the central processing unit 150 receives a sensing signal associated with the current state of the current test unit 110 from the temperature sensor at a predetermined unit time, and generates a control signal for controlling the heater unit accordingly. Since the test is repeated every unit time, the test environment setting unit 120 acts as a factor to increase the load of the central processing unit 150, in particular, compared to other units.

However, such a load weighting of the central processing unit 150 by the test configuration unit 120 immediately causes a process delay of the test handler facility 100 having a sequenced data flow and a control flow, so that the overall process progress is accurate. It is not made or there is a problem that causes downtime.

Accordingly, the present invention has been made in view of such a conventional problem, and an object of the present invention is to prevent an excessive load on the central processing unit so that the semiconductor device test process proceeds accurately and at the same time prevent facility downtime.

Other objects of the present invention will become more apparent from the following detailed description of the invention.

1 is a conceptual diagram of a conventional semiconductor device handler system.

2 is a conceptual diagram of a semiconductor device handler system according to the present invention;

The semiconductor device handler system for realizing the object of the present invention includes a test unit for testing a semiconductor product and a device transfer for loading a semiconductor product into the test unit and unloading the semiconductor product after the test is terminated in the test unit. A test environment setting unit composed of a unit, a temperature sensing sensor and a heater unit installed inside the test unit to create a test environment inside the test unit, a manual operation unit for changing test conditions, a test environment setting unit, and a manual And an integrated sub controller for directly controlling the operation unit, and a central processing unit for controlling the integrated sub controller, the test unit, and the device transfer unit.

Hereinafter, a semiconductor device handler system 200 according to the present invention will be described with reference to FIG. 2.

The semiconductor device handler system 200 according to the present invention generally includes a test unit 210, a device transfer unit 220, a test environment setting unit 230, a manual operation unit 240, and a test environment setting unit 230. And an integrated sub controller 250 for controlling the manual operation unit 240 and a central processing unit 260 for controlling these components as a whole.

More specifically, the test unit 210 is a silicon substrate fabrication process-semiconductor chip manufacturing process-the semiconductor device after the packaging process is completed in a poor environment by testing a semiconductor device subjected to the preceding process, for example, in a predetermined environment It is responsible for conducting a reliability test on whether the system is operating normally.

Meanwhile, the device transfer unit 220 loads or unloads the semiconductor device into the test unit 210 or unloads it from the test unit 210 in order to allow the test of the semiconductor device to proceed in the test unit 210 performing such a role. Play a role.

Meanwhile, the test environment setting unit 230 is installed in the test unit 210 to test the semiconductor device in a predetermined environment, and the test environment setting unit 230 increases the temperature inside the test unit again. And a temperature sensing sensor 233 for operating the unit 235 and the heater unit 235.

The manual operation unit 240 performs a change in environmental conditions or a change in the process order of the test unit 210.

At this time, the central processing unit 260 applies the optimum control signal to each of the above-described components, so that all the components are classified after the test of the semiconductor device put into the test unit 210 for testing under the sequence control This reduces the overall time it takes to discharge.

In order to implement such an action faithfully, in the present invention, the test environment setting unit 230 and the manual operation unit 240 that generate a large load on the central processing unit 260 are separately controlled by the integrated sub-controller 250. As a result, the load on the central processing unit 260 can be minimized.

In order to implement this, the integrated sub controller 250 has a sub central processing unit 252 and a storage unit 254 in which data is temporarily stored, and the integrated sub controller 250 and the test environment setting unit 230 are integrated. The sub-controller 250 and the manual operation unit 240 should allow data flow and control flow to occur in both directions by the RS-232C protocol in one embodiment.

For example, the temperature inside the test unit 210 sensed by the temperature sensor 233 installed inside the test unit 210 is input to the integrated sub-controller 250 as data in the form of an electrical signal to store the memory device ( When temporarily stored in the 254, the integrated sub-controller 250 calls the test unit internal temperature data stored in the memory 254 to perform a comparison operation with the preset temperature data, and then stores the current inside the test unit 210. When it is determined that the temperature is lower than the preset temperature, more power is applied to the heater unit 235 to transmit a control signal to the heater unit 235 to increase the amount of heat generated by the heater unit 235.

However, if the temperature sensing sensor 233 or the heater unit 235 causes abnormal operation, that is, the test unit 210 does not currently perform the normal test process, the process is repeated. The sub controller 250 does not process this alone, but passes the control right to the CPU 260.

That is, when this condition occurs, the central processing unit 260 no longer supplies the semiconductor device from the device transfer unit 220 operating in association with the test unit 210 until the test unit 210 is in a normal state. In order not to apply a predetermined control signal to all components associated with the test unit 210 to temporarily stop the test process.

As described above in detail, there is an effect of reducing the load on the central processing unit and preventing an abnormality in the process of testing the semiconductor device according to the overload of the central processing unit and the equipment down.

Claims (2)

A test unit in which a test of a semiconductor product is performed; A device transfer unit for loading the semiconductor product into the test unit and for unloading the semiconductor product after the test is terminated in the test unit; A test environment setting unit composed of a temperature sensor and a heater unit installed inside the test unit to create a test environment inside the test unit; A manual operation unit for changing the test condition; An integrated sub controller which directly controls the test environment setting unit and the manual operation unit; And a central processing unit for controlling said integrated sub-controller, said test unit, and said device transfer unit. The semiconductor device handler system of claim 1, wherein the integrated sub controller comprises a memory device for storing data generated by the test environment setting unit and the manual operation unit, and a sub central processing device for processing the data.