KR20020012652A - Ac surface discharge plasma display panel, method of driving ac surface discharge plasma display panel, plasma display device and method of manufacturing ac surface discharge plasma display panel - Google Patents

Abstract

PURPOSE: An AC Surface discharge type plasma display panel, driving method for AC Surface discharge type plasma display panel, plasma display device and method for producing AC Surface discharge type plasma display panel are provided to reduce cost by eliminating the necessity of arranging a driver circuit for each address electrode, while obtaining a high definition display. CONSTITUTION: An AC Surface discharge type plasma display panel comprises a first substrate(51Rd) is disposed on address auxiliary electrodes(47T,47B) formed on a surface(9S) of a rear glass substrate(9) all over the adjacent lane regions(ARLm-2,ARLm-1) and identical regions(ARLm,ARLm plus 1), and on a surface(15S) of an insulation layer(15) all over the adjacent lane regions(ARLm minus 1,ARLm) and identical regions(ARLm plus 1,ARLm plus 2); and a common address electrode(46) where a voltage for image data is applied. In the PDP having the first substrate, a light discharge occurs only in the discharge cell where the common address electrode and address auxiliary electrodes belong. A voltage is applied to each of the common address electrode and the address auxiliary electrodes, during the former half(or later half) of address period.

Description

AC surface discharge type plasma display panel, AC surface discharge type plasma display panel driving method, plasma display device and manufacturing method of AC surface discharge type plasma display panel {AC SURFACE DISCHARGE PLASMA DISPLAY PANEL DEVICE AND METHOD OF MANUFACTURING AC SURFACE DISCHARGE PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and a driving method of an AC type PDP that is optimal for high definition of an AC surface discharge type plasma display panel (hereinafter also referred to as an "AC type PDP" or just a "PDP"). The present invention relates to the reduction of the number, the reduction of the pattern density with respect to the address electrode, and the high speed of the write (write) operation.

Fig. 31 is an exploded perspective view showing the structure of a conventional conventional AC PDP.

As shown in Fig. 31, in the conventional AC type PDP 51P (hereinafter also referred to simply as "PDP 51P"), the front panel 51FP and the back panel 51RP are formed of the cathode film 4P and the barrier ribs. The top of 7P is disposed to abut, and forms a discharge gas space or a discharge space 51SP. The front panel 51FP and the rear panel 51RP are sealed at their periphery, not shown, and the Ne-Xe mixed gas or the He-Xe mixed gas in the discharge space 51SP. Discharge gases, such as these, are enclosed.

On the front panel 51FP, on the surface of the discharge space 51SP side of the front glass substrate 5P forming the display surface, 2N strip transparent electrodes 1P are mutually aligned along the second direction D2 parallel to this surface. It is formed in parallel. Moreover, the strip | belt-shaped bus electrode 2P which consists of a metal material for supplementing the electroconductivity of the transparent electrode 1P on the surface of the discharge space 51SP side of the transparent electrode 1P, and supplying a voltage to the said electrode 1P. It is formed along this transparent electrode 1P. The (multiple) electrodes of the structure consisting of the transparent electrode 1P and the bus electrode 2P are paired with each other adjacent to each other, and one pair of the above electrodes forms one scanning line or display line. have. At this time, as shown in Fig. 31, the n-th (1? N? N) scan line SLn is composed of two electrodes Xn and Yn paired with each other. In addition, each bus electrode 2P of the electrodes Xn and Yn is a part on the surface of the transparent electrode 1P adjacent to the scan line SLn, SLn + 1 side, that is, the position farthest from the central axis of the scan line SLn. It is formed in. Moreover, the area | region between the edge which opposes each other of electrode pair Xn, Yn (each transparent electrode 1P) (it includes the three-dimensional area | region in 3rd direction D3 perpendicular | vertical to the said surface of front glass substrate 5P) Is referred to as the "internal gap G".

The dielectric 3P is formed over the entire surface of the front glass substrate 5P so as to cover the transparent electrode 1P and the bus electrode 2P, and the discharge space 51SP of the dielectric 3P is formed. On the surface of the side, an MgO vapor deposition film or cathode film 4P, which functions as a cathode during discharge, is formed.

On the other hand, in the back panel 51RP, on the surface of the discharge space 51SP side of the back glass substrate 9P, in the first direction D1 orthogonal to the second and third directions D2 and D3, that is, the electrodes Xn and Yn M light electrodes 6P or address electrodes Am (1 ≦ m ≦ M) each having the same width in the direction orthogonal to each other are formed to extend, and the rear glass substrate 9P covers the address electrodes 6P. A glaze layer or overglaze layer 10P made of a dielectric material is formed over the entire surface of the surface of the N-type. Then, the barrier ribs 7P are formed on the surface of the discharge space 51SP side of the overglaze layer 10P positioned in the region between the adjacent address electrodes 6P. In addition, each fluorescent color of red, green, and blue is formed on the sidewall faces of the adjacent barrier ribs 7P facing each other and on the surface of the overglaze layer 10P held between the adjacent barrier ribs 7P. Phosphors or phosphor layers (8RP), (8GP), (8BP) (collectively referred to as "phosphor (layer) 8P") which emit light are formed.

In the PDP 51P, the structure at each point where the scan line formed by the electrode pair and the address electrode 6P intersect three-dimensionally forms one discharge cell or light emitting cell as one pixel in the display panel. A large number of discharge cells are arranged in a matrix to form a screen or display area of the PDP 51P. In the following description, the discharge cells or light emitting cells at positions where the scan lines SLn (hence, electrode pairs Xn and Yn) and the address electrodes Am intersect three-dimensionally are referred to as "discharge cells of address (n, m) or light emitting cells". do. By applying a predetermined voltage to each of the electrodes Xn, Yn, and Am, a discharge is generated in the discharge space 51SP of the discharge cells at the addresses (n, m).

As an example of the driving method of the PDP, there is a method of dividing and driving the image display time of one screen into several subfields each having an erasing period, an address period, and a sustain period. In such a driving method, first, the display history of the immediately preceding subfield is erased in the erasing period. In the subsequent address period, information on whether or not to generate sustain discharge in the subsequent sustain period is given to each discharge cell in accordance with the input image data. At this time, a voltage (-Vy) is sequentially applied to the electrode Yn (the electrode Xn is also referred to as the "holding electrode Xn") as the scan electrode, and the predetermined voltage Von corresponding to the input image data is applied to the address electrode Am, or By applying Voff, the above information is recorded for all the discharge cells. Specifically, a light counter discharge is generated between the address electrode Am to which the voltage Von according to the image data in the ON state is applied and the scan electrode Yn to which the voltage (-Vy) is applied. The light discharge is generated between the electrode pairs Xn and Yn by triggering such a counter discharge, and the wall charges as the information are accumulated on each surface of the cathode film 4P positioned above the electrodes Xn and Yn. (At this time, voltage Vx is applied to sustain electrode Xn). In the subsequent sustain period, the image display of the PDP is executed by generating sustain discharge that is responsible for display light emission in the discharge cells in which the information is recorded.

However, in the conventional AC surface discharge type PDP, one discharge cell is formed at a portion where the address electrode 6P and the scan line or the display line intersect in three dimensions. The plurality of address electrodes 6P are electrically independent of each other, and the conventional plasma display device includes an address driver having output bits or output terminals as many as the number of such address electrodes 6P. This address driver generally consists of a drive IC for one or several address electrodes. At this time, when a high-definition display such as full-spec high-definition is composed of a plasma display device, a driver IC for address electrodes having a total of 5760 output bits is required. There is a problem that the ratio of the driving IC for the address electrode to the total cost of the entire plasma display apparatus is very large.

In addition, when the size of the PDP (the display area) is the same, the pattern density of the address electrode 6P increases with the high definition of the PDP, making it difficult to form the same pattern accurately. In addition, since the wiring from the terminal of the address electrode 6P to the output terminal of the drive IC for address electrodes is also high density, a higher degree of high density mounting technique is required for such wiring. In addition, ion migration of terminal electrode materials, which occurs when high loads and high voltages are applied between adjacent terminals, may occur in each terminal formed in a fine pattern.

In addition, the high definition of the PDP causes the following problems with respect to its driving method. First, in the write operation period or the address period, in order to stably perform the write discharge or the address discharge by the selected predetermined scan line, the pulse application time of the voltage Von or Voff applied to the address electrode Am or the sustaining period forming the selected scan line is maintained. It is necessary to lengthen the pulse application time of the voltage (voltage value (-Vy)) applied to a discharge electrode with high definition. This is a delay time from the time when each pulse of the voltage Von and the predetermined voltage (-Vy) is input to each of the address electrode Am and the scan electrode Yn until the write counter discharge between the address electrode Am and the scan electrode Yn occurs. Because it is longer. The following (a) and (b) are estimated as a cause of such an increase of delay time.

(a) In the case where the size of the PDP (display area) is the same, high definition generally involves narrowing of the line width or width (length along the second direction D2) of the address electrode 6P (see FIG. 31). do. At this time, even when the same potential difference is provided (that is, even if the number of equipotential lines is the same), the narrower the width of the address electrode Am, the more equipotential line distribution in the discharge space between the address electrode Am and the scan electrode Yn is obtained at the address electrode Am side. It becomes more compact. In particular, the electric field strength near the discharge space in contact with the cathode film 4P above the scan electrode Yn becomes smaller, and the range of the electric field having the strength necessary for initiating the counter discharge between the electrodes Am and Yn is narrowed. That is, since the influence on the electric field formation of the applied voltage to the address electrode Am decreases in the vicinity of the discharge space in contact with the cathode film 4P (at this time, the above influence of the applied voltage to the scan electrode Yn increases relatively). ), The weakening of the electric field strength near the discharge space in contact with the cathode film 4P, which plays an important role in initiating the counter discharge between the electrodes Am and Yn, is remarkable.

(b) Further, for example, when the voltage Von is applied to the address electrode Am according to the input image data, but the voltage Voff is applied to both the address electrodes Am-1 and Am + 1 adjacent to both sides, the address electrode Am is Light discharge in the belonging discharge cell becomes less likely to occur. This is because the electric field due to the voltage Voff applied to the address electrode Am-1 and the address electrode Am + 1 is an inhibitory factor for the electric field formation in the discharge space between the address electrode Am to which the voltage Von is applied and the scan electrode Yn of the selected scan line. Because it becomes. This inhibition factor increases as the sharper the smaller the pitch between the adjacent electrodes or the electrode gap between the address electrodes Am-1, Am, Am + 1.

As a method for excluding the causes of (a) and (b) above, even when the pattern density of the address electrode 6P increases with high definition, the space that is the area between the electrode patterns of the adjacent address electrodes 6P ( A method of suppressing narrowing of the line width of the address electrode 6P by narrowing the width of the space) area is considered.

However, from the viewpoint of the manufacturing process, in the case of pattern forming the address electrode 6P on a large area back glass substrate 9P with a high density, the space which is the line width of the address electrode 6P and the width of the space region. It is very difficult to significantly narrow either of the width or the width (the length along the second direction D2 of this region). For example, in the case of full spec high vision having a display area of 16: 9 with a size of about 116 cm diagonal, the area allocated as the line width and the space width for one address electrode 6P is 176 mu m. Even if this is equally allocated (allocated), the width dimension applied to the line width and the space width is 88 탆 each. When a band-shaped address electrode is patterned on a glass substrate having a large area of about 116 cm at such a width dimension, sufficient formation process margin is difficult to secure. In other words, even in such a dimension, it is very difficult to further narrow the space width in a situation where the formation of the address electrode and the space region itself is difficult.

In addition, as one of the other methods by which the causes of (a) and (b) can be eliminated, the voltage Vy and the voltage Von are increased to increase the applied voltage (Von + Vy) between the electrodes Am and Yn. The method of making it is considered.

However, when the voltage value Vy is increased, the voltage (Voff + Vy) increases, so that image data is incorrectly written in the off-state discharge cell (hereinafter referred to as "light misfiring" or "orlight discharge"). It becomes easy to occur). In order to cope with this, when the voltage value Voff is lowered, the switching voltage width (Von-Voff) at the time of driving the address electrode driver IC increases, so that the load of the driver IC becomes larger. In addition, the effect of the electric field by the voltage applied to the address electrodes Am-1 and Am + 1 described in the above (b) on the electric field formation in the discharge cell to which the address electrode Am belongs increases.

On the other hand, when the voltage value Von is increased, the switching voltage width Von-Voff increases, so that the load of the address IC driver IC increases. When the voltage value Voff is increased in order to reduce such a load, the voltage Voff + Vy becomes large, which causes a problem that the above-described discharge is easy to occur. When the voltage value Von is increased, for example, when there is a discharge cell in which the image data in the on state is recorded on both sides of the discharge cell in which the image data in the off state is recorded, each address electrode ( The voltage Von applied to 6P) forms a stronger electric field in the discharge cells therebetween. As a result, even when the voltage value Von is made large, the above-described discharge is easily generated.

In this way, as the sharpening progresses, the degree to which the respective factors such as the reduction in the load of the address electrode driver IC, the easy rise of the normal light discharge and the suppression of the ore discharge increases. For this reason, in order to satisfy all such factors, the probabilistic delay time of occurrence of (normal) light discharge is increased by lengthening the application time of these pulses without changing the voltage value Von or Voff or the voltage value Vy. The way to complement them is considered. That is, the pulse application time is set longer than the delay time.

However, in view of the increase in the number of scanning lines with higher definition, the longer the write time for one scanning line, the larger the time occupancy rate of the address period in the subfield. At this time, when the number of subfields is made to be the same as the conventional driving method in order to avoid the reduction of the number of gray scales, there is a need to reduce the time allotted as the sustain period. Moreover, in order to avoid the fall of display luminance, when the pulse number of the sustain pulse in the sustain period is also set in the same manner as in the conventional driving method, it is necessary to shorten the period of the sustain pulse applied to the electrodes Xn and Yn. However, in such a case, there arises a problem that the sustain discharge becomes unstable.

On the other hand, by reducing the number of field divisions in one screen, a driving method of reducing the number of gradations compared to the conventional driving method is considered. According to such a driving method, sufficient time can be given also reliably about light discharge or sustain discharge. However, it is not possible to sufficiently exhibit the excellent image quality originally possessed by the high definition PDP by the number of gray scales reduced.

As described above, it can be said that it is very difficult to satisfy all of most of the above-mentioned elements in a high-definition AC surface discharge type PDP or a plasma display device having the same. Under such circumstances, in order to realize high quality display image quality in the current PDP, a driving method that increases the voltage Von and lowers the voltage Voff in many cases is often employed. In other words, the priority of reducing the load of the drive IC for address electrodes is set slightly lower. For this reason, what can endure high load as a drive IC for address electrodes is used abundantly, and the ratio which the said drive IC in the cost or price of a plasma display apparatus occupies is very large.

Accordingly, an object of the present invention is to provide an AC surface discharge type plasma display panel suitable for high definition and a driving method thereof, a method of manufacturing such a panel, and a plasma display device to which the driving method is applied. . And in order to achieve such a main objective, this invention has the following further detailed objective.

First, the present invention provides an AC surface discharge type plasma display panel having a structure capable of reducing the number of address electrode drive circuits (drive ICs) in a conventional PDP. It is to provide a driving method applied to.

Further, a second object of the present invention is to provide an AC surface discharge type plasma display panel and a driving method thereof capable of further realizing the above-described first object and speeding up the recording operation.

The third object of the present invention is to provide an AC surface discharge type plasma display panel capable of realizing the first object, and has an AC surface discharge type plasma display panel having a structure in which the pattern density of the address electrode in the conventional PDP is reduced. To provide.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view for explaining a subfield division form of one screen and each period within each subfield in the method of driving an AC PDP according to the prior art of the present invention.

Fig. 2 is a timing diagram showing signal waveforms applied to each electrode in a subfield in the method for driving an AC PDP as a prerequisite of the present invention.

3 is a timing chart showing signal waveforms applied to respective electrodes in a subfield in another driving method of an AC PDP as a prerequisite of the present invention;

4 is a diagram for explaining a form of counter discharge between a scan electrode and an address electrode;

5 is a diagram for explaining a form of surface discharge between electrode pairs;

6 is a longitudinal sectional view schematically showing a structure in a display area of an AC PDP according to the first embodiment;

7 is a plan view schematically showing the arrangement of the electrodes of the first substrate according to the first embodiment;

8 is a timing chart showing waveforms of voltages applied to respective electrodes in an address period in the AC type PDP driving method according to the first embodiment;

9 is a plan view schematically showing an arrangement of electrodes in a first substrate according to Modification Example 1 of Example 1;

10 is a longitudinal sectional view schematically showing a structure in a display area of a first substrate according to a second embodiment;

FIG. 11 is a longitudinal sectional view schematically showing a structure in a display region of a first substrate according to Example 3; FIG.

12 is a longitudinal sectional view schematically showing a structure in a display area of a first substrate according to a fourth embodiment;

13 is a longitudinal sectional view schematically showing a structure in a display area of a first substrate according to a fifth embodiment;

FIG. 14 is a diagram schematically showing a correlation between an overlap amount between a common address electrode and an address auxiliary electrode, an electric field formation influence in a capacitance, and a discharge cell; FIG.

15 is a longitudinal cross-sectional view for illustrating each step in the first manufacturing method of the first substrate according to the sixth embodiment;

16 is a longitudinal cross-sectional view for explaining each step in the first manufacturing method of the first substrate according to the sixth embodiment;

17 is a longitudinal cross-sectional view for illustrating each step in the first manufacturing method of the first substrate according to the sixth embodiment;

18 is a longitudinal cross-sectional view for illustrating each step in the first manufacturing method of the first substrate according to the sixth embodiment;

19 is a longitudinal cross-sectional view for explaining each step in the second manufacturing method of the first substrate according to the sixth embodiment;

20 is a longitudinal cross-sectional view for explaining each step in the second manufacturing method of the first substrate according to the sixth embodiment;

21 is a longitudinal cross-sectional view for explaining each step in the second manufacturing method of the first substrate according to the sixth embodiment;

FIG. 22 is a longitudinal sectional view schematically showing a structure in a display region of a first substrate according to Example 7; FIG.

FIG. 23 is a longitudinal sectional view schematically showing a structure in a display area of a first substrate according to Example 8; FIG.

24 is a plan view schematically showing the arrangement of the electrodes of the first substrate according to the eighth embodiment;

25 is an enlarged plan view schematically showing the structures near the lead-out area and the terminal area of the first substrate according to Modification Example 1 of Example 8;

FIG. 26 is a view when the longitudinal section in the line I-I in FIG. 25 is viewed from the arrow direction; FIG.

27 is an enlarged plan view schematically showing the structures near the lead-out area and the terminal area of the first substrate according to Modification Example 2 of Example 8;

28 is a view of a longitudinal section taken along the line II-II in FIG. 27 as viewed in the arrow direction;

29 is a timing chart showing waveforms of voltages applied to respective electrodes in a sustain period in the AC type PDP driving method according to the ninth embodiment;

30 is a view for explaining a subfield division form of one screen and each period within each subfield in the method for driving an AC PDP according to the tenth embodiment;

Fig. 31 is an exploded perspective view schematically showing the structure of an AC type PDP according to the prior art.

Explanation of symbols for the main parts of the drawings

1 transparent electrode 2 bus electrode

3, 3A: dielectric (layer)

Surface: 1S, 3SA, 4S, 5S, 9S, 9S2, 10S, 15S, 35S, 75S, 175S

4: cathode film 5: front glass substrate

6, Am: address electrode 7, Bm: barrier rib

8 phosphor (layer) 9 back glass substrate (substrate)

10: over glaze layer 15: interlayer insulating layer

16, 26, 36, 46, 56, 66, 76, PAk: common address electrode

17B3, 17T3, 77B3, 77T3, 163, 763: terminals

16T, 26T, 36T, 66T: first common address electrode

16B, 26B, 36B, 66B: second common address electrode

17, 27, 37, 47, 57, 67, 77: address auxiliary electrode

17B, 27B, 37B, 47B, 57B, 67B, 77B: second address auxiliary electrode

17T, 27T, 37T, 47T, 57T, 67T, 77T: first address auxiliary electrode

17B2, 17T2, 77B2, 77T2: common electrode part (wiring part)

17BA, 17TA: overlapping parts

17BB, 17TB: non-overlapping parts

35, Lm: lane 51F: second substrate

First substrate: 51Ra, 51Ra2, 51Rb, 51Rc, 51Rd, 51Re, 51Rf, 51Rg

51S: discharge space

156, 256: photosensitive conductor paste (photosensitive material)

101, 201: positive resist (photosensitive material)

75, 175: insulating film 177T, 277T: wiring portion

356: conductor material AD0: address period

AD1: first period (address period)

AD2: Second period (address period)

AR1, AR11, AR12: display area

AR21, AR22: lead-out area AR3, AR31, AR32: terminal area

AR4: Area ARLm: Lane Area

BL: block CB, CT: discharge cell

D1: first direction D2: second direction

D3: third direction DC1: counter discharge (light discharge)

DC2: Surface discharge (hold discharge) R, RA, RB: Erasure period

S0: Holding period SF1 to SF8, SF8A, SF8B: Subfield

Xn: sustain electrode Yn: scan electrode

Von: first voltage Voff: second voltage

Vh: third voltage Vl: fourth voltage

Va, VB, VT, VPAk, VX0, VY0, VY1 to VYN, Vx, Vy: Voltage

[1] An AC surface discharge type plasma display panel according to the present invention is arranged in parallel with each other in a display area on at least one surface side of a substrate and the substrate, and each of the first to s (s is an integer of 2 or more) common addresses. A first substrate having a plurality of band-shaped common address electrodes classified into groups consisting of electrodes, and a plurality of band-shaped address auxiliary electrodes each classified into groups consisting of first to s-address auxiliary electrodes, each parallel to each other And a plurality of electrode pairs formed of a band-shaped scan electrode and a sustain electrode arranged in a direction three-dimensionally intersecting the common address electrode and the address auxiliary electrode, and a dielectric disposed to cover the plurality of electrode pairs. The second substrate is between the first substrate and the second substrate. Spaces are arranged through barrier ribs that divide a space into a plurality of discharge spaces filled with discharge gas along the longitudinal direction of the common address electrode and the address auxiliary electrode, and each of the two adjacent barrier ribs is in a longitudinal direction; And a plurality of discharge cells formed by each of the intersections of the pair of electrodes and the lane area defined as the area between the centers in the plurality of lanes, wherein the plurality of lane areas are located in the jth (1 ≦ j ≦ s) lane area. And at least a portion of the j th common address electrode and at least a portion of the j th address auxiliary electrode are classified into a group consisting of first to s lane regions.

[2] The present invention provides the AC surface discharge type plasma display panel according to the above [1], wherein the first to s common address electrodes are connected in common to each of the group units and belong to each of the plurality of groups. The j address auxiliary electrode may be connected in common between the groups.

[3] The present invention provides the AC surface discharge type plasma display panel according to the above [1] or [2], wherein the plurality of common address electrodes and the plurality of address auxiliary electrodes each pass through an insulating layer in the display area. It is arrange | positioned on a plane.

[4] The present invention provides an AC surface discharge type plasma display panel according to the above [3], wherein the plurality of common address electrodes and the plurality of address auxiliary electrodes are arranged such that the first substrate is perpendicular to the surface of the substrate. In this case, the display area does not have portions overlapping each other.

[5] The present invention provides the AC surface discharge type plasma display panel according to the above [4], wherein the display area is the common address electrode and the address when the first substrate is viewed in a direction perpendicular to the surface of the substrate. It is characterized in that the auxiliary electrode is completely filled without a gap (gap).

[6] The present invention provides the AC surface discharge type plasma display panel according to [1] or [2], wherein the common address electrode and the address auxiliary electrode are arranged on the same plane in the display area. do.

[7] The present invention provides an AC surface discharge type plasma display panel according to any one of the above [1] to [6], wherein at least a portion of one of the plurality of jth address auxiliary electrodes belongs to. In the lane area adjacent to the lane area, at least a part of the other j-th address auxiliary electrodes of the plurality of j-th address auxiliary electrodes is not disposed.

[8] The present invention provides the AC surface discharge type plasma display panel according to the above [7], wherein the plurality of address auxiliary electrodes are each arranged at a predetermined pitch along the width of the lane region in an arrangement direction. And the first and second address auxiliary electrodes arranged alternately.

[9] The present invention provides an AC surface discharge type plasma display panel according to any one of [1] to [6], wherein at least a part of one of the jth address auxiliary electrodes of the plurality of jth address auxiliary electrodes belongs. At least a part of the other j-th address auxiliary electrodes of the plurality of j-th address auxiliary electrodes is disposed in at least one of the lane areas on both sides adjacent to the lane area.

[10] The present invention provides the AC surface discharge type plasma display panel according to the above [9], wherein each of the plurality of address auxiliary electrodes is arranged at a predetermined pitch along the width of the lane area in the same direction and is the same. It is characterized in that it is classified into first and second address auxiliary electrodes alternately arranged in two units of two kinds of electrodes.

[11] The present invention is the AC surface discharge type plasma display panel according to any one of the above [1] to [10], wherein one entire common electrode is disposed in each lane area.

[12] The present invention provides an AC surface discharge type plasma display panel according to any one of [1] to [10], wherein at least one of the common address electrode and the address auxiliary electrode is disposed in two adjacent lane areas. It is characterized by having a pattern shape.

[13] The present invention provides the AC surface discharge type plasma display panel according to the above [1] or [2], wherein the plurality of address auxiliary electrodes are classified into first and second address auxiliary electrodes, and the first address auxiliary electrode. Further comprises a wiring portion extending from one side of the longitudinal direction in the display region and reaching the terminal for the first address auxiliary electrode disposed outside the display region; The second address auxiliary electrode extends along the long direction in the display area to the other side of the long direction to reach the terminal for the second address auxiliary electrode disposed outside the display area. It is characterized by further comprising a part.

[14] The present invention provides an AC surface discharge type plasma display panel according to [1] or [2], wherein each of the plurality of common address electrodes and the plurality of address auxiliary electrodes is formed at one end of each of the electrodes. It further comprises a wiring part leading to each said terminal for electrodes arrange | positioned outside of a display area, Each said wiring part is arrange | positioned electrically separated from each other by the insulating layer arrange | positioned outside the said display area.

[15] A plasma display device according to the present invention includes the AC surface discharge type plasma display panel according to any one of [1] to [14].

[16] A method of driving an alternating current surface discharge plasma display panel according to the present invention is a method of driving the alternating surface discharge plasma display panel according to the above [1] or [2], wherein the display time for one screen is divided into several. After dividing into subfields, each of the plurality of subfields generates an address period for generating a light discharge according to image data in a predetermined discharge cell at least in synchronization with a selective scan of the scan electrode and the discharge in which the light discharge has occurred. When the cell has a sustain period for generating a predetermined number of sustain discharges, the first voltage or the second voltage according to the image data of the discharge cells belonging to the j-th lane area of each group in the address period. Any one of the first to second voltages belonging to the group in the group unit; When a common voltage is applied to the s common address electrode, a third voltage is applied to the jth address auxiliary electrode, and a voltage value different from the third voltage is applied to the address auxiliary electrodes other than the jth address auxiliary electrode. It is characterized by applying a fourth voltage having.

[17] The present invention provides a method of driving an AC surface discharge type plasma display panel as described in [16], wherein both the common address electrode to which the first voltage is applied and the address auxiliary electrode to which the third voltage is applied are provided. The first to fourth voltages may be set to generate the light discharge only in the discharge cells belonging to the lane area.

[18] The present invention provides a method of driving an AC surface discharge type plasma display panel according to the above [16] or [17], wherein the driving method for the j th lane area is applied to each of the first to s th lane areas. It is characterized in that for executing.

[19] The present invention provides a method of driving an alternating current surface discharge plasma display panel according to the above [16], wherein at least one of the subfields of the plurality of subfields that constitutes the video display time for one screen is performed. In the address period, the light discharge is generated only in the discharge cells belonging to the predetermined t (t is an integer less than or equal to s) of the first to s-lane areas.

[20] A method of driving an alternating current surface discharge plasma display panel according to the present invention is a method of driving an alternating current surface discharge plasma display panel according to the above [1] or [2]. After dividing into fields, an address period in which each of the plurality of subfields generates light discharge in accordance with image data in a predetermined discharge cell in synchronization with at least a selective scan of the scan electrode and the discharge cell in which the light discharge has occurred. In the case of having a sustain period for generating a predetermined number of sustain discharges, the same voltage is applied to both the common address electrode and the address auxiliary electrode in the sustain period.

[21] A plasma display device according to the present invention is characterized in that the method of driving the AC surface discharge type plasma display panel according to any one of the above [16] to [20] is applied.

[22] A method of manufacturing an AC surface discharge type plasma display panel according to the present invention is a method of manufacturing an AC surface discharge type plasma display panel according to [5], wherein the method of manufacturing the first substrate includes (a) the common address electrode. Or (b) preparing the substrate having the light-transmitting property, wherein the insulating layer having the light-transmissive property disposed to cover any one of the address auxiliary electrodes and the one electrode, (b) the insulation Disposing a photosensitive material on the surface where the layer is exposed; (c) using the one electrode as a mask and irradiating light from the other surface side of the substrate to expose the photosensitive material. It characterized by having a.

[Examples of the Invention]

Before describing an embodiment of the present invention, a description of the underlying technology will be described.

<Premise Technology>

An example of the driving method of the AC type PDP will be described as a prerequisite technique. In addition, a driving method relating to this premise technique is proposed in Japanese Patent Application No. Hei 9-173962.

The drive method of the AC type PDP according to the premise technique is a drive method for displaying a color image and divides the video display time of one screen into several fields. Here, as shown in FIG. 1, a case where 256 color images are obtained by dividing the video display time for one screen into eight subfields SF1 to SF8 will be described.

Each of the subfields SF1 to SF8 further includes an erasing operation period for erasing the history of light emission in the immediately preceding subfield, or an erasing period RA or RB, for selecting light emission / non-emission of light emitting cells in the subfield. It is divided into a sustain operation period or a sustain period S for executing a predetermined number of discharge / non-discharges according to the state selected in the write operation period or the address period AD and the immediately preceding address period AD. At this time, each sustain period S of the subfields SF1 to SF8 is ranked for each subfield SF1 to SF8. For example, the time of the sustain period S in the subfield SF2 is the sustain period in the subfield SF1. It is set to approximately twice the time of S. That is, the time of the sustain period S of the subfield SF (N + 1) is set to approximately twice that of the subfield SFN (N: 1 to 7).

In the light emitting cells or discharge cells selected in the address period AD of each subfield, sustain discharges generated in the same number of sustain pulses as the sustain pulses applied during the sustain period S are generated. Visible light emission generated by such sustain discharge becomes display light emission of this light emitting cell. As described above, since the number of the sustain pulses is set to be approximately proportional to the time of the sustain period S of each subfield SF1 to SF8, the light emission luminance of the light emitting cells selected by the write operation in the address period AD is sub As the number of fields progresses by one, it is approximately doubled. Therefore, by controlling the combination of lighting / non-lighting (on / off state of the light emitting cell) in the sustain period S in each subfield, the light emission luminance of 2 ⁸ = 256 level in one light emitting cell, Up to 256 gradations of display light emission can be obtained.

Next, a more specific driving method in one subfield will be described using the timing diagrams of FIGS. 2 and 3. Here, the case where the conventional AC type PDP 51P of FIG. 31 is used is demonstrated. In each of FIGS. 2 and 3, (a) is a timing diagram of the address electrode Am (1 ≦ m ≦ M) corresponding to the predetermined address electrode 6P of M in FIG. 31, and (b) is commonly connected. The timing diagrams of the N sustain electrodes X1 to XN (collectively also referred to as "hold electrodes X") to which a single voltage is applied, and each of (c) to (e) is a predetermined scan electrode Yn (1 of N). Is a timing diagram of? N? N). Each subfield shown in Figs. 2 and 3 has an erasing period RA or an erasing period RB, respectively.

In each address period AD of FIGS. 2 and 3, a sequential write operation is performed on the nth scan line SLn (see FIG. 31) composed of electrode pairs Xn and Yn by applying a sequential voltage (-Vy) to scan electrode Yn. Run At this time, in synchronization with the application of the voltage (-Vy), the voltage Von / voltage Voff corresponding to the on / off state of the image data is applied to the address electrode Am. In addition, a predetermined voltage Vx is applied to the sustain electrode X. Light discharge occurs in the discharge cell to which the voltage Von is applied to the address electrode Am, and the image data is recorded in the light emitting cell (as wall charge). On the other hand, the light discharge does not occur in the light emitting cell to which the voltage Voff is applied to the address electrode Am.

In the subsequent sustain period S, an alternating sustain pulse or sustain voltage Vs is applied between the sustain electrode Xn and the scan electrode Yn. At this time, sustain discharge occurs in the discharge cell which caused the write discharge in the address period AD described above in response to the timing when the sustain pulse Vs is applied.

4 and 5, the mechanism for generating light discharge in the address period AD will be described. When a voltage Vx and a voltage (-Vy) are applied to each of the electrodes Xn and Yn, an electric field is generated in the discharge space 51SP between the electrode pairs Xn and Yn. However, only such an electric field does not have the electric field strength necessary to generate surface discharge between the electrode pairs Xn and Yn. In this state, when the voltage Von according to the image data in the on state is applied to the address electrode Am, a strong electric field is generated between the address electrode Am and the scan electrode Yn, and as shown in Fig. 4, between the positive electrodes Am and Yn. The opposite of the (light) opposite discharge DC1 occurs. Then, the charged particles generated by the counter discharge DC1 are triggered, and as shown in Fig. 5, (light) surface discharge DC2 is generated between the electrode pairs Xn and Yn.

The negatively or positively charged particles generated by the surface discharge DC2 are attracted to the electrodes Xn and Yn respectively having polarities opposite to those of the particles, and the surface (4SP) of the cathode film 4P above each of the electrodes Xn and Yn. ) Is accumulated as wall charge. At this time, the electric field generated by the wall charges in the discharge space 51SP acts in a direction of eliminating the electric field formed in the discharge space 51SP by the voltage applied between the electrode pairs Xn and Yn. The amount of charged particles attracted to 4SP) is reduced. When the accumulated amount of wall charges reaches a certain amount, the write surface discharge DC2 between the electrode pairs Xn and Yn ends. At this time, even after the voltage supply to the electrodes Xn and Yn is stopped, wall charges accumulated on the surface 4SP of the cathode film 4P remain unresolved. In the sustain period S following the address period AD, the electric field required for the generation of sustain discharge (surface discharge) between the electrode pairs Xn and Yn is provided to the discharge space 51SP. By the action of the wall charges, the discharge cells to which the voltage Von is applied emit light in the sustain period S. FIG.

On the other hand, in the discharge cell in which the voltage Voff according to the image data signal in the off state is applied to the address electrode Am in the address period AD, an electric field sufficient for generating the light facing discharge DC1 is not formed between the address electrode Am and the scan electrode Yn. For this reason, the light opposing discharge DC1 between the address electrode Am and the scan electrode Yn does not occur, and therefore the light surface discharge DC2 does not occur between the electrode pairs Xn and Yn. As a result, the discharge cell to which the voltage Voff is applied shifts to the sustain period S as it is without the above-described wall charges, so that sustain discharge does not occur in this sustain period S. In other words, the discharge cells do not emit light.

By the way, in the sustain period S, as shown to (a) in each figure of FIG.2 and FIG.3, the positive voltage Va is supplied to all the address electrodes Am. As described above, in the address period AD, wall charges are formed on the surface 4SP of the cathode film 4P. At this time, the overglaze layer 10P and the phosphor layer 8P are also only slightly negatively charged. For this reason, the potential of the space in the vicinity of the portion in contact with the overglaze layer 10P of the phosphor layer 8P by the applied voltage Va is equal to the potential of the space above the central axis of the internal gap G (the voltage Vs / 2). ) And the potential of the wall charges of the positive electrode). Even when the voltage Vs is applied to any one of the electrodes Xn and Yn by the supply of the voltage Va to the address electrode Am, the electric field intensity distribution having spatial symmetry with respect to the central axis of the inner gap G is located near the inner gap G. As a result, according to the driving method of FIGS. 2 and 3, the voltage for starting the discharge applied between the electrode pairs Xn and Yn can be reduced to improve the efficiency of sustain discharge. Can be. The voltage Va is set so that the discharge intensity per one time of sustain discharge (surface discharge) between the electrodes Xn and Yn is the highest.

Hereinafter, embodiments of the present invention will be described.

<Example 1>

<Structure of AC Type PDP in Example 1>

FIG. 6 is a longitudinal sectional view schematically showing the structure of an AC surface discharge type plasma display panel (hereinafter, also referred to simply as "(AC type) PDP") according to the first embodiment. FIG. 6 corresponds exactly to the drawing when the conventional AC type PDP 51P of FIG. 31 is seen from the 1st direction D1.

As shown in FIG. 6, in the PDP according to the first embodiment, a first direction D1, which is a direction in which the first and second substrates 51Ra and 51F are described later, extends or elongates the common address electrode 16. Therefore, it is arrange | positioned via the (various) discharge space 51S partitioned by the barrier rib 7 mentioned later. The 1st board | substrate 51Ra and the 2nd board | substrate 51F are sealed in the peripheral edge part which is not shown in figure, and discharge gas, such as Ne-Xe mixed gas and He-Xe mixed gas, is enclosed in discharge space 51S, have.

First, the structure of the 2nd board | substrate 51F is demonstrated using FIG. In this PDP, since the front panel 51FP of the conventional PDP 51P can be used as the second substrate 51F, the second substrate 51F is also referred to with reference to FIG. 31 which is a perspective view of the conventional PDP 51P. Describe the structure of the.

As shown in FIG. 6, the strip | belt-shaped transparent equivalent to the transparent electrode 1P of FIG. 31 on the surface 5S of the discharge space 51S side of the front glass substrate 5 in 2nd board | substrate 51F is shown. The electrodes 1 (2N pieces) are formed in a stripe shape along the second direction D2 perpendicular to the third direction D3 perpendicular to the surface 5S. In addition, in FIG. 6, only one transparent electrode 1 (and the bus electrode 2 mentioned later) is shown with respect to the direction shown. At this time, a total of 2N transparent electrodes 1 as a whole of the PDP are paired with each other for two adjacent ones. And the bus electrode 2 equivalent to the bus electrode 2P of FIG. 31 is formed in the predetermined position on the surface 1S of the opposite side to the said surface 5S of the transparent electrode 1. As shown in FIG. Specifically, the bus electrode 2 has a band-like shape along the edge on the surface 1S of the transparent electrode 1 near the edge opposite to the transparent electrode 1 paired with the transparent electrode 1. It is formed. In the following description, electrodes composed of the transparent electrode 1 and the bus electrode 2 and paired with each other are referred to as "(holding) electrode Xn (1≤n≤N)" and "(scanning) electrode Yn (1≤n). ≤ N) ''. At this time, as in the conventional PDP 51P of Fig. 31, the n-th (or n-th) scan line or display line SLn in this PDP is formed by the electrode pairs Xn and Yn.

Then, the dielectric or dielectric layer 3 equivalent to the conventional dielectric (layer) 3P of FIG. 31 is covered so as to cover the surface 5S, the transparent electrode 1 and the bus electrode 2 of the front glass substrate 5. It is arranged. Cathode film 4 (corresponding to cathode film 4P in Fig. 31) made of a high secondary electron emission material such as magnesium oxide (MgO) on the surface 3S on the discharge space 51S side of the dielectric layer 3. Is formed. The dielectric layer 3 and the cathode film 4 may be generically referred to as "dielectric layer 3A" in view of their materials. At this time, the "surface 3SA of the dielectric layer 3A" corresponds to the surface 4S of the discharge space 51S side of the cathode film 4.

On the other hand, the first substrate 51Ra, which is a feature of the PDP according to the first embodiment, has the following configuration. In addition, the following description is also demonstrated using FIG. 7 which is a schematic plan view for demonstrating the arrangement | positioning form of each electrode in the case where the 1st board | substrate 51Ra is seen from the discharge space 51S side in addition to FIG. . In addition, in FIG. 7, the common address electrode 16 (to its center axis | shaft) mentioned later is shown typically by a thick solid line. In addition, in the following description, for convenience of explanation, it is called "upper" and "lower" along the 1st direction D1 (it is perpendicular | vertical to both the said 2nd and 3rd directions D2 and D3) of the 1st board | substrate 51Ra. This is to correspond to the top or the bottom of the display screen when the PDP is used. Even in this case, it is clear that generality is not lost.

6 and 7, the first substrate 51Ra includes a back glass substrate 9, a first address auxiliary electrode 17T, and a second address auxiliary electrode 17B (collectively, an address auxiliary electrode ( 17) ", the common address electrode 16, the insulating layer 15, and the overglaze layer 10 are provided. In detail, a plurality of band-shaped first address auxiliary electrodes 17T and second address auxiliary electrodes (not shown) extending in parallel to each other along the first direction D1 in the display area AR1 in which discharge cells described later are arranged in a matrix form. 17B) is alternately arrange | positioned on the surface 9S of the discharge space side of the back glass substrate 9 in the 2nd direction D2 which is its arrangement direction. Here, the display area AR1 is not only a planar area in the surface 9S of the rear glass substrate 9 but also a three-dimensional area in which the planar area is extended in the third direction D3 perpendicular to the surface 9S. We shall include. The same holds true for the upper lead-out area AR21, the lower lead-out area AR22, the terminal part area AR3 and the area AR4 described later.

The M / 2 first address auxiliary electrodes 17T are formed extending from the upper lead-out area AR21 side provided on the upper side in the first direction D1 subsequent to the display area AR1, and within the region AR21, the second direction D2 In addition, it is connected to the (first) common electrode part (wiring part) 17T2 for the said 1st address auxiliary electrode which extends also in the vicinity of the both ends in the said direction D2 of the back glass substrate 9 along. Such a common electrode part 17T2 is in the said direction D2 of the part which extends along the 2nd direction D2 to the area | region AR4 of the edge part of the left-right side edge in the 2nd direction D2 of the back glass substrate 9 along the said 2nd direction D2. Each of both ends further has a portion extending along the first direction D1. The portion extending along the first direction D1 reaches the terminal portion region AR3 provided at the end opposite to the upper lead-out region AR21, and the end portion in the region AR3 of the portion extending along the first direction D1. Thus, the terminal for the first common electrode portion 17T2, that is, the terminal 17T3 for the first address auxiliary electrode 17T is formed.

On the other hand, the M / 2 second address auxiliary electrodes 17B continue to the display area AR1 and extend toward the lower lead-out area AR22 provided on the lower side in the first direction D1. It is connected to the (second) common electrode portion (wiring portion) 17B2 for the second address auxiliary electrode 17B extending along the direction D2 and not in contact with the first common electrode portion 17T2. Such a common electrode portion 17B2 is formed extending from the predetermined position in the first direction D1 and further has a portion reaching the terminal portion region AR3 provided in the first direction D1 following the lower lead-out region AR22. And the terminal part for the common electrode part 17B2, ie, the terminal 17B3 for the 2nd address auxiliary electrode 17B, is formed by the edge part of the part extended along this 1st direction D1.

A uniform interlayer insulating layer 15 made of a dielectric material is disposed in a predetermined range of the surface 9S so as to cover the address auxiliary electrode 17. As shown in FIG. 7, the interlayer insulating layer 15 is disposed to cover the display area AR1, the upper lead-out area AR21, the lower lead-out area AR22 and the area AR4 on the surface 9S of the back glass substrate 9. have.

In addition, on the surface 15S on the side opposite to the surface 9S of the interlayer insulating layer 15, two M-shaped two-lane common address electrodes (hereinafter also referred to simply as "common address electrodes") 16 are formed. It is arranged in a stripe shape along the first direction D1. In detail, in the display area AR1, the center axis in the first direction D1 of the common address electrode 16 and the center axis in the direction D1 of the address auxiliary electrode 17 coincide with each other. At this time, the width that is the length along the second direction D2 of the common address electrode 16 is set to a size smaller than the width that is the length along the direction D2 of the address auxiliary electrode 17.

As shown in FIG. 7, the M common address electrodes 16 are commonly connected to each other adjacent to each other in the lower lead-out area AR22. That is, the first common address electrode 16T that opposes the first address auxiliary electrode 17T and the second common address electrode 16B that oppose the second address auxiliary electrode 17B are connected to each other. For this reason, each of two (or one pair) common address electrodes connected in common is also called "common address electrode PAk (k: 1 to M / 2)." A terminal for the two common address electrodes 16, i.e., a terminal for common address electrode common to the terminal portion region AR3, formed by extending from the commonly connected portion to the terminal portion region AR3. 163 is formed. In addition, the terminals 163 for the common address electrode 16 are blocked and arranged in correspondence with the wiring pitch of the FPC (Flexible Printed Circuit) connected to the terminal 163, for example, between the adjacent blocks BL. The arrangement area of the above-described terminals 17T3 and 17B3 of the address auxiliary electrodes 17T and 17B can be provided in the blank area generated in the above. Therefore, as illustrated in FIG. 7, the terminals 163, 17T3, and 17B3 of the common address electrode 16 and the address auxiliary electrode 17 are concentrated on one end or the bottom of the back glass substrate 9. The advantage is that you can.

Further, the first and second common address electrodes 16T, 16B commonly connected in the above-mentioned lower lead-out area AR22 reach the output bits or output terminals of the address IC driver IC outside the display area AR1. It should just be electrically integrated in the wiring path | route until it does.

The overglaze layer or glaze layer 10 made of a dielectric material is disposed to cover the common address electrode 16. The overglaze layer 10 is formed at least in the display area AR1. At this time, the layer 10 may be formed in the same range as the formation range of the interlayer insulating layer 15.

As shown in Fig. 6, the surface of the first substrate 51Ra on the discharge space 51S side of the overglaze layer 10 or on the surface 10S on the side opposite to the surface 15S is shown in Fig. 31. (M + 1) barrier ribs or partitions 7 which are equivalent to the barrier ribs 7P are arranged. In detail, a strip-shaped barrier rib 7 having a predetermined height along the third direction D3 and extending along the first direction D1 is disposed in parallel with each other on the surface 10S. At this time, the center axis in the said direction D1 of the area | region between the 1st address auxiliary electrode 17T and the 2nd address auxiliary electrode 17B which adjoin the center axis of the barrier rib 7 in the 1st direction D1. The barrier rib 7 is arrange | positioned so that it may correspond in this 3rd direction D3.

Here, each of the (M + 1) barrier ribs 7 is referred to as &quot; barrier rib Bi (i: 1 to M + 1) &quot;, while the barrier ribs Bm and the barrier ribs Bm + 1 are faced to both side walls and the above. The lane 35 constituted by the surface 10S is also referred to as "lane Lm". Moreover, it divides by the plane containing the central axis in the 1st direction D1 of any one barrier rib, and perpendicular | vertical to a 2nd direction D2, and the said plane with respect to the other barrier rib adjacent to the said arbitrary one barrier rib. The three-dimensional area to be referred to as a "lane area". At this time, the lane area partitioned by barrier rib Bm and barrier rib Bm + 1 is called like "lane area ARLm." In this case, the (several) first address auxiliary electrodes 17T in FIG. 6 belong to the lane areas ARLm-1, ARLm + 1, ARLm + 3, and ARLm + 5, and likewise (seconds) the second The address auxiliary electrode 17B belongs to the lane areas ARLm-2, ARLm, ARLm + 2, and ARLm + 4. At this time, the address auxiliary electrodes 17 are arranged at the same pitch as the width or pitch in the arrangement direction of the lane area. In view of the above-described dimensional relationship of the mutual widths, the address auxiliary electrode 17 is covered with the common address electrode 16 when the first substrate 51Ra is viewed from the discharge space 51S side. Part 17TA, 17BA which is not (hidden), and part 17TB, 17BB which are not covered and covered by the said electrode 16 are contained in each lane area | region.

Then, the phosphor or the phosphor layer 8 is formed on the inner surface 35S of the U-shaped groove or the lane 35 formed by the opposite wall surfaces of the adjacent barrier ribs 7 and the surface of the overglaze layer 10. This is arranged. At this time, similar to the phosphors 8PR, 8PG, and 8PB in Fig. 31, the phosphors for red light emission, green light emission, and blue light emission are arranged in units of lanes 35.

The 1st board | substrate 51Ra and the 2nd board | substrate 51F which have such a structure are arrange | positioned via the discharge space 51S in which discharge gas was filled. At this time, a discharge cell or a light emitting cell is formed by each component near a portion where the common address electrode 16 (and the address auxiliary electrode 17) and the scan line intersect three-dimensionally. At this time, the discharge cells to which the first common address electrode 16T and the first address auxiliary electrode 17T belong are also referred to as "(first) discharge cell CT" and at the same time, the second common address electrode 16B and the second The discharge cell to which the address auxiliary electrode 17B belongs is also called "(second) discharge cell CB".

<Drive Method of AC Type PDP in Example 1>

Next, the driving method by the subfield gradation method of the above AC type PDP will be described with reference to FIG. FIG. 8 is a timing chart showing waveforms of voltages applied to the electrodes in the write operation period or the address period (see FIGS. 1 to 3) AD0 in this driving method. 8A to 8C show voltages VT, VB, and VAk (k: 1) applied to the first address auxiliary electrode 17T, the second address auxiliary electrode 17B, and the common address electrode PAk, respectively. The timing diagram of ˜M / 2) is shown. (D) in FIG. 8 shows the voltage Vx0 commonly applied to all the sustain electrodes X1 to XN (collectively referred to as "holding electrode X"), and (e) to (g) in FIG. Each voltage VY1, VY2, VYN applied to the electrodes Y1, Y2, YN is shown.

As shown in Fig. 8, the address period AD0 in this driving method is largely divided into a first period AD1 and a second period AD2. In the following description, for example, when voltages V1, V2, V3, and V4 have a relationship of (voltage V1)> (voltage V2) and (voltage V3)> (voltage V4), "voltage V1 and voltage" are described. V3 (or voltage V2 and voltage V4 are on the same side (polarity)) and "voltage V1 and voltage V4 (or voltage V2 and voltage V3 are on opposite sides (polarity)" will be described.

First, as shown in (a) and (b) of FIG. 8 in the first period AD1 forming the first half of the address period AD0, the image of the first address auxiliary electrode 17T turned on as the voltage VT. The voltage (third voltage) Vh having the same polarity as the voltage (first voltage) Von according to the data is applied, and the voltage according to the off-state image data as the voltage VB to the second address auxiliary electrode 17B. (2nd voltage) Voff (<Von) and the voltage (4th voltage) Vl (it shall be <Vh) in the polarity on the same side are applied. In this state, as shown in (e) to (g) in FIG. 8, voltage pulses of the sequential voltage value (-Vy) are applied as the voltages VY1 to VYN of the scan electrodes Y1 to YN. At this time, as shown in (c) of FIG. 8, the discharge cells belonging to the first address auxiliary electrode 17T are selected from among the discharge cells belonging to the selected scan lines in synchronization with the timing of the selective scan of the scan electrodes Y1 to YN. Write discharge or address discharge in accordance with the image data is generated. That is, the voltage Von or the voltage Voff is commonly applied as the voltages VA1 to VAM / 2 according to the image data of the discharge cells to which the first address auxiliary electrode 17T belongs to each common address electrode PA1 to PAM / 2. .

On the other hand, in the second period AD2 that forms the second half of the address period AD0, as shown in (a) and (b) of FIG. 8, the voltage Vl on the same side as Voff is the voltage VT as opposed to the first period AD1 described above. At the same time, the voltage Vh on the same side as Von is applied as the voltage VB. In such a state, as shown in (e) to (g) in FIG. 8 as in the first period AD1 described above, the sequential voltage values (-Vy) are defined as the voltages VY1 to VYN of the scan electrodes Y1 to YN. Apply voltage pulse. At this time, in the second period AD2, the voltage Von or the voltage corresponding to the image data of the discharge cell to which the second address auxiliary electrode 17B belongs as the voltages VA1 to VAM / 2 in synchronization with the timing of the selective scan of the scan electrodes Y1 to YN. Apply Voff. As a result, the light discharge according to the image data is generated in the discharge cells to which the second address auxiliary electrode 17B belongs among the plurality of discharge cells belonging to the selected scanning line.

On the other hand, as described above, the address auxiliary electrode 17 in FIG. 6 is a part 17TB not covered by the common address electrode 16 when the first substrate 51Ra is viewed from the discharge space 51S side. , (17BB). Therefore, the voltage of the common address electrode 16 (or (PAk)) is formed to form an electric field in the vicinity of the discharge space 51S in contact with the cathode film 4 above the scan electrode Yn selectively scanned in the address period AD0 described above. In addition to the electric field by VAk, the electric fields by the voltages VT and VB of the first address auxiliary electrode 17T and the second address auxiliary electrode 17B have a great influence. Therefore, in the driving method according to the first embodiment, the voltage VAk and the address of the common address electrode 16 (or (PAk)) are appropriately adjusted or controlled by the voltage (value) Vh, Vl, Von, Voff, and Vy. The voltage condition that both the voltage VT or the voltage VB of the auxiliary electrode 17 are at the same polarity as the voltage Von is written in the discharge cell belonging to the first address auxiliary electrode 17T or the second address auxiliary electrode 17B. It is set as a necessary and sufficient condition for generating a discharge.

According to such a voltage setting condition, in the discharge cell CT in which the voltage Vh is applied as the voltage VT when the voltage Von is applied to the common address electrode PAk (or 16) in the first period AD1. Light discharge occurs. In contrast, the light discharge does not occur in the discharge cell CB to which the voltage V1 is applied as the voltage VB. On the contrary, when the voltage Von is applied to the common address electrode 16 in the second period AD2, the light discharge occurs in the discharge cell CB to which the voltage Vh is applied as the voltage VB, whereas the voltage V1 is applied as the voltage VT. Light discharge does not occur in the discharge cell CT. That is, in the first period AD1, the write operation is performed only for the first discharge cell CT to which the first address auxiliary electrode 17T is accelerated, while in the second period AD2, the second to which the second address auxiliary electrode 17B belongs. The write operation for only the discharge cell CB is performed. As a result, the write operation for the entire lane 35 or all the discharge cells CT and CB is performed through the address period AD0. In addition, during the transition from the first period AD1 to the second period AD2, the period in which the voltages VT and VB shown in Figs. 8A and 8B are all set to the voltage Vl is not an essential configuration requirement.

As described above, according to the AC surface discharge type plasma display panel and the driving method thereof according to the first embodiment, the number of the terminal electrodes 163 for the address electrodes is changed to that of the conventional AC type PDP by applying the common address electrode 16. You can do it with half. For this reason, high density mounting in terminal part area | region AR3 can be effectively avoided. Of course, since the number of the address electrode terminals 163 is halved, the number of the drive ICs for the address electrodes is also halved, so that significant cost reduction can be realized.

Further, several common address electrodes are grouped as common address electrodes (corresponding to the common address electrodes 16) common to the S lanes 35, and at the same time, each of the plurality of address auxiliary electrodes is first to s addresses. The above-described driving method can also be applied to an AC surface discharge type plasma display panel divided into groups consisting of auxiliary electrodes T 1 to Ts (corresponding to first or second address auxiliary electrodes 17T and 17B). At this time, the first to s-address auxiliary electrodes are arranged in the order of, for example, the address auxiliary electrodes T1, T2, ..., Ts, T1, T2, ..., Ts, ... The arrangement order of the auxiliary electrodes is not limited to this example). When the number of common address electrodes belonging to each group (or the number of common address electrodes supplied with voltage in common) and the number of address auxiliary electrodes belonging to each group (corresponding to s) are the same, the above-described driving is performed. The advantage is that you can make relatively simple changes to the method.

At this time, the address period is divided into s periods, and the image corresponding to lanes 35 or discharge cells to which the address auxiliary electrode Tj belongs to the common address electrode in the jth (1 ≦ j ≦ s) period. When voltage Von or Voff according to data is applied in synchronization with the selective scan of scan electrode Yn, voltage Vh is applied to address auxiliary electrode Tj and voltage Vl is applied to another address auxiliary electrode Ti (i ≠ j). In such a case, each number of the address electrode terminal and the address electrode driver IC can be set to 1 / s, so that high-density packaging can be avoided and the cost can be further reduced.

Here, an AC type PDP having one address electrode shared by an adjacent discharge cell and an electrode of a different electrical type provided in each of the adjacent discharge cells and a driving method thereof are disclosed in, for example, Japanese Patent Application Laid-Open. It is disclosed in Unexamined Patent Publication No. 9-325732. According to the driving method according to the prior art, by controlling the voltages applied to the different types of electrodes which are electrically different from each other, it is selected which of the adjacent discharge cells is to be generated. Further, the PDP according to the prior art has a structure of so-called counter discharge type structure in which sustain discharge is performed at an intersection portion of a row electrode and a column electrode which face each other with a discharge space therebetween. In contrast, the PDP according to the first embodiment is a so-called (AC) surface discharge type plasma display panel, and the basic structure of the PDP to which each driving method is applied differs greatly.

However, in the PDP according to the prior art, for example, M / 2 common address electrodes are disposed in every other area between M adjacent column electrodes. And all the column electrodes belonging to the even-numbered partition of the column electrode divided into two by the said common address electrode are commonly connected to the 1st type of sustain electrode, and all the column electrodes belonging to the odd-numbered partition are It is commonly connected to the second type of sustain electrode. In other words, a first type or a second type of sustain electrode, which is a different type of sustain electrode, is disposed on both sides of each common address electrode. At this time, by controlling the polarities of the two types of sustain electrodes, the wall charges are erased in the discharge cells belonging to the column on one side of the common address electrode in accordance with the image data in the on state or the off state input to the common address electrode. To generate a discharge (erase address operation). By such a driving method, the columns on both sides of the electrodes are independently switched by one common address electrode.

However, the polarity control of the voltages applied to the first and second sustain electrodes needs to be switched by a frequency above the frequency of the voltage according to the image data input to the common address electrode. At this time, a circuit capable of recovering the reactive power generated by the switching operation with high efficiency must be provided. Again, such a circuit is very complicated.

In contrast, in the AC type PDP according to the first embodiment, the common address electrode and the sustain electrode are not in parallel positional relationship. As described above, the AC type PDP includes a common address electrode shared in adjacent lane regions (or discharge cells) and an address auxiliary electrode disposed in parallel with the electrode. One of the two discharge cells sharing the common address electrode is selected by a simple control of the voltage applied to the address auxiliary electrode. At this time, the switching operation relating to the voltage control described above is basically one time in one address period. The switching of the scan electrode and sustain electrode in the address period is the same as that of the conventional drive method except that the linear sequential scanning of the scan electrode in two cycles is performed in the address period of the conventional drive method. In other words, it can be said that the driving method according to the first embodiment has an advantage in that there is no need to perform high frequency switching as in the driving method according to the prior art.

<Modification 1 of Example 1>

In the first modified example, another example of the pattern shape of the common address electrode 16 and the address auxiliary electrode 17 will be described. FIG. 9 is a plan view corresponding to FIG. 7 described above. In FIG. 9, the common address electrode 16 (or its central axis) is schematically illustrated by a thick solid line as shown in FIG. 7.

As shown in FIG. 9, the first substrate 51Ra2 according to the first modified example is a method in which (multiple) scanning lines (not shown in FIG. 9) are driven by two blocks on the upper and lower sides of the display area. Up and down block parallel addressing system ”. In detail, the display area AR1 is divided into an upper display area AR11 and a lower display area AR12 in the center portion of the first direction D1, and the first and second common address electrodes 16T, 16B, that is, the common address electrode 16 is disposed. As for the common address electrode 16 in the display area AR1 of the first substrate 51Ra2 of FIG. 9, the common address electrode 16 of FIG. 7 is electrically divided at the center in the first direction D1 of the display area AR1. It is equivalent to the structure.

In this case, the first and second common address electrodes 16T and 16B belonging to the upper display area AR11 are connected in common in the lead-out area AR21, and the upper terminal part area provided above the lead-out area AR21. It extends to AR31 and is formed. And the terminal part 163 for the common address electrode 16 which belongs to upper display area AR11 is formed by the edge part in upper terminal part area | region AR31. In contrast, the common address electrode 16 belonging to the lower display area AR12 is commonly connected in the lower lead-out area AR22 and extends to the lower terminal part area AR32 corresponding to the terminal part area AR3 (see FIG. 7) described above. The terminal 163 for the common address electrode 16 belonging to the lower display area AR12 is formed by the end in the lower terminal part area AR32 of the common address electrode 16.

At this time, as shown in Fig. 9, when arranging the terminal 17T3 for the first address auxiliary electrode 17T in the above-described blank area caused by the blocking of the terminal 163 in the upper terminal part area AR31, the terminal part area is shown. It is possible to further reduce the mounting density in AR31 and AR32.

In addition, the common electrode portion 17T2 and the terminal 17T3 of the first address auxiliary electrode 17T are symmetrical in the structure of the first address auxiliary electrode 17T and the second address auxiliary electrode 17B shown in FIG. 7. ) Is disposed in the lower lead-out area AR22 and the lower terminal part area AR32, and the common electrode part 17B 2 and the terminal 17B3 of the second address auxiliary electrode 17B are placed in the upper lead-out area AR21 and the upper terminal part area AR31. It is clear that you may arrange inside.

<Example 2>

6, the first and second address auxiliary electrodes 17T and 17B of the first substrate 51Ra described above move the first substrate 51Ra to the discharge space 51S side. When seen from the surface 9S side of the back glass substrate 9, it has the parts 17TA and 17BA which overlap (overlap) with the 1st and 2nd common address electrodes 16T and 16B. Therefore, the capacitance component of the capacitor structure composed of the interlayer insulating layer 15 sandwiched between the common address electrode 16, the address auxiliary electrode 17, and both electrodes is used to reduce the driving speed of the PDP. There may be one.

For example, in the case where write discharge is performed on the discharge cells CT belonging to the lane area ARLm-1 in the first period AD1 (see FIG. 8), the second addresses belonging to the lane areas ARLm-2 and ARLm on both sides are also provided. The electric field due to the potential V1 applied to the auxiliary electrode 17B sometimes hinders the formation of an electric field (including its strength) necessary for generating light discharge in the discharge cell CT. For this reason, a case may not occur in which a sure recording operation can be performed.

Therefore, the second embodiment describes an AC type PDP capable of a higher speed operation than the AC type PDP according to the first embodiment and capable of performing a reliable recording operation. In addition, each AC type PDP according to the second embodiment and Examples 3 to 10 to be described later is characterized by the structure of the first substrate corresponding to the first substrate 51Ra described above. . For this reason, the same code | symbol is attached | subjected to the equivalent component, and the detailed description is used. At this time, since the second substrate 51F of FIG. 6 can be applied to the second substrate in each AC type PDP, the description thereof is merely used. Such a point is the same also in description of Examples 3-10 mentioned later.

10 is a longitudinal sectional view schematically showing a structure in a display area of the first substrate 51Rb according to the second embodiment. In addition, in FIG. 10 and FIGS. 11-13 and 22-23 which are mentioned later, although the illustration of the fluorescent substance 8 shown in FIG. 6 is abbreviate | omitted in order to avoid the complicated drawing, either of the first substrates Also in FIG. 6, the fluorescent substance 8 (made of fluorescent substance for red, green, and blue light emission) is arrange | positioned as mentioned above.

As shown in Fig. 10, several barrier ribs 7 are disposed on the first substrate 51Rb according to the second embodiment. In each lane area defined by the adjacent barrier ribs 7, the first common address electrode 26T and the first address auxiliary electrode 27T, or similarly, the third, which do not overlap with each other in the third direction D3 direction. In the direction D3, the second common address electrode 26B and the second address auxiliary electrode 27B, which do not overlap each other, are disposed. In the following description, the first and second common address electrodes 26T and 26B are collectively referred to as the "common address electrode 26" while the first and second address auxiliary electrodes 27T and 27B are referred to. ) Is also collectively referred to as "address auxiliary electrode 27".

In detail, for example, in the lane region ARLm-1 shown in FIG. 10, the first address auxiliary electrode 27T extends the lane Lm-1 and the barrier rib Bm-1 on the surface 9S of the rear glass substrate 9. In the case of projecting on, it is arrange | positioned in the position over the projection part of both elements Lm-1 and Bm-1. Then, the first common address electrode 26T is disposed on the surface 15S of the interlayer insulating layer 15 covering the first address auxiliary electrode 27T. At this time, the first common address electrode 26T is disposed at a position across both projection portions of both elements Lm-1 and Bm when the lane Lm-1 and the barrier rib Bm are projected on the surface 15S. have. As a whole of the first substrate 51Rb, the address auxiliary electrode 27T is disposed at a pitch twice the width or the pitch in the array direction of the lane area.

In contrast, in the lane area ARLm adjacent to the lane area ARLm-1, when the second address auxiliary electrode 27B projects the lane Lm and the barrier rib Bm + 1 on the surface 9S, both elements Lm, It is arrange | positioned in the position over both projection parts of Bm + 1. In addition, the second common address electrode 26B, which forms the common address electrode PAk together with the first common address electrode 26T, forms the lane Lm and the barrier rib Bm on the surface 15S of the interlayer insulating layer 15. When it projects on the said surface 15S, it arrange | positions in the position over both projection parts of both elements Lm and Bm. The overglaze layer 10 is disposed to cover the common address electrode 26.

Thus, each component in adjacent lane area | region Lm-1, Lm is arrange | positioned in the symmetrical position with respect to the boundary (surface) between both lane area | regions. And as a whole 1st board | substrate 51Rb, the structure which sets the adjacent lane area | region Lm-1 and Lm as one set is arrange | positioned along the 2nd direction D2.

In addition, the structure or wiring pattern in the lead-out area | region and terminal part area | region of the 1st board | substrate 51Rb can apply the same thing as that of Example 1 mentioned above or the modified example 1 of this. As the driving method in the address period, the driving method (see Fig. 8) according to the first embodiment is applied.

As described above, the common address electrode 26 and the address auxiliary electrode 27 in the first substrate 51Rb according to the second embodiment have both electrodes 26 and 27 on the back surface of the glass substrate 9. In the case seen from the (9S) side (that is, in the third direction D3), there is no portion overlapping each other. For this reason, the capacitance between the common address electrode 26 and the address auxiliary electrode 27 is smaller than that in the first substrate 51Ra. Therefore, according to the AC type PDP to which the first substrate 51Rb is applied, it is possible to realize a faster writing operation than the AC type PDP according to the first embodiment.

Further, in the first substrate 51Rb, for example, in the lane areas ARLm-1 and ARLm to which the common address electrode PAk belongs, the first substrate 51Rb has a higher number than the second address auxiliary electrode 27B with respect to the first common address electrode 26T. The two common address electrodes 26B are arranged near each other. For this reason, when the AC type PDP to which the first substrate 51Rb is applied is driven, for example, light discharge is applied to the discharge cell CT (see Fig. 6) belonging to the lane area ARLm-1 in the first period AD1 (see Fig. 8). In the case of generating, the influence on the electric field formation in the lane area ARLm-1 is the electric field side by the voltage Von applied to the second common address electrode 26B rather than the electric field by the voltage Vl applied to the second address auxiliary electrode 27B. This is big. Therefore, compared to the AC PDP according to the first embodiment, normal light discharge is more likely to occur in the discharge cell CT belonging to the lane Lm-1. In other words, a reliable recording operation can be performed. As a result, since the voltages Von and Vh can be reduced, the advantage that the load of the address IC driver IC can be reduced in the plasma display device including the AC PDP is obtained.

<Example 3>

As described above, in the AC type PDP including the first substrate 51Rb according to the second embodiment, for example, the discharge cells CT belonging to the lane area ARLm-1 in the first period AD1 (see FIG. 8) (FIG. 6). When the light discharge is performed, the electric field due to the voltage Von applied to the second common address electrode 26B disposed at the position closest to the discharge cell CT in the adjacent lane region ARLm is the lane Lm−. There is an action of assisting the electric field formation within 1.

However, on the side opposite to the lane area ARLm, the second address auxiliary electrode 27B belonging to the lane area ARLm-2 adjacent to the lane area ARLm-1 is disposed adjacent to the lane area ARLm-1. Therefore, in the above-described driving, when the electric field due to the voltage V1 applied to the second address auxiliary electrode 27B belonging to the lane area ARLm-2 inhibits the light discharge in the discharge cell belonging to the lane area ARLm-1. There is.

Thus, in Example 3, a first substrate capable of providing an AC type PDP in which such a point is improved will be described.

11 is a longitudinal sectional view schematically showing a structure in a display region of a first substrate 51Rc according to the third embodiment. As shown in FIG. 11, in this 1st board | substrate 51Rc, the 1st address auxiliary electrode 37T corresponding to the 1st address auxiliary electrode 27T shown in FIG. 10, the agent shown in FIG. The second address auxiliary electrode 37B corresponding to the two address auxiliary electrodes 27B (both electrodes 37T and 37B are collectively referred to as the "address auxiliary electrode 37") is characterized by an arrangement position. In detail, in the 1st board | substrate 51Rb shown in FIG. 10, although the 1st address auxiliary electrode 27T and the 2nd address auxiliary electrode 27B are alternately arrange | positioned in 2nd direction D2, this 1st In the substrate 51Rc, as shown in Fig. 11, the first address auxiliary electrode 37T and the second address auxiliary electrode 37B are alternately arranged in two units. That is, the first address auxiliary electrode 37T, the first address auxiliary electrode 37T, the second address auxiliary electrode 37B, the second address auxiliary electrode 37B, and the address auxiliary electrode of FIG. It is arrange | positioned in the position corresponded to the arrangement position of (27). The interlayer insulating layer 15 is disposed to cover the first and second address auxiliary electrodes 37T and 37B. The first and second common address electrodes (at the positions corresponding to the respective arrangement positions of the first and second common address electrodes 26T and 26B of FIG. 10 on the surface 15S of the interlayer insulating layer 15) ( 36T) and 36B (generally referred to as "common address electrode 36") are arranged. At this time, as shown in FIG. 11, the first common address electrode 36T belonging to the lane area ARLm-1 and the second common address electrode 36B belonging to the lane area ARLm adjacent to the area ARLm-1 are common addresses. The electrode PAk is formed.

The above-described driving method (see FIG. 8) can be applied to the AC type PDP in which the first substrate 51Rc in FIG. 11 and the second substrate 51F in FIG. 6 are combined. That is, in the address period AD0, each of the first address auxiliary electrode 37T, the second address auxiliary electrode 37B, the sustain electrodes X1 to XN, and the scan electrodes Y1 to YN is shown in FIGS. voltages having the voltage waveforms (d) and (e) to (g) are applied. The following voltage is applied to the common address electrode 37. That is, in the first period AD1, the voltage Von or Voff corresponding to the image data corresponding to the lane 35 or the discharge cell CT to which the first address auxiliary electrode 37T belongs is applied, while in the second period AD2, the second address auxiliary is applied. The voltage Von or Voff corresponding to the image data corresponding to the lane 35 to which the electrode 37B belongs or the discharge cell CB is applied. As a result, a write operation for all lanes or all discharge cells is performed.

Thus, unlike the first substrate 51Rb in FIG. 10, in the first substrate 51Rc according to the third embodiment, the first address auxiliary electrode 37T is disposed in the lane region ARLm-2 adjacent to the lane region ARLm-1. Have Therefore, for example, in the case where write discharge is performed to the discharge cell CT belonging to the lane area ARLm-1 in the first period AD1, it belongs to the lane areas ARLm-2 and ARLm on both sides of the corresponding lane area ARLm-1. The first address auxiliary electrode 37T belonging to the lane area ARLm-2 disposed near the lane area ARLm-1 and the second common address electrode 36B belonging to the lane area ARLm are both on the same side as the voltage Von. A voltage in polarity is being applied. That is, voltages of the polarity on the same side as the voltage Von are all applied to the electrodes present in the vicinity of the discharge cells to generate the light discharge. For this reason, according to the AC type PDP which has this 1st board | substrate 51Rc, it is possible to generate | occur | produce light discharge more easily and reliably compared with the AC type PDP which concerns on Example 2. Of course, in the second period AD2 (see FIG. 8), the light discharges to the discharge cells belonging to the lane 35 (for example, lane Lm) having the second common address electrode 36B and the second address auxiliary electrode 37B. The same effect can be obtained also in the case of executing. At this time, the voltages Von and Vh can be further reduced.

In addition, when the voltage Voff is applied to the common address electrode 36 (for example, the common address electrode PAk) in the first period AD1, the lane 35 to which the second address auxiliary electrode 37B belongs (for example, For example, a voltage at the same polarity as the voltage Voff is applied to all the electrodes near the lane Lm). For this reason, in the discharge cell to which the second address auxiliary electrode 37B belongs, there is a situation in which orly discharge is very unlikely to occur. This is because the lane 35 having the first address auxiliary electrode 37T when the voltage Voff is applied to the common address electrode 36 (for example, the common address electrode PAk) in the second period AD2. The same applies to the discharge cells belonging to () (for example, lane Lm-1). Therefore, by increasing the voltages Voff and Vl, the potential difference, the switching widths Von-Voff, and Vh-Vl can be reduced, thereby reducing the load of the address IC driver IC. At this time, the voltages VT and VB (voltage Vh or Vl) applied to the first or second address auxiliary electrodes 37T and 37B belonging to each lane 35 and the voltage VPAk applied to the common address electrode 36. It is necessary to set the voltages Voff and Vl so that no ore discharge occurs when the polarity of the voltage Von or Voff becomes the opposite side. However, since the voltages Von and Vh can be reduced as described above, the above conditions for increasing the voltages Voff and Vl are very loose.

As described above, the AC type PDP including the first substrate 51Rc and the substrate 51Rc according to the third embodiment is compared with the AC type PDP including the first substrates 51Ra and 51Rb described above. It is possible to further accelerate the write operation and reduce the switching width (Von-Voff). At this time, in the above-described driving method shown in Fig. 8 in which the number of the drive ICs for the address electrodes can be halved by the application of the common address electrode, the output bits or one output terminal of the drive ICs for the address electrodes in the address period AD0. Given that the number of output pulses is twice that of the conventional plasma display device and its driving method, the first substrate 51Rc according to the third embodiment is applied to the first substrates 51Ra and 51Rb described above. It can be said that a more practical AC type PDP can be provided for the driving method. That is, by speeding up the recording operation, it is possible to sufficiently secure the time allotted to the sustain period, and as a result, a sufficient number of gradations. It goes without saying that reducing the switching width (Von-Voff) is preferable from the viewpoint of reducing the load of the drive IC for the address electrode.

<Example 4>

12 is a longitudinal sectional view schematically showing a structure in a display region of a first substrate 51Rd according to the fourth embodiment. As shown in Fig. 12, in the first substrate 51Rd, the first address auxiliary electrode 47T and the second address auxiliary electrode 47B (collectively, "address") are formed on the surface 9S of the back glass substrate 9; Auxiliary electrodes 47 "are alternately arranged in the second direction D2 in the array direction.

The first address auxiliary electrode 47T has a structure in which two first address auxiliary electrodes 37T adjacent to each other in the first substrate 51Rc in FIG. 11 are formed as one electrode. In detail, the first address auxiliary electrode 47T slightly has a barrier rib at the central axis in the first direction D1, for example, in a portion in which the lane Lm-2 is projected along the third direction D3 on the surface 9S. Has a width (length along the second direction D2) from a position biased to Bm-1 to a position symmetrical with respect to the boundary (surface) between the position and the lane areas ARLm-2 and ARLm-1, and in the first direction D1 It is a band-shaped electrode extending.

Similarly, the second address auxiliary electrode 47B disposed on the surface 9S of the first substrate 51Rd is adjacent to the second address auxiliary electrode 37B adjacent to the first substrate 51Rc of FIG. 11. Has a structure formed as one electrode. That is, the second address auxiliary electrode 47B has a structure equivalent to that of the first address auxiliary electrode 47T, and has, for example, a width over two adjacent lane areas ARLm and ARLm + 1. The interlayer insulating layer 15 is disposed to cover the first and second address auxiliary electrodes 47T and 47B. In addition, the first substrate 51Rd includes a common address electrode 46 disposed on the surface 15S of the interlayer insulating layer 15. The common address electrode 46 has a structure equivalent to that of the first and second address auxiliary electrodes 47T and 47B. That is, the structure of the common address electrode 46 corresponds to the structure in which two adjacent first and second common address electrodes 36T and 36B are formed as one electrode in the first substrate 51Rc of FIG. do. Specifically, the common address electrode 46 is slightly moved from the central axis in the first direction D1 to the barrier rib Bm side, for example, in the portion where the lane Lm-1 is projected along the third direction D3 on the surface 15S. It is a strip-shaped electrode which has the width | variety which reaches the position which is symmetric about the boundary (surface) between the said position and lane area | region ARLm-1, ARLm from a biased position. At this time, the common address electrode 46 and the first and second address auxiliary electrodes 47T and 47B do not have portions overlapping each other in the third direction D3. The overglaze layer 10 is disposed to cover the common address electrode 46.

According to the first substrate 51Rd according to the fourth embodiment, the number in the display area of the address auxiliary electrode 47 disposed on the surface 9S and the common address electrode 46 disposed on the surface 15S is reduced. Can be half of the number of the same electrodes in the above-described first substrates 51Ra, 51Rb, and 51Rc.

Further, according to the first substrate 51Rd, the pattern density and the space area (the area where the electrode is not arranged) of the electrodes 47 and 46 on each surface or on the formation surfaces 9S and 15S. ) Can be reduced than those in the first substrates 51Ra, 51Rb, and 51Rc described above. In other words, the line widths or widths (lengths along the second direction D2) of the respective electrodes 47 and 46 are doubled in the first substrates 51Ra, 51Rb, and 51Rc described above. This can be done. In addition, the first substrate 51Rd is, for example, between two adjacent first or second address auxiliary electrodes 37T or 37B in the first substrate 51Rc of FIG. The space area existing between the two common address electrodes 36T and 36B can be eliminated. For this reason, the space area which exists in this 1st board | substrate 51Rd is adjacent 1st and 2nd address auxiliary electrodes 47T and 47B which have a width larger than the said space area in 1st board | substrate 51Rc. Only the space area between and the space area between adjacent common address electrodes 46 are provided.

Therefore, even when the density of the lanes 35 is increased due to the high definition of the AC type PDP, the formation of the electrodes 47 and 46 is performed by the first substrates 51Ra, 51Rb, 51Rc and conventional AC. It is significantly easier than the back panel 51RP (see FIG. 31) in the type PDP. That is, according to the first substrate 51Rd, high manufacturing efficiency can be achieved. Here, for example, in the case of the first substrate 51Rd that can correspond to an SXGA-class high-definition panel having 3840 lanes, pattern formation and common of the first and second address auxiliary electrodes 47T and 47B are common. The pattern formation of the address electrode 46 is applied to a manufacturing technique of a level applied to the pattern formation of the address electrode (corresponding to the address electrode 6P in Fig. 31) in a conventional AC-type PDP of VGA class having 1920 lanes. This can be achieved.

As described above, the first substrate 51Rd is disposed between two adjacent first address auxiliary electrodes 37T or adjacent second address auxiliary electrodes 37B in the first substrate 51Rc of FIG. 11. It does not have a narrow space region existing between the first and second common address electrodes 36T and 36B. For this reason, according to the AC type PDP provided with the 1st board | substrate 51Rd concerning Example 4, the 1st board | substrate 51Rc of FIG. 11 only increased the width | variety of each electrode with which the 1st board | substrate 51Rd is equipped. It is much easier to form an electric field required to generate light discharge than an AC type PDP having a. Therefore, compared with an AC PDP having the first substrate 51Rc in Fig. 11, it is possible to further speed up the write operation and reduce the load on the driver IC for the address electrode.

Example 5

FIG. 13 is a longitudinal sectional view schematically showing a structure in a display area of a first substrate 51Re according to the fifth embodiment. As shown in FIG. 13, this 1st board | substrate 51Re is the 1st address auxiliary electrode 57T alternately arrange | positioned in the 2nd direction D2 which is an arrangement direction on the surface 9S of the back glass substrate 9, and The surface of the interlayer insulating layer 15 covering the second address auxiliary electrode 57B (collectively referred to as "address auxiliary electrode 57") and the first and second address auxiliary electrodes 57T and 57B ( And a common address electrode 56 disposed on 15S.

In particular, as can be seen by comparing the first substrate 51Re in FIG. 13 and the first substrate 51Rd in FIG. 12, in the first substrate 51Re, the substrate 51Re is viewed in the third direction D3. In this case, the pattern of the first address auxiliary electrode 57T and the second address auxiliary electrode 57B and the pattern of the common address electrode 56 are mutually spaced on each surface or on the formation surfaces 9S and 15S. It is arranged to almost complement the area. That is, the first substrate 51Re has almost no area corresponding to the gap (gap) in the second direction D2 between the electrodes 46 and 47 of the first substrate 51Rd in FIG. 12.

In detail, as shown in FIG. 13, the 1st address auxiliary electrode 57T is the said surface at the position corresponding to the center axis in the 1st direction D1 of lane Lm-2 on the said surface 9S, for example. It is a strip | belt-shaped electrode which has the width | variety which reaches the position corresponded to the center axis | shaft in the said direction D1 of lane Lm-1 adjacent to (9S) phase, and extends in 1st direction D1. Similarly, the second address auxiliary electrode 57B has, for example, a first direction having a width ranging from a position corresponding to the center axis of lane Lm on the surface 9S to an equivalent position with respect to the adjacent lane Lm + 1. It is a strip-shaped electrode extending to D1. At this time, the widths (lengths along the second direction D2) of both of the space regions between the first and second address auxiliary electrodes 57T, 57B and adjacent identical electrodes 57T, 57B are substantially the same. Do. The interlayer insulating layer 15 is disposed to cover the address auxiliary electrode 57.

The common address electrode 56 also has a structure equivalent to that of the address auxiliary electrode 57. That is, as shown in FIG. 13, the common address electrode 56 is a position corresponding to the central axis in the 1st direction D1 of the lane Lm-1 on the surface 15S of the interlayer insulation layer 15, for example. It is a strip | belt-shaped electrode which has the width | variety which reaches the position corresponding to the center axis | shaft in the said direction D1 of the lane Lm adjacent to the said surface 15S, and extends in 1st direction D1. At this time, the widths of both the common address electrode 56 and the space region between the adjacent electrodes 56 are almost the same. The widths of both the common address electrode 56 and the address auxiliary electrode 57 are almost the same. The overglaze layer 10 is disposed to cover the common address electrode 56.

In the AC type PDP including the first substrate 51Re according to the fifth embodiment, the widths of the electrodes 56 and 57 are wider than those of the AC type PDP including the first substrate 51Rd in FIG. As a result, it is easy to form an electric field for generating light discharge. Therefore, load reduction of the drive IC for address electrodes can be further promoted.

In addition, although the common address electrode 56 and the address auxiliary electrode 57 hardly overlap, the electrostatic discharge between the two electrodes 56 and 57 is lower than that of the AC type PDP including the first substrate 51Rd of FIG. The capacity is slightly increased. However, a diagram schematically showing a correlation between the field formation influence force (indicated by α in the figure) and the capacitance (indicated by β in the figure) in the discharge cell to the overlap amount between the common address electrode and the address auxiliary electrode. According to 14, it can be seen that in the case of having a gap between the positive electrodes 56 and 57, the increase rate of the electric field forming influence due to the decrease in the amount of the gap is larger than that of the capacitance. In addition, when the overlap between the two electrodes 56 and 57 overlaps, the capacitance increases sharply as the amount of overlap increases, whereas the influence of the electric field formation hardly changes. That is, according to Fig. 14, the drive, especially the write operation, of the AC type PDP can be made the fastest when there is no gap between the common address electrode and the address auxiliary electrode and no overlap. Therefore, the AC type PDP provided with the first substrate 51Re according to the fifth embodiment can be further speeded up compared to the AC type PDP provided with the first substrate 51Rd according to the fourth embodiment. have.

In addition, even when the widths of both the common address electrode and the address auxiliary electrode which are disposed over the adjacent lane areas are different from each other, the above-described effects are effective as long as there is no gap between the two electrodes and the two electrodes do not overlap. You can get it to some extent. In this case, it is noted that the above effects are maximized when the widths of both the common address electrode and the address auxiliary electrode are the same, that is, in the case of the structure shown in FIG.

<Example 6>

By the way, the common address electrode 56 and the address auxiliary electrode 57 of the first substrate 51Re of FIG. 13 are formed by a separate pattern forming process. For this reason, when a misalignment shift occurs at the time of pattern formation of each of the electrodes 56 and 57, there is an overlap in the third direction D3 between the common address electrode 56 and the address auxiliary electrode 57. The above-mentioned gap may occur. In such a case, there may occur a case where the above-described effects cannot be effectively exhibited.

Thus, in the sixth embodiment, a manufacturing method in which the first substrate 51Re of FIG. 13 is practical is described, in particular, a method of forming the common address electrode 56 and the address auxiliary electrode 57 will be described.

Below, an example of the manufacturing method of the 1st board | substrate 51Re is demonstrated as a 1st manufacturing method which concerns on Example 6 using FIGS. 15-18. 15-18 is a longitudinal cross-sectional view for demonstrating each process in the said manufacturing method. As described later, in this manufacturing method, the common address electrode 56 is patterned by using a photolithography technique using a conductor paste having negative photosensitive characteristics as a raw material of the common address electrode 56. There is a characteristic in point. It describes in detail below.

<1st process regarding a 1st manufacturing method>

In the first step, as shown in Fig. 15, the address auxiliary electrode 57 is formed in a predetermined shape at a predetermined position on the surface 9S, and the uniform interlayer insulating layer 15 having light transmittance is made of this electrode. (57) and the back glass substrate 9 of the state formed so that the said surface 9S may be covered are prepared. The address auxiliary electrode 57 is formed using, for example, a forming method such as a screen printing method, a sand blasting method, a sputtering method, or the like. The interlayer insulating layer 15 is formed of an overglaze layer such as a method of printing a low dielectric glass paste over the entire surface of the surface 9S by screen printing, and then drying and sintering the same. It is formed by an equivalent method.

<2nd process regarding 1st manufacturing method>

In the second step, first, the conductor paste 156 (see FIG. 16) having negative photosensitive property is uniformly applied on the entire surface of the surface 15S of the interlayer insulating layer 15 and subjected to an appropriate drying treatment. To dry.

Thereafter, as shown in FIG. 16, only a proper amount of light (light) of the light source for exposure that is optimal for the photosensitive characteristic of the conductor paste is vertical on the surface 9S2 side opposite to the surface 9S of the back glass substrate 9. Investigate. At this time, since the back glass substrate 9 and the interlayer insulating layer 15 are light-transmitting, the negative photosensitive conductor paste (dry film) 156 uses the light-shielding pattern of the address auxiliary electrode 57 as a mask. It exposes. That is, the negative photosensitive conductor paste 156 is photosensitive and hardened | cured as a pattern shape (Hereinafter, it expresses like "the inversion pattern of the address auxiliary electrode 57") which inverted the electrode pattern of the address auxiliary electrode 57. FIG.

<3rd process concerning a 1st manufacturing method>

Next, in the third step, by appropriately developing the negative photosensitive conductor paste (dry film) 156, only the portion not photocured in the second step is selectively removed. As a result, the negative photosensitive conductor paste 156 of FIG. 16 has a surface (negative photosensitive conductor paste (dry film) 256 having an inversion pattern of the address auxiliary electrode 57 as shown in FIG. Remaining on 15S).

<4th process concerning a 1st manufacturing method>

In the fourth step, the negative photosensitive conductor paste (dry film) 256 of FIG. 17 is sintered to complete the electrode pattern of the common address electrode 56 (see FIG. 18).

According to the manufacturing method of the 1st board | substrate provided with the 1st process-the 4th process concerning the 1st manufacturing method mentioned above, the relative mismatch of the common address electrode 56 and the address auxiliary electrode 57 shown in FIG. It can be effectively avoided.

Next, one example of another manufacturing method of the first substrate 51Re will be described as a second manufacturing method according to the sixth embodiment with reference to FIGS. 19 to 21. 19-21 is a longitudinal cross-sectional view for demonstrating each process in the said manufacturing method.

<1st process regarding a 2nd manufacturing method>

In the first step, first, the back glass substrate 9 in a state where the address auxiliary electrode 57 and the interlayer insulating layer 15 shown in FIG. 15 are formed is prepared.

<2nd process regarding 2nd manufacturing method>

In the second step, a resist film 101 (see Fig. 19) having a positive photosensitive characteristic is uniformly applied so as to cover the entire surface of the surface 15S of the interlayer insulating layer 15, and then dried. Let's do it. As shown in Fig. 19, only a proper amount of vertical irradiation of light from the light source for exposure that is optimal for positive photosensitive characteristics is performed on the surface 9S2 side opposite to the surface S of the rear glass substrate 9. At this time, since the back glass substrate 9 and the interlayer insulating layer 15 are light-transmissive, the positive photosensitive resist (dry film) 101 is formed by using the pattern of the address auxiliary electrode 57 having light shielding as a mask. Exposed. That is, the inversion pattern portion of the address auxiliary electrode 57 is photosensitive and softened in the positive photosensitive resist 101.

<3rd process concerning a 2nd manufacturing method>

In the third process, as shown in FIG. 20, by appropriately developing the exposed resist film 101, only the photosensitive portion is selectively removed in the third process. As a result, a resist 201 having the same pattern shape as the address auxiliary electrode 57 remains on the surface 15S.

<4th process concerning a 2nd manufacturing method>

Next, in the fourth step, a predetermined conductor material 356 is formed on the surface 15S on which the resist 201 is formed, as shown in FIG. At this time, the conductor material 356 is formed by a film formation method such as a sputtering method, a vacuum deposition method, or a plating method. By removing the conductor material 356 on the resist 201 by the lift-off method together with the resist 201, the electrode pattern of the common address electrode 56 shown in FIG. 18 is completed.

According to the manufacturing method of the 1st board | substrate provided with the 1st process-the 4th process concerning the above-mentioned 2nd manufacturing method, the common address electrode 56 and the address auxiliary electrode shown in FIG. 13 similarly to the above-mentioned 1st manufacturing method are shown. The relative mismatch of (57) can be effectively avoided.

In addition, the above-mentioned first and second manufacturing methods both relate to the manufacture of the common address electrode 56 and the address auxiliary electrode 57 in the display area. For this reason, the first and second manufacturing methods of the lead portions AR21 and AR22 in which the electrode patterns of the electrodes 56 and 57 do not necessarily exist at positions complementary to each other in the third direction D3 (FIG. 7). 9 and the formation of the electrode pattern in the terminal region AR3, AR31, AR32 (see FIG. 7 or FIG. 9). However, high precision alignment is not required with respect to the arrangement positions of the positive electrodes 56 and 57 throughout the lead portion regions AR21 and AR22 and the terminal portion regions AR3, AR31 and AR32. Therefore, the electrode pattern of the common address electrode 56 in the areas AR21, AR22, AR3, AR31, and AR32 is a separate one that can reliably execute the connection in the lead-out area and the display area of the electrode 56. It is noted that it can be easily formed in the manufacturing process.

<Example 7>

22 is a longitudinal sectional view schematically showing a structure in a display region of a first substrate 51Rf according to the seventh embodiment. As shown in FIG. 22, the 1st board | substrate 51Rf is the 1st common address electrode 66T and the 2nd common address electrode 66B (collectively, "the 1st board | substrate 51Rf arrange | positioned on the surface 9S of the back glass substrate 9). Common address electrode 66), a first address auxiliary electrode 67T, and a second address auxiliary electrode 67B (collectively referred to as "address auxiliary electrode 67"). Specifically, the electrode corresponds to a position corresponding to each arrangement position of the first and second address auxiliary electrodes 37T and 37B of the first substrate 51Rc shown in FIG. 11 described above on the surface 9S. First and second address auxiliary electrodes 67T and 67B that are equivalent to 37T and 37B are disposed. The electrodes 36T and 36B are positioned at positions where the respective arrangement positions of the first and second common address electrodes 36T and 36B of the first substrate 51Rc in FIG. 11 are projected on the surface 9S. And the first and second common address electrodes 66T and 66B are disposed. The overglaze layer 10 is disposed so as to cover a predetermined range of the common address electrode 66, the address auxiliary electrode 67, and the surface 9S. At this time, the overglaze layer 10 is disposed at least in the display area.

As described above, in the first substrate 51Rf, since the common address electrode 66 and the address auxiliary electrode 67 are disposed on the same surface 9S, both electrodes 66 and 67 can be formed in a lump. Can be. Therefore, when forming the positive electrodes 66 and 67 collectively, the misalignment between the patterns of the positive electrodes 66 and 67 can be effectively avoided. Moreover, according to the 1st board | substrate 51Rf, the number of manufacturing processes of a 1st board | substrate is significantly reduced compared with the manufacturing method of 1st board | substrate 51Ra, 51Rb, 51Rc, 51Rd, and 51Re mentioned above. This is advantageous in that it can be made equivalent to the number of manufacturing steps on the back glass substrate 9P side in the conventional AC PDP 51P shown in FIG. 31.

<Example 8>

When collectively forming the common address electrode 66 and the address auxiliary electrode 67 of the first substrate 51Rf described above, the number of electrodes to be formed on the surface 9S is determined by the conventional AC type PDP 51P. Since it is twice as large as the address electrode 6P, its formation requires a high density pattern formation technique. Thus, in the eighth embodiment, a first substrate having a structure that does not require such a high density pattern formation technique will be described.

FIG. 23 is a longitudinal sectional view schematically showing a structure in a display region of a first substrate 51Rg according to the eighth embodiment. As shown in FIG. 23, the first substrate 51Rg includes a common address electrode 76, a first address auxiliary electrode 77T, and a second address auxiliary electrode disposed on the surface 9S of the rear glass substrate 9. 77B (collectively also referred to as "address auxiliary electrode 77"). In detail, it corresponds to each arrangement position of the 1st and 2nd address auxiliary electrodes 47T and 47B of the 1st board | substrate 51Rd concerning Example 4 shown in FIG. 12 mentioned above on the said surface 9S. The first and second address auxiliary electrodes 77T and 77B which are equivalent to the electrodes 47T and 47B are disposed at the positions. The common address electrode 76 equivalent to the electrode 46 is disposed at the position where the arrangement position of the common address electrode 46 of the first substrate 51Rd of FIG. 12 is projected on the surface 9S. The overglaze layer 10 is disposed so as to cover a predetermined range of the common address electrode 76, the address auxiliary electrode 77, and the surface 9S. At this time, the overglaze layer 10 is disposed at least in the display area.

According to such a first substrate 51Rg, the pattern density of the common address electrode 76 and the address auxiliary electrode 77 can be made about the same as that of the conventional AC PDP 51P (see FIG. 31). Therefore, even when both electrodes 76 and 77 are collectively formed, a high density pattern formation technique is not required. Of course, the same effects and advantages as those of the first substrate 51Rf according to the seventh embodiment can be obtained.

24 is a top view which shows typically the arrangement form of each electrode 76 and 77 of the 1st board | substrate 52Rg. As shown in FIG. 24, the common address electrode 76 extends through the lower lead-out area AR22 to the lower terminal area AR32, and the terminal 763 for the common address electrode 76 is formed by the end in the terminal area AR32. ). In contrast, the address auxiliary electrode 77 extends through the upper lead portion region AR21 to the upper terminal portion region AR31. The second address auxiliary electrode 77B is connected to a common electrode portion 77B2 (wiring portion) corresponding to the common electrode portion 17B2 of FIG. 7 disposed in the upper terminal portion region AR31. The second common electrode portion 77B2 may be a terminal of the second address auxiliary electrode 77B, or a terminal corresponding to the terminal 17B3 in FIG. 7 may be separately provided. On the other hand, the first address auxiliary electrode 77T is disposed between the end of the electrode 77T or the terminal 77T3 in the upper terminal portion area AR31 and the output terminal of the drive circuit for the electrode 77T not shown in FIG. Commonly connected in paths or relay wirings.

According to such a wiring pattern, the terminals of the electrodes 76 and 77 are dispersed above and below the rear glass substrate 9, so that high-density mounting in the terminal areas AR31 and AR32 can be effectively avoided. have.

<Modification 1 of Example 8>

In the first modified example, another example of the structure in the lead-out area and the terminal area of the first and second address auxiliary electrodes 77T and 77B of the first substrate 51Rg described above is shown in FIGS. 25 and FIG. It demonstrates using 26. FIG. 25 is an enlarged plan view of the main portion for explaining such a structure, and FIG. 26 is a view when the longitudinal section in the line I-I in FIG. 25 is viewed from the arrow direction.

25 and 26, the second address auxiliary electrode 77B extends from the display area AR1 (see FIG. 24) to the upper lead-out area AR21, and in the area AR21 the common electrode part 77B2. ) And the terminal 77B3 for the 2nd address auxiliary electrode 77B which extends in the terminal part area | region AR31 from the desired position of the common electrode part 77B2 is arrange | positioned. And on the surface 9S of the back glass substrate 9, the electrode arrange | positioned in the said range is covered in the predetermined | prescribed range on the lead-out area | region AR21 side or the display area AR1 side by the boundary of the lead-out area | region AR21 and the terminal part area | region AR31. The insulating layer 5 is arrange | positioned.

And the common electrode part (wiring part) equivalent to the common electrode part 17T2 shown in FIG. 7 mentioned above on the surface 75S which is not in contact with the surface 9S of the back glass substrate 9 of the insulating layer 75. ) 77T2 is disposed. The common electrode portion 77T2 and the first address auxiliary electrode 77T are connected to each other by a wiring portion 177T, a part of which is disposed on the surface 75S. And the terminal 77T3 for the 1st address auxiliary electrode 77T which extends toward the inside of the terminal part area | region AR31 at the desired position of the common electrode part 77T2 is arrange | positioned.

According to this structure, the relay wiring from the terminals 77T3 and 77B3 to the output terminals of the respective driving circuits for the first and second address auxiliary electrodes 77T and 77B is shown in FIG. This is simpler than in the case of one structure. That is, in the structure shown in FIG. 24, it is necessary to prepare (one or several) FPCs corresponding to the number of terminals and the arrangement pitch of the terminals 77T3 for the first address auxiliary electrode 77T. As described above, the path must be connected in common between the terminal 77T3 and the output terminal of the drive circuit for the first address auxiliary electrode 77T. In addition, the terminal of the FPC and the terminal 77T3 must be aligned and mounted.

On the other hand, according to the structure shown in Figs. 25 and 26, any one of the terminals 77T3 and 77B3 of the first and second address auxiliary electrodes 77T and 77B is also desired as many times as desired. It is possible to form. Therefore, as a relay wiring between the terminals 77T3 and 77B3 and the output terminals of the respective drive circuits for the electrodes 77T and 77B, a flat cable FFC which is cheaper than FPC can be used. At this time, the connection of the terminals 77T3 and 77B3 and the flat cable does not require a high-level alignment process. Thus, according to the structure shown in FIG. 25, the said relay wiring can be made simpler than the case of the structure shown in FIG. Further, as a result, there is an advantage that the material cost and manufacturing cost for the relay wiring can be greatly reduced.

Instead of the insulating layer 75, the overglaze layer 10 (for example, see FIG. 23) is extended to the lead-out area AR21, and a structure such as a contact hole is provided in the overglaze layer 10. By this, you may form the structure equivalent to the structure shown in FIG. In such a case, it is possible to avoid the need to separately provide a step of forming the insulating layer 75.

<Modification 2 related to Example 8>

In the second modified example, the arrangement of the electrodes in the case where the first substrate 51Rg according to the eighth embodiment is applied to an AC type PDP that is compatible with the so-called up-and-down block parallel address system will be described. In addition, in this modification 2, the common address electrode 76 of the 1st board | substrate 51Rg is divided up and down in the center of display area AR1 like the common address electrode 16 shown in FIG. In addition, the terminals for the common address electrodes 76 belonging to each of the upper and lower display regions AR11 and AR12 (see FIG. 9) are provided in the upper or lower terminal portion regions AR31 and AR32.

At this time, when both the terminals for the first and second address auxiliary electrodes 77T and 77B are concentrated on one of the upper or lower terminal portion regions AR31 and AR32, the terminal 763 for the common address electrode 76 is provided. ), The arrangement density or the pattern density of the terminals in the region AR31 or AR32 becomes very high. For this reason, it is preferable to provide each terminal for the 1st and 2nd address auxiliary electrodes 77T and 77B in each terminal part area | region AR31 and AR32.

For example, as shown in FIG. 24, the common address electrode in the lead-out area | region AR22 and the terminal part area | region AR32 (in this case, correspond to each area | region 22 and 32 for the lower block of FIG. 9). An array interval (pitch) of 76 is set smaller than that in the display area AR1. In such a structure, in the case where the address auxiliary electrode 77 is extended to the regions AR22 and AR32 as it is, the common electrode portions 77T2 and 77B2 (for example, see FIG. 7) are reached. The plurality of address auxiliary electrodes 77 are guided to a region where the common address electrodes 76 (terminals) are concentrated. Such a high-density wiring pattern is undesirable from the viewpoint of the forming technique and the mounting technique.

One structure which can solve such a problem is demonstrated using FIG. 27 and FIG. 28 as a 1st board | substrate 51Rg which concerns on this 2nd modification. FIG. 27 is an enlarged plan view of the vicinity of the upper lead-out area AR21 and the upper terminal part area AR31 corresponding to FIG. 25 described above, and FIG. 28 is a view in the longitudinal cross-sectional view taken along the line II-II in FIG. Here, as illustrated in FIG. 27, a structure in which the first address auxiliary electrode 77T is drawn out in the upper lead-out area AR21 and the upper terminal part area AR31 will be described. The lower side in which the second address auxiliary electrode 77B is drawn out will be described. The structure of the lead-out area AR22 and the lower terminal part area AR32 (both refer to Fig. 9, for example) merely uses the following description regarding the areas AR21 and AR31.

As shown in FIG. 27, the structures of the upper lead-out area AR21 and the terminal area AR31 of the common address electrode 76 are the same as the structures of the lower lead-out area AR32 and the terminal area AR32 of FIG. 24 described above. .

As shown in Figs. 27 and 28, the first address auxiliary electrode 77T is a predetermined position in the lead-out area AR21 in the display area AR1 (it is preferably an area in which the common address electrodes 76 are not concentrated). It extends to the furnace and is formed. The insulating layer 175 equivalent to the insulating layer 75 shown in Figs. 25 and 26 described above is disposed so as to cover a part of the common address electrode 76 in the lead-out area AR21.

And common electrode part 77T2 is arrange | positioned on the surface 175S which is not in contact with the surface 9S of the back glass substrate 9 of the insulating layer 175. As shown in FIG. Such a common electrode portion 77T2 and a first address auxiliary electrode 77T have a wiring portion 277T whose portion is disposed on the surface 175S (corresponding to the wiring portion 177T in FIGS. 25 and 26). It is connected by. Then, the terminal 77T3 for the first address auxiliary electrode 77T extending from the common electrode portion 77T2 toward the region where the terminal 763 for the common address electrode 76 is not concentrated in the terminal portion region AR31 is disposed. It is.

At this time, similarly to the modification 1 described above, the insulating layer is formed on the layer 10 by forming the overglaze layer 10 (for example, see FIG. 23) formed to extend to the lead-out area AR21 in an appropriate shape. You may give a role equivalent to (175).

According to the first substrate 51Rg according to the second modification having such a structure, the above-described problems due to the higher density of the wirings in the lead-out area and the terminal area can be reliably avoided.

In addition, the above-described structure of the address auxiliary electrode in the lead-out region and the terminal portion region provides the first and second address auxiliary electrodes 77T, 77B terminals 77T3, 77B3 in the respective terminal portion regions. Note that the present invention is applicable to the case where the shape of the common address electrode 76 is not limited to the case where the shape of the common address electrode 76 corresponds to the upper and lower block parallel addressing schemes.

Example 9

In Example 9, the driving method in the sustain period S in the case where the AC type PDP provided with each of the above-mentioned first substrates is driven by the driving method according to the premise technique will be described with reference to FIG. 29 is a timing chart showing waveforms of voltages applied to respective electrodes in the sustain period S in the driving method according to the ninth embodiment. 29A to 29C are timing diagrams of respective voltages VT, VB, and VAk (k: 1 to j) applied to the first address auxiliary electrode, the second address auxiliary electrode, and the common address electrode PAk, respectively. Figure is a diagram. (D) in FIG. 29 shows the voltage VX0 which is applied to all the sustain electrodes X1 to XN in common, and (e) shows the voltage VY0 which is applied to all the scan electrodes Y1 to YN in common. The timing diagrams of the voltage VX0 and the voltage VY0 are the same as those of (b) and (c) to (e) in FIGS. Here, the AC type PDP according to the first embodiment shown in Fig. 6 described above will be described as an example.

As shown in FIG. 29, in the sustain period S0, the same voltage Va as the voltages VT, VB, and VAk is applied to the first and second address auxiliary electrodes and the common address electrode PAk. The driving method in FIG. 1 to FIG. 3 can be realized. By applying the same voltage Va to all the electrodes of the first substrate in this way, the surface discharge DC2 between the electrode pairs Xn and Yn is equal to the voltage Va applied to the address electrode in the same manner as in the driving method according to the prior art. The starting voltage of can be made the lowest. That is, when the sustain pulse Vs is applied to the sustain electrode Xn or the scan electrode Yn, the potential in the discharge space 51S near the surface of the discharge space 51S side of the phosphor 8 in FIG. In the discharge space 51S in the vicinity of the potential near the portion corresponding to the central axis of the internal gap G (the (three-dimensional) region between the opposing edges of the paired electrodes Xn and Yn (see Fig. 5)). You can almost match it. As a result, since the electric field distribution of the discharge space 51S above the inner gap G can be made symmetrical, the surface discharge DC2 between the electrode pairs Xn and Yn can be started by the voltage Vs of the required minimum voltage value. Therefore, according to the voltage setting mentioned above, efficient surface discharge or sustain discharge DC2 can be obtained.

<Example 10>

In the tenth embodiment, as a driving method of the AC-type PDP provided with each of the above-mentioned first substrates, a driving method capable of suppressing and removing moving image contours in image display will be described with reference to FIG. Explain. 30 is a diagram for explaining the subfield division form of one screen and each period in each subfield in this driving method. In this case, the case of performing image display of 256 gradations is described as an example.

As shown in Fig. 30, in the present driving method, the video display time for one screen is equal to the subfields SF1 to SF7 equivalent to the driving method (see Fig. 1) related to the premise technique, and the subfields SF8A and subcharacteristics of the present driving method. The field is divided into SF8B. In other words, in this driving method, the subfield SF8 having the maximum number of sustain pulses in the sustain period S of the driving method according to the prior art is divided into two subfields SF8A and SF8B. As shown in Fig. 30, the nine subfields are executed in the order of the subfields SF1, SF2, SF8A, SF3, SF4, SF8B, SF5, SF6, SF.

As shown in Fig. 30, each of the subfields of the subfields SF1 to SF7 continues in the erasing period R and the erasing period R in which the same operation as that of any one of the erasing periods RA or RB in the premise description is performed. Thus, the period in which the same operation as in the above-described address period AD0 (see FIG. 8) is executed and the driving method described in the ninth embodiment are made up of the sustain period S which is continued in the address period AD0. In the erasing period R (RA or RB), a voltage capable of performing a predetermined erasing operation in accordance with the prior art is applied to the common address electrode and the address auxiliary electrode.

In contrast, in the subfield SF8A, the address period AD1 including only the first period AD1 of the address period AD0 is provided instead of the address period AD0 described above. On the other hand, in the subfield SF8B, the address period AD2 including only the second period AD2 of the address period AD0 is provided instead of the address period AD0. The erasing period and the sustain period of each of the subfields SF8A and SF8B are the same as those of the subfields SF1 to SF7. At this time, the number of sustain pulses in either of the sustain periods S0 in the subfields SF8A and SF8B is the same as that in the subfield SF8 (see Fig. 1) according to the premise technique.

In the subfields SF8A and SF8B having such a configuration, the write operation is performed only for half of all the discharge cells belonging to the entire screen or the entire lane 35 (see Fig. 6, for example) in the address period AD1 or AD2. For this reason, in the sustain period S0, image display for the discharge cells belonging to half of the lanes 35 of the total number is executed. In the sustain period S0 of the subfield SF7, the sustain discharge of all the discharge cells (that is, the entire lane 35) is executed by about half of the pulses compared to the number of sustain pulses of the subfields SF8A and SF8B. Therefore, on average, the three subfields SF8A, SF8B and SF7 have the same level of light emission intensity and have the largest weight or rank among the series of nine subfields. Therefore, by subdividing the subfields SF8A, SF8B and SF7 as shown in Fig. 30 so as not to be biased within the video display time for one screen, it is possible to improve the moving picture-like outline.

The first substrate of each AC type PDP according to Examples 1 to 10 may have a structure without the overglaze layer 10.

[1] According to the present invention, when the AC surface discharge type plasma display panel is driven, a common (same) voltage is applied to each of the first to s-th common address electrodes in a group unit, and the plurality of j-th address auxiliary electrodes are simultaneously applied. When a discharge is generated in a discharge cell belonging to a predetermined lane region by applying a common (same) voltage between groups, the number of driving circuits for supplying a driving voltage to the common address electrode is the number of the groups of the common address electrode. Is enough. Further, s drive circuits for driving the address auxiliary electrodes of the entire panel may be used. As described above, since it is not necessary to provide the driving circuit for each address electrode as in the conventional driving method, an AC surface discharge type plasma display panel capable of significantly reducing the cost of the driving circuit can be obtained.

In addition, in the above-mentioned case, even when the terminal for common address electrode for connecting the output terminal of the said drive circuit for common address electrodes is provided in the 1st board | substrate side, the number is sufficient as the said number of groups. Similarly, even when the address auxiliary electrode terminals for connecting the output terminals of the drive circuit for the address auxiliary electrodes of the entire panel are provided on the first substrate side, the number of electrically independent numbers thereof may be s. In this way, the arrangement density of both terminals is significantly reduced than that of the address electrode terminal of the conventional plasma display panel. Therefore, the mounting density of each terminal of the AC surface discharge type plasma display panel and each output terminal of the driving circuit can be significantly reduced than that of the conventional plasma display panel, so that the manufacturing cost can be reduced.

For this reason, according to the invention [1], it is possible to obtain an AC surface discharge plasma display panel with higher definition and to provide an AC surface discharge plasma display panel at low cost.

[2] Further, according to the present invention, since the first to s common address electrodes are commonly connected in group units, and the plurality of j th address auxiliary electrodes are commonly connected to the entire AC surface discharge type plasma display panel, It is possible to provide an AC surface discharge type plasma display panel which can exhibit the effect of the [1].

[3] In addition, according to the present invention, the common address electrode and the address auxiliary electrode are arranged on the respective planes in the display area. For this reason, compared with the case where both electrodes are arrange | positioned on the same plane, the density of the electrode pattern on one plane is low. Therefore, compared with the case where both electrodes are collectively formed on the same plane, an electrode pattern having a predetermined shape can be reliably formed.

[4] According to the present invention, the electrode farther from the second substrate is compared with the case where the common address electrode and the address auxiliary electrode have portions overlapping each other in the direction perpendicular to the surface of the substrate included in the first substrate. The electric field by each voltage applied to can be used more effectively at the time of forming an electric field in the discharge space. Therefore, when appropriately setting the voltage applied to each electrode, it is possible to more reliably generate the light discharge and the sustain discharge in the predetermined discharge cell, as compared with the plasma display panel having the structure overlapping each other.

In addition, according to the invention [4], the capacitance between the common address electrode and the address auxiliary electrode is smaller than that in the case where both electrodes have portions overlapping each other. Therefore, compared with the plasma display panel having the structure having the portions overlapping each other, it is possible to speed up the write operation in the address period.

[5] According to the present invention, compared to the AC surface discharge type plasma display panel according to the invention described in [4] above, each width (length in the arrangement direction of the electrodes) of the common address electrode and the address auxiliary electrode is maximized. It is possible to set. For this reason, the influence of the electric field by the voltage applied to each electrode on the electric field formation in a discharge space can be made larger than the AC surface discharge type plasma display panel which concerns on the invention as described in said [4]. Therefore, since the voltage applied to each electrode can be reduced, the load of the driving circuit for the common address electrode can be reduced. At this time, since a large increase in the capacitance between the common address electrode and the address auxiliary electrode does not occur, the write operation in the address period is performed in comparison with the AC surface discharge type plasma display panel according to the invention described in [4] above. It can run faster.

[6] According to the present invention, when the common address electrode and the address auxiliary electrode are collectively formed, the number of steps in the formation process of both electrodes can be reduced.

[7] According to the present invention, at least a part of the j-th address auxiliary electrode belonging to a different group is not disposed in each of two adjacent lane areas. For this reason, for example, light discharge is generated in the discharge space of the discharge cells belonging to one lane area according to the image data for two adjacent lane areas, and in the discharge space of the discharge cells belonging to the other lane area. Even when driving so as not to cause light discharge, generation of ore discharge in a discharge cell belonging to the other lane region as compared with the structure in which both j-th address auxiliary electrodes are arranged in each of two adjacent lane regions. Can be greatly suppressed.

[8] According to the present invention, several address auxiliary electrodes are classified into two types of address auxiliary electrodes. Therefore, an effect similar to the above-mentioned [1] to [7] can be obtained by the AC surface discharge type plasma display panel having a very simple structure.

[9] According to the present invention, when write discharge is generated in a discharge cell of a lane area to which one j-th address auxiliary electrode of a plurality of j-th address auxiliary electrodes belongs, another j-th address auxiliary electrode belonging to an adjacent lane area is generated. The electric field by the voltage applied to assists the formation of the electric field required for generation of the light discharge. For this reason, generation | occurrence | production of light discharge can be made easier. Thus, the load on the switching operation of the driving circuit for the common address electrode can be reduced. In addition, the recording operation can be speeded up.

[10] According to the present invention, an effect similar to the above-mentioned [1] to [6] and [9] can be obtained by an AC surface discharge type plasma display panel having a very simple structure.

According to the present invention, most of the influence of the electric field due to the voltage applied to the common address electrode on the electric field formation in the discharge space can be concentrated in the discharge cell to which the common address electrode belongs. Therefore, when regular light discharge is generated in a predetermined discharge cell, generation of ore discharge in the discharge cell adjacent to the discharge cell can be effectively suppressed.

[12] According to the present invention, the effect of the electric field due to the voltage applied to the electrode having the pattern shape over the adjacent lane area on the electric field formation in the discharge space is the same type of electrode (at least of the common address electrode and the address auxiliary electrode). One side) is much stronger than the electric field in the structure (refer to [11] mentioned above) of each adjacent lane area | region. For this reason, the electric field required for generation of light discharge can be formed more easily, and such light discharge can be easily generated. Therefore, the respective voltages related to the light discharge can be reduced, so that the load of the driving circuit for the common address electrode can be reduced and the speed of the write operation can be further increased.

The number of such predetermined electrodes can be halved as compared to the structure in which the predetermined electrodes described above are arranged in adjacent lane regions (see [11] above). Therefore, by reducing the pattern density of the predetermined electrode, it is possible to suppress and eliminate problems related to high-density electrode patterns.

[13] According to the present invention, each of the wiring portions of the first and second address auxiliary electrodes and the respective terminals for the electrodes is disposed in predetermined regions on the opposite sides via the display region. For this reason, the wiring pattern of the address auxiliary electrode on the outer side of the display area can be made very simple. Further, even when a plurality of first or second address auxiliary electrodes are commonly connected outside of the display area, the wiring pattern for connecting in common can be formed in a very simple shape. At this time, since there is no need to provide a terminal for each of the plurality of electrodes, the mounting density of each terminal and the output terminal of the electrode driving circuit can be greatly reduced.

According to the present invention, since the wiring portion of each electrode is arranged three-dimensionally through the insulating layer, the complexity of the wiring pattern on the outside of the display area can be suppressed. At this time, since a large degree of freedom can be given to the arrangement position of each electrode terminal, high density mounting between each terminal and the output terminal of a drive circuit can be avoided.

[15] According to the present invention, the effect of any one of the above [1] to [14] is exerted, whereby a plasma display device with higher definition can be provided.

According to the present invention, in the address period, since the same voltage is applied to each of the first to s common address electrodes in each group unit, the number of driving circuits for supplying the driving voltage to the common address electrode is the common address electrode. The number of said groups of is enough. In other words, since it is possible to eliminate the need to provide a driving circuit for each common address electrode as in the conventional driving method, the cost for the driving circuit can be significantly reduced.

The number of terminals for the common address electrode for connecting the output terminal of the drive circuit is also sufficient for the group number. That is, the arrangement density of the terminal can be significantly reduced than that of the conventional plasma display panel. For this reason, since the mounting density of the said terminal of the AC surface discharge type plasma display panel to which the said drive method is applied, and the output terminal of the said drive circuit is alleviated significantly compared with the case of the conventional plasma display panel, manufacturing cost can also be reduced. .

Therefore, according to the invention described in the above [16], even a plasma display device including the plasma display panel with higher definition can be provided at low cost.

[17] According to the present invention, only the discharge cells belonging to the lane region to which both the common address electrode to which the first voltage is applied and the address auxiliary electrode to which the third voltage is applied belong, are surely discharged independently of other discharge cells. Can be generated.

According to the present invention, the write operation in the address period can be performed for all the discharge cells of the AC surface discharge type plasma display panel. Therefore, the above recording operation can be performed with the above-described effect [16] or [17] also for a highly sharpened AC surface discharge type plasma display panel.

In this case, s driving circuits for driving the address auxiliary electrodes of the entire plasma display panel may be sufficient. Therefore, the cost regarding the drive circuit can be further reduced. Similarly, even when an address auxiliary electrode terminal for connecting the output terminal of the address auxiliary electrode driving circuit of the entire plasma display panel is provided on the first substrate side, the number of electrically independent of them may be s. For this reason, since the arrangement density of the said both terminals can be reduced significantly compared with that of the address electrode terminal in the conventional plasma display panel, the above-mentioned manufacturing cost can be reduced further.

According to the present invention, for example, when a plurality of lane regions are classified into first and second lane regions, an address period for generating write discharge only in discharge cells belonging to the first or second lane regions is provided. When both of the subfields are set in a subfield having a high light emission intensity in the sustain period, and arranged so as not to deviate in time within the video display time for one screen, the moving picture-like outline can be improved.

According to the present invention, since the discharge start voltage of the surface discharge between the electrode pairs can be minimized, as a result, an efficient sustain discharge can be obtained.

[21] According to the present invention, the effect of any one of the above [16] to [20] can be exerted to provide a plasma display device with higher definition.

[22] According to the present invention, the common address electrode and the address auxiliary electrode in the first substrate of the AC surface discharge type plasma display panel described in [5] above can be formed without causing misalignment.

Claims (3)

A plurality of band-shaped common address electrodes arranged in parallel with each other in the display area on at least one surface side of the substrate and classified into groups each consisting of first to s (s is an integer of two or more) common address electrodes. And a first substrate having a plurality of band-shaped address auxiliary electrodes each classified into a group consisting of first to s-address auxiliary electrodes; Are arranged to cover the plurality of electrode pairs and the plurality of electrode pairs each including a stripe scan electrode and a sustain electrode arranged in parallel with each other and in a direction three-dimensionally intersecting the common address electrode and the address auxiliary electrode. A second substrate having a dielectric, The space between the first substrate and the second substrate is disposed through barrier ribs having a component for partitioning the space between the common address electrode and the address auxiliary electrode into a plurality of discharge spaces filled with discharge gas; , A plurality of discharge cells formed by each intersection of the electrode region and the lane region defined as the region between the centers in the longitudinal direction of each of the two adjacent barrier ribs, The plurality of lane areas may include a first to s-lane area in which at least a portion of the j-th common address electrode and at least a portion of the j-th address auxiliary electrode are disposed in the j-th (1 ≦ j ≦ s) lane area. AC surface discharge type plasma display panel characterized by being classified into a group consisting of. The method of claim 1, And at least one of the common address electrode and the address auxiliary electrode has a pattern shape over two adjacent lane areas. The method of claim 1, After dividing an image display time for one screen into a plurality of subfields, each of the plurality of subfields generates light discharge in accordance with image data in the predetermined discharge cell at least in synchronization with the selective scan of the scan electrode. In the case of having an address period to cause and a sustain period for generating a predetermined number of sustain discharges in the discharge cell in which the write discharge has occurred, In the address period, any one of the first voltage or the second voltage according to the image data of the discharge cell belonging to the j-th lane area of each group belongs to the group in the group unit. When commonly applied to the s common address electrode, a voltage value different from the third voltage is applied to the address auxiliary electrodes other than the j address auxiliary electrode while applying a third voltage to the j th address auxiliary electrode. And applying a fourth voltage having the AC surface discharge type plasma display panel.