KR20020011475A - A damascene process included low dielectric insulating layer - Google Patents

A damascene process included low dielectric insulating layer Download PDF

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KR20020011475A
KR20020011475A KR1020000044754A KR20000044754A KR20020011475A KR 20020011475 A KR20020011475 A KR 20020011475A KR 1020000044754 A KR1020000044754 A KR 1020000044754A KR 20000044754 A KR20000044754 A KR 20000044754A KR 20020011475 A KR20020011475 A KR 20020011475A
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low dielectric
trench
dielectric constant
layer
damascene process
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KR1020000044754A
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Korean (ko)
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선정민
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박종섭
주식회사 하이닉스반도체
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Publication of KR20020011475A publication Critical patent/KR20020011475A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A damascene method including a low dielectric insulation layer is provided to prevent a delay caused by an RC component and to improve an insulation characteristic, by maintaining a low dielectric characteristic of an insulation material to manufacture a semiconductor device. CONSTITUTION: An interlayer dielectric(104) is formed on a silicon substrate(100). An etch barrier layer(106) is formed on the interlayer dielectric. An interline dielectric is formed on the etch barrier layer. A trench hole(110) is firstly formed on the interline dielectric to be adhered to a predetermined region of the silicon substrate. A diffusion barrier layer(112) is formed on the inner surface of the trench hole. The trench hole having the diffusion barrier layer is filled with a metal to form a trench. The interline dielectric formed near the trench is eliminated. A predetermined insulation sub layer(116) is deposited on the etch barrier layer and the trench where the interline dielectric is eliminated. After the space between the trenches on which the insulation sub layer is deposited is filled with a low dielectric material, a heat treatment process is performed at a predetermined temperature to maintain the low dielectric characteristic of the low dielectric material.

Description

저유전율 절연막이 포함된 다마신공정법{A DAMASCENE PROCESS INCLUDED LOW DIELECTRIC INSULATING LAYER}A DAMASCENE PROCESS INCLUDED LOW DIELECTRIC INSULATING LAYER}

본 발명은 다마신(damascene)공정에 관한 것으로, 트렌치 상부에 절연보조층을 형성시키고 그 사이에 저유전율 절연물질을 매립한 다음, 낮은 온도에서 어닐링을 실시함으로써, 저유전율 특성을 유지시켜 RC 성분에 의한 지연을 방지할 수 있는, 저유전율 절연막이 포함된 다마신공정법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a damascene process, wherein an insulating auxiliary layer is formed on a trench, a low dielectric constant insulating material is interposed therebetween, and then annealing is performed at a low temperature to maintain low dielectric constant characteristics. The damascene process method which the low dielectric constant insulating film which can prevent the delay by the same is included.

메모리소자의 집적도가 증가함에 따라, 향후 금속배선 형성방법이 기존의 반응성이온식각법(RIE)대신 다마신(damascene)방법으로 변화를 추구하고 있다. 이러한 다마신방법은 비아(Via)의 매립이 가능하고 비용을 최소화하면서도 소자의 특성이 양호하게 개선시킬 수 있다. 아울러 디자인 룰이 작은 고집적 논리소자 및 메모리소자에서 광범위하게 적용이 가능하다.As the integration of memory devices increases, metal wiring forming methods are being changed to damascene instead of conventional reactive ion etching (RIE). This damascene method allows the filling of vias and can improve the characteristics of the device while minimizing costs. In addition, the design rule is widely applicable to small integrated logic and memory devices.

반도체소자는 각각의 층들을 상부로 쌓아 올리면서 기판에 형성된 개개의 소자들을 금속선으로 연결하여 회로를 만들어 간다. 금속콘택과 상부의 금속배선을 각각 분리하여 실시하였던 것과는 달리, 각 층을 잇는 구멍과 각 층의 금속선을 한번에 형성하는 이중다마신(dual damascene) 공정은 공정의 단순화 등 잇점이 있어 반도체공정에서 많이 이용되고 있다.The semiconductor device builds a circuit by connecting individual devices formed on the substrate with metal wires while stacking the respective layers upward. Unlike the metal contact and the upper metal wiring, which are separated from each other, the dual damascene process that forms the holes connecting the layers and the metal wires of each layer at a time has advantages such as the simplification of the process. It is used.

그러나, 전술한 종래 다마신 공정은 다음과 같은 문제점이 있다.However, the above-described conventional damascene process has the following problems.

즉 다층구조의 첫번째 층에서 기판과의 콘택하기 위해 다마신 공정을 적용하는 경우 콘택저항을 낮추기 위해서는, 공정온도를 기판의 실리콘과 콘택홀의 장벽금속인 티타늄(Ti)간 Ti-Si의 실리콘화반응(silicidation) 온도(약 650℃)보다 높게 설정하여 RTA(Rapid Thermal Annealing;급속열처리)를 실시해 주어야 한다. 하지만 이러한 공정온도는 금속배선 사이에 증착되는 약 2.7∼3.0의 저유전율 절연막의 분자구조를, 고유의 비유전율을 갖도록 변화시킴으로써 RC 지연(RC delay)을 초래하는 문제점이 있다.That is, when the damascene process is applied to contact the substrate in the first layer of the multilayer structure, the siliconization reaction of Ti-Si between the silicon of the substrate and titanium (Ti), which is a barrier metal of the contact hole, is used to reduce the contact resistance. (silicidation) It should be set higher than the temperature (about 650 ℃) and RTA (Rapid Thermal Annealing) should be performed. However, such a process temperature causes a problem of RC delay by changing the molecular structure of the low dielectric constant insulating film of about 2.7 to 3.0 deposited between metal wirings to have an intrinsic dielectric constant.

따라서 전술한 문제점을 해결하기 위한 본 발명의 목적은, 형성된 트렌치 상부에 절연보조층을 형성시키고 그 사이에 저유전율 절연물질을 매립한 후 낮은 온도에서 어닐링을 실시함으로써, 저유전율 특성을 유지시켜 RC 성분에 의한 지연을 방지할 수 있는, 저유전율 절연막이 포함된 다마신공정법을 제공하는 데 있다.Therefore, an object of the present invention for solving the above problems, by forming an insulating auxiliary layer on the formed trench, and embedding a low dielectric constant insulating material therebetween and performing annealing at a low temperature, thereby maintaining the low dielectric constant characteristics RC The present invention provides a damascene process method including a low dielectric constant insulating film capable of preventing delay caused by components.

도 1a 내지 도 1e는 본 발명의 일실시예에 따른 트렌치 형성과정을 설명하기 위한 공정도.1A to 1E are flowcharts illustrating a trench formation process according to an embodiment of the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

100 : 기판 102 : 콘택영역100 substrate 102 contact region

104 : 층간절연막 106 : 식각차단막104: interlayer insulating film 106: etch stop film

108 : 선간절연막 110 : 트렌치홀108: line insulating film 110: trench hole

112 : 확산방지막 114 : 금속매립층112: diffusion barrier 114: metal buried layer

116 : 절연보조층 118 : 저유전율 절연막116: insulating auxiliary layer 118: low dielectric constant insulating film

본 발명에 따른 저유전율 절연막이 포함된 다마신공정법은, 반도체소자의 다마신 공정에 있어서,In the damascene process method including the low dielectric constant insulating film according to the present invention, in the damascene process of a semiconductor device,

실리콘기판 상부에 층간절연막을 형성하는 제1단계; 상기 형성된 층간절연막의 상부에 식각차단을 위한 식각차단막을 형성하는 제2단계; 상기 식각차단막의 상부에 선간절연막을 형성하는 제3단계; 상기 실리콘기판의 소정영역에 접합될 수 있도록 상기 선간절연막에서부터 트렌치홀을 형성하는 제4단계; 확산을 방지하기 위해 상기 트렌치홀의 내부표면에 확산방지막을 형성하는 제5단계; 상기 확산방지막이 형성된 상기 트렌치홀을 금속으로 매립하여 트렌치를 형성하는 제6단계; 상기 트렌치 주위에 형성되어 있는 상기 선간절연막을 제거하는 제7단계; 선간절연막이 제거된 상기 식각차단막 및 트렌치 표면에 소정의 절연보조층을 증착하는 제8단계; 및, 상기 절연보조층이 증착된 상기 트렌치 사이의 공간을 저유전율물질로 매립한 후, 상기 저유전율물질의 저유전율 특성이 유지되도록 소정의 온도에서 열처리하는 제9단계를 포함한다.A first step of forming an interlayer insulating film on the silicon substrate; Forming an etch barrier layer on the formed interlayer insulating layer to etch off the interlayer insulating layer; Forming a line insulating layer on the etch barrier layer; Forming a trench hole from the interlayer insulating layer so as to be bonded to a predetermined region of the silicon substrate; Forming a diffusion barrier on the inner surface of the trench hole to prevent diffusion; A sixth step of forming a trench by filling the trench hole in which the diffusion barrier layer is formed of metal; A seventh step of removing the interlayer insulating film formed around the trench; An eighth step of depositing a predetermined insulating auxiliary layer on the etch barrier layer and the trench surface from which the line insulating layer is removed; And a ninth step of filling a space between the trenches on which the insulating auxiliary layer is deposited with a low dielectric constant material, and then performing heat treatment at a predetermined temperature to maintain a low dielectric constant of the low dielectric constant material.

이하 도면들을 참조하여 본 발명의 바람직한 실시예를 자세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1e는 본 발명의 일실시예에 따른 트렌치 형성과정을 설명하기 위한 공정도이다.1A to 1E are flowcharts illustrating a trench forming process according to an embodiment of the present invention.

도 1a에 도시한 바와 같이, 본 발명은 먼저 기판(100)상부에 다마신 공정의 콘택을 위한 콘택영역(102)을 형성한다.As shown in FIG. 1A, the present invention first forms a contact region 102 on the substrate 100 for contact of a damascene process.

이 후 형성시킬 트렌치의 하부 깊이만큼 층간절연막(104)을 증착한다. 그리고 그 상부에 식각차단을 위해 질화막으로 식각차단막(106)을 증착한 다음, 다시 그 상부에 선간절연막(108)을 형성한다.Thereafter, the interlayer insulating film 104 is deposited to have a lower depth of the trench to be formed. The etch stop layer 106 is deposited on the upper portion of the etch barrier layer 106 to form an etch barrier layer.

이 후 도 1b와 같이, 공지된 다마신 공정에 의해 트렌치홀(110)을 형성한 다음, 이 트렌치홀(110)의 표면에 티타늄(Ti) 및 질화티타늄(TiN)을 차례로 증착하여 확산방지막(112)을 형성한다. 다음 트렌치홀(110)의 하부에서 실리콘화반응(silicidation)이 진행되도록 RTA(Rapid Thermal Annealing)을 실시한다.Thereafter, as shown in FIG. 1B, a trench hole 110 is formed by a known damascene process, and then titanium (Ti) and titanium nitride (TiN) are sequentially deposited on the surface of the trench hole 110 to prevent diffusion. 112). Next, RTA (Rapid Thermal Annealing) is performed to progress the siliconization reaction (silicidation) in the lower portion of the trench hole 110.

이 후 도 1c와 같이, 확산방지막(112)이 증착된 트렌치홀에 금속을 매립시킨 다음, 그 상부에 화학기계적연마(CMP)로 평탄화시켜 금속매립층(114)을 형성한다.Thereafter, as shown in FIG. 1C, the metal is buried in the trench hole in which the diffusion barrier film 112 is deposited, and then the metal buried layer 114 is formed by planarization with chemical mechanical polishing (CMP) thereon.

이 후 도 1d와 같이, 습식식각 방식에 의해 식각차단막(106)을 기준으로 하여 선간절연막(108)을 제거한다.Thereafter, as shown in FIG. 1D, the interlayer insulating layer 108 is removed based on the etch stop layer 106 by a wet etching method.

이 후 도 1e와 같이, 형성된 트렌치 및 식각차단막(106)의 상부 전면에 절연보조층(116)을 증착시킨 다음, 트렌치와 트렌치 사이가 매립되도록 저유전율 절연막(118)을 형성한다. 이때 저유전율 물질은 SOG(Spin On Glass)계열 물질을 이용한다. 이후 약 400℃의 낮은 온도에서 어닐링(annealing)을 실시하여 본 발명의 일실시예에 따른 다마신공정을 완료한다.Thereafter, as shown in FIG. 1E, an insulating auxiliary layer 116 is deposited on the entire upper surface of the formed trench and etch barrier layer 106, and then a low dielectric constant insulating layer 118 is formed to fill the gap between the trench and the trench. In this case, the low dielectric constant material uses a spin on glass (SOG) -based material. After annealing (annealing) at a low temperature of about 400 ℃ to complete the damascene process according to an embodiment of the present invention.

전술한 바와 같이, 본 발명은 절연물질의 저유전율 특성을 유지시켜 반도체소자를 제작함으로써 RC 성분에 의한 지연을 방지할 수 있으며, 반도체소자의 절연특성에 많은 향상을 기하는 효과가 있다.As described above, the present invention can prevent the delay caused by the RC component by maintaining the low dielectric constant characteristics of the insulating material to prevent the delay caused by the RC component, there is an effect that much improvement in the insulating properties of the semiconductor device.

Claims (6)

반도체소자의 다마신 공정에 있어서,In the damascene process of a semiconductor device, 실리콘기판 상부에 층간절연막을 형성하는 제1단계;A first step of forming an interlayer insulating film on the silicon substrate; 상기 형성된 층간절연막의 상부에 식각차단을 위한 식각차단막을 형성하는 제2단계;Forming an etch barrier layer on the formed interlayer insulating layer to etch off the interlayer insulating layer; 상기 식각차단막의 상부에 선간절연막을 형성하는 제3단계;Forming a line insulating layer on the etch barrier layer; 상기 실리콘기판의 소정영역에 접합될 수 있도록 상기 선간절연막에서부터 트렌치홀을 형성하는 제4단계;Forming a trench hole from the interlayer insulating layer so as to be bonded to a predetermined region of the silicon substrate; 확산을 방지하기 위해 상기 트렌치홀의 내부표면에 확산방지막을 형성하는 제5단계;Forming a diffusion barrier on the inner surface of the trench hole to prevent diffusion; 상기 확산방지막이 형성된 상기 트렌치홀을 금속으로 매립하여 트렌치를 형성하는 제6단계;A sixth step of forming a trench by filling the trench hole in which the diffusion barrier layer is formed of metal; 상기 트렌치 주위에 형성되어 있는 상기 선간절연막을 제거하는 제7단계;A seventh step of removing the interlayer insulating film formed around the trench; 선간절연막이 제거된 상기 식각차단막 및 트렌치 표면에 소정의 절연보조층을 증착하는 제8단계; 및,An eighth step of depositing a predetermined insulating auxiliary layer on the etch barrier layer and the trench surface from which the line insulating layer is removed; And, 상기 절연보조층이 증착된 상기 트렌치 사이의 공간을 저유전율물질로 매립한 후, 상기 저유전율물질의 저유전율 특성이 유지되도록 소정의 온도에서 열처리하는 제9단계를 포함하는 것을 특징으로 하는, 저유전율 절연막이 포함된 다마신공정법.And filling a space between the trenches on which the insulating auxiliary layer is deposited with a low dielectric constant material, and then performing a heat treatment at a predetermined temperature to maintain a low dielectric constant of the low dielectric constant material. A damascene process method comprising a dielectric constant insulating film. 제 1항에 있어서, 상기 제2단계는The method of claim 1, wherein the second step 질화막으로 상기 식각차단막을 형성하는 것을 특징으로 하는, 저유전율 절연막이 포함된 다마신공정법.A damascene process method comprising a low dielectric constant insulating film, characterized in that to form the etch barrier film with a nitride film. 제 1항에 있어서, 상기 제5단계는The method of claim 1, wherein the fifth step 티타늄(Ti) 및 질화티타늄(TiN)을 차례로 증착하여 상기 확산방지막을 형성하는 것을 특징으로 하는, 저유전율 절연막이 포함된 다마신공정법.The damascene process method comprising a low dielectric constant insulating film, characterized in that to form a diffusion barrier by sequentially depositing titanium (Ti) and titanium nitride (TiN). 제 1항 또는 제 3항에 있어서, 상기 제5단계는The method of claim 1 or 3, wherein the fifth step 상기 기판간의 원활한 접속을 위해 상기 트렌치홀의 하부에서 실리콘화반응이 진행되도록, RTA에 의한 열처리 단계를 더 포함하는 것을 특징으로 하는, 저유전율 절연막이 포함된 다마신공정법.And a heat treatment step by RTA so that the siliconization reaction proceeds in the lower portion of the trench hole for smooth connection between the substrates. 제 1항에 있어서, 상기 제9단계는The method of claim 1, wherein the ninth step is 상기 저유전율 물질로 SOG(Spin On Glass)계열의 물질을 사용하는 것을 특징으로 하는, 저유전율 절연막이 포함된 다마신공정법.A damascene process method comprising a low dielectric constant insulating film, characterized in that the use of SOG (Spin On Glass) -based material as the low dielectric constant material. 제 1항에 있어서, 상기 제9단계는The method of claim 1, wherein the ninth step is 약 400℃의 온도에서 어닐링(annealing)하여 열처리하는 것을 특징으로 하는, 저유전율 절연막이 포함된 다마신공정법.A damascene process method comprising a low dielectric constant insulating film, characterized in that the annealing (annealing) at a temperature of about 400 ℃.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008157338A1 (en) * 2007-06-14 2008-12-24 Svtc Technologies, Llc Copper-free semiconductor device interface and methods of fabrication and use thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008157338A1 (en) * 2007-06-14 2008-12-24 Svtc Technologies, Llc Copper-free semiconductor device interface and methods of fabrication and use thereof

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