KR20020006236A - Apparatus and method for correcting image quality of image scaler - Google Patents

Abstract

PURPOSE: An apparatus and method for correcting picture quality of an image scaler are provided to decrease the number of multipliers in the image scaler, to reduce hardware load and to correct image distortion. CONSTITUTION: An apparatus for correcting picture quality of an image scaler includes a counter(121) for generating the first and second select signals for designating and outputting a repetition filter coefficient in case of extension and reduction of an image, a multiplexer(122) for receiving the first and second select signals to output the first and second repetition filter coefficients, and the first data generator(123) for receiving the first repetition filter coefficient and input image data to generate the first filter coefficient value and for multiplying the first filter coefficient value by the input image data to generate the first image data. The apparatus further has the second data generator(124) for receiving the first and second repetition filter coefficients to generate the second filter coefficient value, adding the second and first filter coefficient values to the second filter coefficient value to generate the third filter coefficient value and multiplying the third filter coefficient value by the input image data to generate the second image data, and an image data adder(128) for adding the first image data to the second image data.

Description

{Apparatus and method for correcting image quality of image scaler}

The present invention relates to a device and a method for compensating image quality of an image scaler. In particular, the image quality is filtered to filter image information when an image image is enlarged or reduced using an image scaler to prevent distortion of the enlarged or reduced image. A calibration device and method.

An image scaler is used to enlarge or reduce the video image. When the video image is enlarged or reduced, the image quality is lower than that of the original video image which is enlarged or reduced. An image quality correction device is used to prevent image quality from being deteriorated by being enlarged or reduced by using an image scaler. The image quality correction apparatus of the conventional image scaler will be described with reference to the accompanying drawings.

1 is a block diagram of a conventional image quality correction apparatus. The conventional image quality compensator shown in FIG. 1 shows a configuration in which an image is enlarged or reduced in the horizontal direction, and when the image is enlarged or reduced in the vertical direction, the second registers Rb1, Rb2,. The delay of one line can be configured by replacing with a delay circuit (not shown).

As shown in FIG. 1, the conventional image quality correction apparatus includes a first register part Ra1, Ra2, ..., Ra40, a second register part Rb1, Rb2, ..., Rb40, a plurality of multipliers 1, 2, ..., 40 ) And a plurality of adders 41, 42, ..., 79. The first registers Ra1, Ra2, ..., Ra40 are composed of the first a register Ra1, the second a register Ra2,. The 40th register Ra40 is connected in series, and the second register parts Rb1, Rb2, ..., Rb40 are connected to the first b register Rb1, the second b register Rb2,. The 40th register Rb40 is connected in series.

The plurality of multipliers 1, 2,..., 40 are the first multipliers 1, the second multipliers 2,... , The 40th multiplier 40, each of the first multiplier 1, the second multiplier 2,... The 40th multiplier 40 is connected in parallel between the first register portions Ra1, Ra2, ..., Ra40 and the second register portions Rb1, Rb2, ..., Rb40. The plurality of adders 41, 42, ..., 79 are composed of the first adder 41, the second adder 42, ... And a 39 th adder 79, each of the first adder 41, the second adder 42,... The thirty-ninth adder 79 comprises the first register Rb1, the second register Bb, and the second register Rb1, Rb2, ..., Rb40. And serially connected between each of the 40th registers Rb40.

A plurality of multipliers (1, 2, ..., 40) are connected in parallel between the first register (Ra1, Ra2, ..., Ra40) and the second register (Rb1, Rb2, ..., Rb40) and the second register unit Referring to FIG. 2, the operation of a conventional image quality compensator, in which a plurality of adders 41, 42, ..., 79 are connected in series between Rb1, Rb2, ..., Rb40, is as follows.

When the input image data P0, P1, P2, ..., P39 are sequentially transmitted in synchronization with the predetermined clock, the first image is Ra1 of the first registers Ra1, Ra2, ..., Ra40. The first input image data P0 is transmitted to the first a register Ra1 and the first multiplier 1. The first input image data P0 transmitted to the first multiplier 1 is multiplied by the first filter coefficient data C0 to generate a C0P0 value and stored in the first b register Rb1.

When the second input image data P1 is transmitted to the first a register Ra1 and the first multiplier 1 in synchronization with the second clock, the first input image data P0 transmitted to the first a register Ra1 is first generated. It is sent to the multiplier (2). The first input image data P0 transmitted to the second multiplier 2 is multiplied by the second filter coefficient data C1 to generate a C1P0 value, and transmitted to the first adder 41. The first multiplier 1 receiving the second input image data P1 is multiplied by the first filter coefficient data C0 to generate a C0P1 value, stored in the first b register Rb1, and then transferred to the first adder 41. Is sent.

The first adder 41 receiving the C0P1 value and the C1P0 value adds the received C0P1 value and the C1P0 value to generate a C0P1 + C1P0 value and transmits the value to the second b register Rb2. When the third input image data P2 is transmitted by repeating the above-described process, the second adder 42 generates the C0P2 + C1P1 + C2P0 value, and when the fourth input image data P3 is transmitted, the third adder 43 uses the C0P3 + C1P2 + C2P1 + C3P0 value. Occurs. When the fifth input image data P4 is transmitted, the fourth adder 44 generates and outputs the values C0P4 + C1P3 + C2P2 + C3P1 + C4P0, and at the time point where the 40th input image data P39 is transmitted, the 39th adder 79 uses C0P39 + C2P38 +. The value + C37P2 + C38P1 + C39P0 is generated and output.

C0P39 + C2P38 +, which is generated and output from the 39th adder 79; Like the + C37P2 + C38P1 + C39P0 value, the image quality of the image can be prevented from being distorted even when the image is greatly enlarged or reduced by interpolation with 40 tabs when the image is reduced or enlarged. 40 multipliers are required in proportion to the number of taps when interpolating to 40 taps when reducing or enlarging an image. When the multiplier is provided in proportion to the number of taps in order to correct the distortion of the image due to the enlargement or reduction while enlarging or reducing the image, the chip size of the image scaler is increased and the multiplication operation is increased. There is a problem that the burden of hardware) is increased.

The present invention provides an apparatus and method for compensating image quality of an image scaler which can reduce hardware burden by reducing the number of multipliers and multiplication operations using repeated filter coefficients when an image is enlarged / reduced.

It is another object of the present invention to provide an image scaler and an image quality correcting apparatus capable of enlarging or reducing an image without distortion of an image when zooming in / out for any magnification that is not repeated, not just an integer multiple.

It is still another object of the present invention to provide an apparatus and method for compensating image quality of an image scaler capable of minimizing the chip size of the image scaler by minimizing the number of multipliers performing multiplication in the image scaler.

1 is a block diagram of a conventional image quality correction apparatus;

FIG. 2 is a table showing a logical operation result of the image quality correction device shown in FIG.

3 is a block diagram of an image scaler to which an image quality correction apparatus according to the present invention is applied;

4 is a block diagram of an image quality correction device shown in FIG. 3;

5A through 5E are timing diagrams of the image quality correction apparatus shown in FIG. 4;

6A and 6B are tables showing a logic operation result of the image quality correction apparatus according to the present invention;

7 is a flowchart illustrating a quality correction method according to the present invention;

8A to 8C are tables showing coefficient calculation data of the image quality correction apparatus according to the present invention.

The image quality correction apparatus of the image scaler of the present invention receives a counter control signal, generates a first selection signal for designating and outputting a repetition filter coefficient when the image is enlarged / reduced, and continuously outputs the first selection signal. A counter unit which generates a second selection signal and continuously outputs the signal after a predetermined time delay; A multiplexer unit receiving the first selection signal and the second selection signal output from the counter unit and outputting a first iteration filter coefficient and a second iteration filter coefficient according to the received first selection signal and the second selection signal; Receives the first repeating filter coefficient and the input image data and sequentially feeds back the first repeating filter coefficient to the received first repeating filter coefficient to generate a first filter coefficient value, and generates the first filter coefficient value and the received first filter coefficient value. A first data generator for multiplying input image data and outputting first image data; The first filter coefficient value and the second repeat filter coefficient are continuously received and added to generate a second filter coefficient value, and the second filter coefficient value is fed back to receive the first filter coefficient value and is selectively received. A third filter coefficient value is generated by selectively adding the second filter coefficient value and the first filter coefficient value to the filter coefficient value, and generating the second image data by multiplying the generated third filter coefficient value and the received image data. A second data generator; And an image data adder for adding the first image data output from the first data generator and the second image data output from the second data generator.

The counter unit includes: a first FC register configured to continuously receive and output a first original image size value at a predetermined period when the image is enlarged; A second FC register configured to receive and store the fed back first original image size value; The first original image size value received from the first FC register is received and outputted, and the first original image size value fed back to the second FC register is added to the first original image size value received to add the second original image size value. FC adder that generates and outputs continuously; The first original image size value and the second original image size value received from the FC adder are sequentially received, and the first original image size value and the second original image size value reach the enlarged image size value by comparing with the enlarged image size value. A comparator for generating and outputting a reset signal when the reset signal is generated; And generating and outputting a first selection signal for receiving a reset signal and repeatedly outputting a repeating filter coefficient, and generating a second selection signal after delaying a predetermined time after the first selection signal is output and continuously outputting the second selection signal. And an address counter.

The multiplexer unit may include: a first FC multiplexer configured to receive the first repeating filter coefficient and receive the first selection signal output from the counter unit to continuously output the first repeating filter coefficient; A second FC multiplexer which receives the second repeating filter coefficient and receives the second selection signal output from the counter unit and continuously outputs the second repeating filter coefficient; A third FC multiplexer which receives the third repeating filter coefficient and receives the third selection signal output from the counter unit and continuously outputs the third repeating filter coefficient; And a fourth FC multiplexer which receives the fourth repeated filter coefficient and receives the fourth selected signal output from the counter unit, and continuously outputs the fourth repeated filter coefficient value.

A first Ra register configured to receive and output a first iterative filter coefficient; a first data generator receives a first iterative filter coefficient and a value of '0', receives a first external selection signal, and receives a first external selection signal according to a first external selection signal; A first multiplexer for selecting and outputting a value and a first iterative filter coefficient sequentially received; A first adder that receives the first iteration filter coefficient output from the first Ra register, receives and adds a value of '0' selected from the first multiplexer and the first iterative filter coefficient, and generates and outputs the first filter coefficient value. A second Ra register receiving the first iterative filter coefficient and the first filter coefficient value output from the first adder, transmitting the received first iterative filter coefficient to the first multiplexer, and outputting the received first filter coefficient value; A third Ra register for receiving and outputting image data; receiving a first repetitive filter coefficient and a first filter coefficient value output from the second Ra register, receiving input image data output from the third Ra register, and multiplying the first filter coefficient value A first multiplier for generating and outputting first image data; and a fourth Ra register for receiving and outputting first image data output from the first multiplier; do.

The second data generator includes: a first Rb register configured to receive and output a first iterative filter coefficient;

A second Rb register for receiving and outputting a second iterative filter coefficient; The first filter coefficient value and the second filter coefficient value output from the second Ra register are sequentially received, and when the second external selection signal is received, the first filter coefficient value and the second filter coefficient value according to the received second external selection signal. A second multiplexer for selecting and outputting the selected; Receives and adds a first repeating filter coefficient output from the first Rb register and a second repeating filter coefficient output from the second Rb register to generate and output a second filter coefficient value, and then selects and outputs the second filter coefficient from the second multiplexer. A second adder receiving the value and the second filter coefficient value, adding the second filter coefficient value to generate and output a third filter coefficient value; A third Rb register that receives the second filter coefficient value and the third filter coefficient value output from the second adder, transmits the received second filter coefficient value to the second multiplexer, and receives and outputs the received third filter coefficient value; ; A fourth Rb register for receiving and outputting input image data; A second multiplier configured to receive a third filter coefficient value output from the third Rb register, receive and multiply input image data output from the fourth Rb register, and generate and output second image data; And a fifth Rb register configured to receive and output second image data output from the second multiplier.

The image quality correction method of the image scaler of the present invention comprises the steps of selecting to enlarge or reduce the image to M / N magnification; Initializing the total pixel sum, the total pixel count value, the repetition pixel count, and the step increment value to “0” when the enlargement or reduction of the image is selected in the step of enlarging or reducing the image; In the step of initializing the total pixel sum, the total pixel count value, the repeat pixel count and the step increment value to "0", the total pixel sum, the total pixel count value, the repeat pixel count and the step increment value are initialized to "0". Checking whether magnification is selected; If it is determined that the image enlargement is selected in the step of confirming whether the image enlargement is selected, adding N to the total pixel sum and increasing the total pixel count value and the repetition pixel coefficient by one step; In addition to adding the N value to the total pixel sum and increasing the total pixel count value and the repeating pixel coefficient by one step, adding the N value to the total pixel sum and increasing the total pixel count value and the repeating pixel coefficient by one step, Checking whether the pixel sum is greater than or equal to the M value; Checking whether the total pixel count value is greater than or equal to the N value if the total pixel sum is greater than or equal to the M value in the checking whether the total pixel sum is greater than or equal to the M value; In the step of checking whether the total pixel count value is greater than or equal to the N value, the total pixel count value is greater than or equal to the N value.

In the step of confirming that the image enlargement is selected, if the image enlargement is not selected, the image reduction is selected and the M value is added to the total pixel sum and the total pixel count value and the repeating pixel coefficient are increased by one step. ; In addition to adding the M value to the total pixel sum and increasing the total pixel count value and the repeating pixel coefficient by one step, adding the M value to the total pixel sum and increasing the total pixel count value and the repeating pixel coefficient by one step, Checking whether the pixel sum is greater than or equal to an N value; Checking whether the total pixel count value is greater than or equal to the M value if the total pixel sum is greater than or equal to the N value in the checking whether the total pixel sum is greater than or equal to the N value; In the step of checking whether the total pixel count value is greater than or equal to the M value, if the total pixel count value is greater than or equal to the M value, the method may include correcting an image by using a repeating pixel coefficient.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

3 is a block diagram of an image scaler to which the image quality correction apparatus according to the present invention is applied, and FIG. 4 is a block diagram of the image quality correction apparatus shown in FIG. As shown in the drawing, the counter control signal C-control is received to generate a first selection signal sela for designating and outputting the repetition filter coefficients C0, C1, ... C21 when the image is enlarged or reduced. A counter unit 121 for generating a second selection signal selb and outputting it continuously after a predetermined time delay after the first selection signal sela is output, and a first output from the counter unit 121. Receiving the selection signal sela and the second selection signal selb, and according to the received first selection signal sela and the second selection signal selb, the first iteration filter coefficients C0, C1,... The multiplexer unit 122 outputs the second iteration filter coefficients C0, C1, ... C21, the first iteration filter coefficients C0, C1, ... C9, and the input image data, and receives the first iteration filter coefficients C0, C0, C21. The first filter coefficient value HC0 is generated by adding the first iterative filter coefficients C0, C1, ... C9 received by sequentially feeding back C1, ... C9, and the generated first filter coefficient value HC0 and Received A first data generator 123 for multiplying the output image data to output the first image data, a first iteration filter coefficient C0, C1, ... C9 and a second iteration filter coefficient C0, C1, ... C21 Receive continuously and add a second filter coefficient value, and feed back the second filter coefficient value to receive first filter coefficient value HC0 and selectively receive the second filter coefficient value to the second filter coefficient value. A third filter coefficient value HC1 is generated by selectively adding the value and the first filter coefficient value HC0, and second image data is generated by multiplying the generated third filter coefficient value HC1 and the received image data. An image data adder for adding and outputting the second data generator 124, the first image data output from the first data generator 123, and the second image data output from the second data generator 124. It consists of 128.

Hereinafter, the configuration and operation of the present invention in more detail as follows.

The image quality correction apparatus will be described first after the image quality correction apparatus and the image quality correction apparatus of the image scaler of the present invention. The overall configuration of the image scaler to which the image quality correction apparatus of the present invention is applied is shown in FIG. 3. As shown in FIG. 3, the image scaler includes a first vertical filter 110, a second horizontal filter 120, a line memory unit 130, a second vertical filter 140, and a second horizontal filter 150. do. In order to enlarge the image image, the enlarged input image data is input to the line memory unit 130 and then enlarged and corrected through the second vertical filter 110 and the second horizontal filter 120, and then the second horizontal filter 120 is enlarged. Through the enlarged output image data is output. In order to reduce the video image, the reduced input image data is input to the first vertical filter 110, the first horizontal filter 120, and the line memory unit 130, reduced, and then corrected to reduce the output image through the line memory 130. The image data is configured to be output.

The first vertical filter 110 and the first vertical filter 110, the first horizontal filter 120, the second vertical filter 140, and the second horizontal filter 150 are configured to enlarge or reduce an image. The two vertical filters 140 are configured identically to each other, and the first horizontal filter 120 and the second horizontal filter 150 are configured identically to each other. The configuration difference between the first and second vertical filters 110 and 140 and the first and second vertical filters 120 and 150 is configured by a latch (not shown) to latch the input image data. That is, the first and second vertical filters 110 and 140 require a line memory (not shown) to latch the input image data, and the first and second vertical filters 120 and 150 use the pixel data. Since a register (not shown) for latching is used, the first horizontal filter 120 is used to describe the detailed configuration of the present invention.

The first horizontal filter 120 is illustrated in FIG. 4. As shown in FIG. 4, the first horizontal filter 120 includes a counter 121, a multiplexer 122, a first data generator 123, a second data generator 124, and an image data adder 128. It is composed. The counter unit 121 receives a counter control signal C-control from a controller (not shown) that generally controls the image scaler. The counter unit 121 receiving the counter control signal C-control generates a first selection signal sela for specifying and outputting the repetitive filter coefficients C0, C1, ... C21 when the image is enlarged / reduced. After outputting continuously and delaying the predetermined time after the first selection signal sela is output, the second selection signal selb is generated and continuously output.

The multiplexer 122 receives the first selection signal sela and the second selection signal selb output from the counter 121. The multiplexer unit 122 that receives the first selection signal sela and the second selection signal selb receives the first iteration filter coefficient C0 according to the received first selection signal sela and the second selection signal selb. , C1, ... C9 and second iterative filter coefficients C0, C1, ... C21 are output. The first iteration filter coefficients (C0, C1, ... C9) and the second iteration filter coefficients (C0, C1, ... C21) are calculated and stored in advance as coefficients of a filter that is repeated when the image is enlarged or reduced. It is supplied to the multiplexer part 122 by control.

The first data filter 123 receives the first iterative filter coefficients C0, C1, ... C9 selected from the multiplexer unit 122 and sequentially output. The first data generator 123 receives the first iterative filter coefficients C0, C1, ... C9, and the input image data, and sequentially feeds back the first iterative filter coefficients C0, C1, ... C9. The first filter coefficient value HC0 is generated by adding the first iterative filter coefficients C0, C1, ... C9, and the first image data is multiplied by the generated first filter coefficient value HC0 and the received input image data. Will print

The first iterative filter coefficients C0, C1, ... C9 are sequentially output from the multiplexer unit 122, and the first iterative filter coefficients C0, C1, ... C9 are output. The second iterative filter coefficients C0, C1, ... C21 are continuously output after a predetermined time delay by the time C0, C1, ... C9 is output once. The second iterative filter coefficients C0, C1, ... C21 repeatedly outputted from the multiplexer unit 122 are received by the second data generator 124. The second data generator 124 receiving the second iterative filter coefficients C0, C1, ... C21 simultaneously receives the second iterative filter coefficients C0, C1, ... C9 and receives the second iterative filter coefficients C0, C1, ... C21. C1, ... C21) are continuously received.

When the first iteration filter coefficients C0, C1, ... C9 and the second iteration filter coefficients C0, C1, ... C21 are received, the second data generation unit 124 receives the first iteration filter coefficients C0, C1, ... C9. C9) and the first iterative filter coefficients C0, C1, ... C9 are added to generate a second filter coefficient value. The second data generator 124 generates a second filter coefficient value and feeds back the second filter coefficient value to selectively receive the first filter coefficient value HC0. The second data generator 124 selectively receiving the first filter coefficient value HC0 and the second filter coefficient value HC0 by feeding back the second filter coefficient value has a second filter coefficient value or a first filter coefficient value HC0. Next, the third filter coefficient value HC1 is generated to add the second filter data, and second image data is generated by outputting the second filter coefficient value HC1 by multiplying the received image data.

The second image data output from the second data generator and the first image data output from the first data generator 123 are received by the image data adder 128 and added to the image data register 129. . The first iterative filter coefficient in the process of receiving and adding the second image data output from the second data generator 124 and the first image data output from the first data generator 123. (C0, C1, ... C9) and the second iterative filter coefficients (C0, C1, ... C21) are used to correct the image to be enlarged when the image is enlarged, and the first iterative filter coefficient (C0, C1, ... to be repeated at the time of reduction The reduced image can be corrected by outputting the first filter coefficient "C0" in C9) and the second iterative filter coefficients C0, C1, ... C21 and not using the rest.

Referring to the configuration of the first horizontal filter 120 of the present invention in more detail as follows. First, the counter unit 121 includes a first FC register FCReg1, a second FC register FCReg2, an FC adder 121a, a comparator 121b, and an address counter unit 121c. When the image is enlarged by a predetermined magnification, the first FC register FCReg1 continuously receives and outputs the first original image size value X-value at a predetermined period. The first original image size value X-value output from the first FC register FCReg1 is received by the FC adder 121a and output. When the first original original image size value (X-value) output from the FC adder 121a is output, it is received by the comparator 121b. The comparator 121b receives and compares the first original image size value X-value and the enlarged image size value Y-value, thereby comparing the first original image size value X-value to the enlarged image size value Y-value. value), a reset signal is generated. If not, a reset signal is not generated.

If the reset signal is not received from the comparator 121b, the address counter 121c sequentially specifies the first iteration filter coefficients C0, C1, ... C9 and the second iteration filter coefficients C0, C1, ... C21. A first selection signal sela and a second selection signal selb are continuously generated and output. The FC adder 121a is configured to generate a reset signal for periodically repeating and outputting the first iteration filter coefficients C0, C1, ... C9 and the second iteration filter coefficients C0, C1, ... C21. The original image size value (X-value) is fed back. The fed back first original image size value X-value is stored in the second FC register FCReg2 and received by the FC adder 121a.

In addition to receiving the first original image size value (X-value) fed back, the FC adder 121a receives and receives the first original image size value (X-value) continuously output from the first FC register FCReg1. A second original image size value (X-value + X-value) is generated by adding the first original image size value (X-value) to be generated and output. The second original image size value (X-value + X-value) generated and output from the FC adder 121a is received by the comparator 121b and compared with the enlarged image size value (Y-value) to obtain the second original image. When the size value (X-value + X-value) reaches the enlarged image size value (Y-value), a reset signal is generated and output.

When the reset signal is output from the comparator 121b, the address counter 121 repeats the first and second iterative filter coefficients C0, C1, ... C9 (C0, C1, ... C21) based on the received reset signal. After generating the first selection signal sela for continuously outputting and outputting the first selection signal sela, the second selection signal selb is generated continuously after being delayed for a predetermined time. In order to output the first selection signal sela and the second selection signal selb after a predetermined time delay, the address counter unit 121c receives the counter control signal C-control from the controller and receives the first selection signal sela. ) Is output after delaying the second selection signal selb for a predetermined time.

When the image is reduced differently from the above-described image enlargement, the first reduced image size value X-value is received by the first FC register FCReg1, and the FC adder 121a is output from the first FC register FCReg1. Receives and outputs one reduced image size value (X-value) and feeds back the first reduced image size value (X-value) to add the received first reduced image size value (X-value) to the second reduction. The image size value (X-value + X-value) is generated continuously and printed. The second reduced image size value (X-value + X-value) output from the FC adder 121a is received by the comparator 121b, and the comparator 121b receives the second reduced image size value (X-value + X). -value) is configured to receive the original image size value (X-value + X-value) in order to compare it with the original image size value (X-value + X-value). Will be implemented.

The first and second repetition filter coefficients C0, C1, ... C9 are received by receiving the first selection signal sela and the second selection signal selb output from the address counter 121c of the counter 121; A multiplexer unit 122 is provided to continuously output C0, C1, ... C21. The multiplexer unit 122 includes a first FC multiplexer FCMUX1 and a second FC multiplexer FCMUX2. The first FC multiplexer FCMUX1 receives the pre-stored first iterative filter coefficients C0, C1,... C9 and receives the first selection signal sela output from the address counter 121c of the counter 121. Receive

The first FC multiplexer FCMUX1 receiving the first iteration filter coefficients C0, C1,... C9 and the first selection signal sela may receive a first iteration filter coefficient C0, in accordance with the received first selection signal sela. In C1, ... C9), filter coefficients "C0, C1, ... C9" are sequentially selected and output one by one. The first FC multiplexer FCMUX1 sequentially and repeatedly outputs the filter coefficients “C0, C1, ... C9” one by one, and the second FC multiplexer FCMUX2 performs the same operation as the first FC multiplexer FCMUX1 to perform the second selection signal ( When selb) is received, the filter coefficients C0, C1, C21 are selected from the second iterative filter coefficients C0, C1, C21, and output one by one. Here, the delay times of the first and second iterative filter coefficients C0, C1, ... C9 (C0, C1, ... C21) output from the first FC multiplexer FCMUX1 and the second FC multiplexer FCMUX2, respectively, are repeated filters. After the coefficients "C0, C1, ... C21" are all sequentially output one time, the second iterative filter coefficients C0, C1, ... C21 are output from the second FC multiplexer FCMUX2.

When the image is reduced or enlarged, the number of interpolation taps is increased to more accurately correct the image. To this end, the multiplexer unit 122 further includes a third FC multiplexer FCMUX3 and a fourth FC multiplexer FCMUX4 in addition to the first FC multiplexer FCMUX1 and the second FC multiplexer FCMUX2. In order to further include the third FC multiplexer FCMUX3 and the fourth FC multiplexer FCMUX4 in the multiplexer unit 122, the address counter 121c generates a third select signal selc and a fourth select signal seld. Will print.

The third selection signal selc and the fourth selection signal seld output from the address counter 121c are received by the third FC multiplexer FCMUX3 and the fourth FC multiplexer FCMUX4, respectively. The third FC multiplexer FCMUX3 receiving the third selection signal selc continuously performs a third iterative filter after one output period of the filter coefficients "C0, C1, ... C21" repeated than the second FC multiplexer FCMUX2 is delayed. The coefficients C0, C1, ... C31 are output continuously. The fourth FC multiplexer FCMUX4 receiving the fourth selection signal seld is continuously delayed by the time that all of the filter coefficients “C0, C1,… C21” which are repeated than the third FC multiplexer FCMUX3 are sequentially output one time. The fourth iterative filter coefficients C0, C1, ... C31 are output continuously.

First to fourth iterative filter coefficients C0 and C1 received by the first FC multiplexer FCMUX1, the second FC multiplexer FCMUX2, the third FC multiplexer FCMUX3, and the fourth FC multiplexer FCMUX4 of the multiplexer unit 122, respectively. ... C31) has the same value when the magnification factor is an integer multiple, and an unequal value is used when the magnification factor is not an integer multiple. For example, if the repeating filter coefficient is repeated as "C0, C1, ... C9" when the zoom factor is an integer multiple, the same number of "C0, C1, ... C9" is repeated and outputted. The number of repeated filter coefficients " C0, C1, ... C9 " may be eight and may be less than nine to nine. Even if the number of repeated filter coefficients " C0, C1, ... C9 "

The first data filter 123 receives the first iterative filter coefficients C0, C1, ... C9 output from the first FC multiplexer FCMUX1 of the multiplexer 122. The first data generator 123 receiving the first iterative filter coefficients C0, C1, ... C9 may include a first Ra register Ra1, a second Ra register Ra2, a third Ra register Ra3, and a fourth Ra register. Ra4), a first multiplexer MUX1, a first adder 123a, and a first multiplier 123b.

The first iterative filter coefficients C0, C1, ..., C9 are received by the first Ra register Ra1 of the first data generator 123. The first Ra register Ra1 receiving the first iterative filter coefficients C0, C1, ... C9 sequentially outputs the first iterative filter coefficients C0, C1, ... C9. The filter coefficient "C0" first input from the first iterative filter coefficients C0, C1, ... C9 output from the first Ra register Ra1 is passed through the first adder 123a and stored in the second Ra register Ra2. . The first filter coefficient "C0" stored in the second Ra register Ra2 is fed back to the first multiplexer MUX1 and to the first multiplier 123b. The first filter coefficient "C0" transmitted to the first multiplier 123b is multiplied by the input image data input through the third Ra register Ra3 and then output through the fourth Ra register Ra4.

The first filter coefficient "C0" fed back to the first multiplexer MUX1 is selected and outputted alternately with the value "0" received by the first multiplexer MUX1. After that, the filter coefficients "C0" and "0" are added by the filter coefficients "C1, C2, ... C9" and the first adder 123a which are output after "C0" and the first filter coefficient value HC0. Will generate the output. The first filter coefficient value HC0 generated by the first adder 123a is fed back to the first multiplexer MUX1 and received by the first adder 123a to receive the first iterative filter coefficients C0, C1, ... C9. And are generated. For convenience of description, the first filter coefficient value HC0 to which the first iterative filter coefficients C0, C1, ... C9 are added is also collectively referred to as the first filter coefficient value HC0.

The first filter coefficient value HC0 generated and output from the first adder 123a is temporarily suited to the second Ra register Ra2 and then transmitted to the first multiplier 123b. The first multiplier 123b receiving the first filter coefficient value HC0 multiplies the input image data received from the third Ra register Ra3 and the received first filter coefficient value HC0 to generate first image data. Will print. The first image data output from the first multiplier 123b is sequentially stored in the fourth Ra register Ra4 and then transmitted to the image data adder 128. The third Ra register Ra3, which receives the input image data and transmits it to the first multiplier 123b, is configured as a line memory (not shown).

A synchronous operation of enlarging or reducing an image by adding first repetitive filter coefficients C0, C1, ... C9 and input image data sequentially input from the first data generator 123 will be described with reference to FIG. 5A. Is as follows. As shown in FIG. 5A, the first iterative filter coefficients C0, C1, ... C9 output from the first Ra register Ra1 are output to the selection of the first selection signal waveform "sela" synchronized with the synchronization signal waveform "rack". . In the first selection signal waveform "sela", "0,1,2, ..., 9" means the address represented by the decimal number and the first iterative filter coefficient C0, which is output by the selection of the first selection signal waveform "sela". C1, ... C9) are output like the waveform "cina", and the first multiplexer MUX1 is synchronized with the waveform "mca" representing the first external selection signal, "0" and "C0" or the first filter coefficient value. (HC0) is alternately selected and output.

The first filter coefficient value HC0, which is added by the first adder 123a and output and fed back to the first multiplexer MUX1, represents the first external selection signal and is formed by the waveform "mca", such as the waveform "hca". The filter coefficient value HC0 and the value " 0 " are alternately selected and output. It is added by the first adder 123a and outputted, so that the first filter coefficient value HC0 is outputted as a waveform "hc0". That is, the first filter coefficient value HC0 is added and output as "C0, C0 + C1, C0 + C1 + C2, C0 + C1 + C2 + C3 ...". The input image data received by the third Ra register Ra3 is composed of "A0, A1, ...", and each input image data "A0, A1, ..." is received in synchronization with the waveform "pixin", and the third Ra register ( Ra3) outputs the input image data in synchronization with the waveform "pixck".

The input image data output from the third Ra register Ra3 in synchronization with the waveform "pixck" is generated and output like the waveform "md0". The input image data output as the waveform "md0" is multiplied by the first filter coefficient value HC0 in the first multiplier 123b, and then sequentially as "R0, R1" as in the waveform "rdata" representing the first image data. ,… "Will be printed. The output "R0, R1, ..." is transmitted to the fourth Ra register Ra4 and then to the image data adder 128.

The image data adder 128 receives second image data in addition to the first image data. The second image data is generated by the second data generator 124, and the second data generator 124 generates the first iterative filter coefficient C0 through the first Rb register Rb1 to generate the second image data. The second Rb register Rb2 receives and outputs the second iteration filter coefficients C0, C1, ... C21. The second adder 124a receives the first and second repetitive filter coefficients C0, C1, ... C9 (C0, C1, ... C21) output from the first and second Rb registers Rb1 and Rb2, respectively. Receive and add a second filter coefficient value to output.

The second filter coefficient value output from the second adder 124a is transmitted to the second multiplexer MUX2. The second multiplexer MUX2 receiving the second filter coefficient value receives the first filter coefficient value HCO output from the second Ra register Ra2 and receives the second filter coefficient value and the first filter coefficient value HCO. In response to the second external selection signal mcb, the signal is repeatedly outputted alternately. The second filter coefficient value and the first filter coefficient value HCO, which are alternately selected and output from the second multiplexer MUX2, are received by the second adder 124a and added with the second filter coefficient value to add a third filter coefficient value. Generate and output (HC1). The third filter coefficient value HC1 output from the second adder 124a is received by the third Rb register Rb3 and transmitted to the second multiplier 124b.

The second multiplier 124b receiving the third filter coefficient value HC1 receives the input image data received through the fourth Rb register Rb4 and multiplies the third filter coefficient value HC1 to multiply the second image data. Generate and print. The fourth Rb register Rb4 is used to enlarge / reduce the image in the horizontal direction and is configured as a line memory when enlarged / reduced in the vertical direction of the image. The second image data output from the second multiplier 124b is transferred to the fifth Rb register Rb5 and then transferred to the image data adder 128, added with the first image data, and then transferred to the image data register 129. do. The input and output waveforms of the second data generator 124 for generating the second image data are shown in FIG. 5B, and the waveforms "selb, rbck, cinb, csb, mcb, hcb, hc1, pixck, md1, pdata " performs the same operation as the waveforms " rack, sela, cina, mca, hca, hc0, pixin, pixck, md0, rdata "

When the third FC multiplexer FCMUX3 and the fourth FC multiplexer FCMUX4 are provided in the multiplexer unit 122 to increase the number of interpolation tabs when the image is enlarged or reduced, from the third FC multiplexer FCMUX3 and the fourth FC multiplexer FCMUX4. In order to receive and process the third iterative filter coefficients C0, C1, ... C31 and the fourth iterative filter coefficients C0, C1, ... C39, respectively, the third data generator 125 and the fourth data generator 126 and the fifth data generating unit 127 are provided.

The third data generator 125 first receives and outputs the second repetition filter coefficients C0, C1, ... C21 through the first Rc register Rc1, and the third repetition through the second Rc register Rc2. The filter coefficients C0, C1, ... C31 are received and output. The second and third iterative filter coefficients C0, C1, ... C21 (C0, C1, ... C31) output from the first Rc register Rc1 and the second Rc register Rc2, respectively, are received by the third adder 125a. It receives and adds to generate a fourth filter coefficient value and outputs it.

The fourth filter coefficient value output from the third adder 125a is transmitted to the third multiplexer MUX3. The third multiplexer MUX3 receiving the fourth filter coefficient value receives the second filter coefficient value output from the second Rb register Rb2 and receives the second filter coefficient value and the fourth filter coefficient value as the third external selection signal ( mcc) will be outputted alternately. The fourth filter coefficient value and the second filter coefficient value, which are alternately selected and output from the third multiplexer MUX3, are received by the third adder 125a and added with the fourth filter coefficient value to add the fifth filter coefficient value HC2. Generate and print The fifth filter coefficient value HC2 output from the third adder 125a is received by the third Rc register Rc3 and transmitted to the third multiplier 125b.

The third multiplier 125b receiving the fifth filter coefficient value HC2 receives the input image data received through the fourth Rc register Rc4 and multiplies the fifth filter coefficient value HC2 to multiply the third image data. Generate and print. The fourth Rc register Rc4 is used to enlarge / reduce the image in the horizontal direction and is configured as a line memory when enlarged / reduced in the vertical direction of the image. The third image data output from the third multiplier 125b is transmitted to the fifth Rc register Rc5 and then transferred to the image data adder 128 and added with the first and second image data, and then the image data register 129. Will be sent to. The input and output waveforms of the third data generator 125 generating third image data are shown in FIG. 5C, and the waveforms "selc, rcck, cinc, csc, mcc, hcc, hc2, pixck, md2, qdata "performs the same operation as the waveforms" selb, rbck, cinb, csb, mcb, hcb, hc1, pixck, md1, pdata "shown in 5b, so a detailed description thereof will be omitted.

The fourth data generator 126 generating the fourth image data receives and outputs the third iterative filter coefficients C0, C1, ... C31 through the first Rd register Rd1, and the second Rd register Rd2. The fourth iterative filter coefficients C0, C1, ... C39 are received and output through the third and fourth iterative filter coefficients C0, C1 respectively output from the first Rd register Rd1 and the second Rd register Rd2. ,... C39 is received by the fourth adder 126a, added to generate and output a sixth filter coefficient value.

The sixth filter coefficient value output from the fourth adder 126a is transmitted to the fourth multiplexer MUX4. The fourth multiplexer MUX4 that has received the sixth filter coefficient value receives the fourth filter coefficient value output from the third Rc register Rc3 and receives the fourth filter coefficient value and the sixth filter coefficient value as the fourth external selection signal ( According to mcd), the output will be repeated alternately. The sixth filter coefficient value and the fourth filter coefficient value, which are alternately selected and output from the fourth multiplexer MUX4, are received by the fourth adder 126a and added with the sixth filter coefficient value to add the seventh filter coefficient value HC3. Generate and print The seventh filter coefficient value HC3 output from the fourth adder 126a is received by the third Rd register Rd3 and transmitted to the fourth multiplier 126b.

The fourth multiplier 126b receiving the seventh filter coefficient value HC3 receives the input image data received through the fourth Rd register Rd4 and multiplies the seventh filter coefficient value HC3 to multiply the fourth image data. Generate and print. The fourth Rd register Rd4 is used to enlarge / reduce the image in the horizontal direction and is configured as a line memory to enlarge / reduce the image in the vertical direction of the image. The fourth image data output from the fourth multiplier 126b is transmitted to the fifth Rd register Rd5 and then transferred to the image data adder 128 and added with the first and second image data, and then the image data register 129. Will be sent to. The input / output waveforms of the fourth data generator 126 for generating the fourth image data are shown in FIG. 5D, and the waveforms "seld, rdck, cind, csd, mcd, hcd, hc3, pixck, md3, sdata "performs the same operation as the waveforms" selc, rcck, cinc, csc, mcc, hcc, hc2, pixck, md2, qdata "shown in 5c, and thus the detailed description thereof will be omitted.

The fifth data generator 127 receives and outputs the fourth iterative filter coefficients C0, C1, ..., C39 through the first Re register Re1. The fourth iterative filter coefficients C0, C1, ..., C39 output from the first Re register Re1 are received by the fifth adder 126a, added, and the eighth filter coefficient value HC4 is generated and output. The eighth filter coefficient value HC4 output from the fifth adder 127a is transmitted to the fifth multiplexer MUX5. The fifth multiplexer MUX5 receiving the eighth filter coefficient value HC4 receives the sixth filter coefficient value output from the third Rd register Rd3 and receives the sixth filter coefficient value HC8 and the eighth filter coefficient value HC4. The output is alternately repeated according to the fifth external selection signal mce.

Fourth repeated filter coefficients C0 and C1 that are repeatedly received by the fifth adder 127a by receiving the sixth filter coefficient value and the eighth filter coefficient value HC4 alternately selected and output from the fifth multiplexer MUX5. , ... is added to C39 to generate and output the eighth filter coefficient value HC4. The eighth filter coefficient value HC4 output from the fifth adder 127a is received by the third Re register Re3 and transmitted to the fifth multiplier 127b. The fifth multiplier 127b receiving the eighth filter coefficient value HC4 receives the input image data received through the fourth Re register Re4 and multiplies the eighth filter coefficient value HC4 to multiply the fifth image data. Generate and print.

The fourth Re register Re4 is used to enlarge / reduce the image in the horizontal direction and is configured as a line memory to enlarge / reduce the image in the vertical direction of the image. The fifth image data output from the fifth multiplier 127b is transferred to the fifth Re register Re5 and then transferred to the image data adder 128 and added with the first and second image data, and then the image data register 129. Will be sent to. The input and output waveforms of the fifth data generator 127 for generating fifth image data are shown in FIG. 5E, and the waveforms "sele, reck, cse, mce, hce, hc4, pixck, md4, tdata" shown in FIG. 5E. The same operation as the waveforms "seld, rdck, cind, csd, mcd, hcd, hc3, pixck, md3, sdata" shown in 5d will be omitted.

As described above, the first through fifth outputs to the first data generator 123, the second data generator 124, the third data generator 125, the fourth data generator 126, and the fifth data generator 127, respectively. The calculation results of the first, third, fifth, seventh and eighth essential coefficient values HC0, HC1, HC2, HC3 and HC4 to generate five image data are shown in FIGS. 6A and 6B. It is a result of assuming that the first filter coefficient value HC0 is SC0 in the logical operation results shown in FIGS. 6A and 6B, and the first, third, fifth, seventh and eighth essential coefficient values HC0 (HC1) and HC2 are calculated. After multiplying the image data by the shifted first, third, fifth, seventh and eighth essential coefficient values (HC0) (HC1) (HC2) (HC3) (HC4) by shifting and outputting (HC3) (HC4) By adding with the image data adder 128, many multiplication operations can be eliminated when the image is enlarged or reduced.

A method of correcting image quality by calculating a repetitive filter coefficient value to reduce multiplication by configuring the number of multipliers to a minimum when enlarging or reducing an image will be described with reference to the accompanying drawings.

7 is a road illustrating a flowchart of a method for correcting image quality according to the present invention. First, an enlargement or reduction of an image at an M / N magnification is performed (S110). In step S110 of selecting an enlargement or reduction of an image, when the enlargement or reduction of the image is selected, the total pixel sum, total pixel count value (tc), repetition pixel count (jc), and step increment value (ac) are selected. Each step S120 is initialized. In the step S120, the total pixel sum sum and the total pixel count value tc, the repeat pixel count jc and the step increment value ac are initialized to "0", respectively. When the count value tc, the repetition pixel count jc and the step increment value ac are respectively initialized to "0", a step S130 is performed to confirm whether image magnification is selected.

In the step S130 of checking whether the image magnification is selected, when it is confirmed that the magnification of the image is selected, an N value is added to the total pixel sum, and a total pixel count value tc and a repeating pixel coefficient jc are added. Step 140 is stepped up. In addition to adding the N value to the total pixel sum (sum) and increasing the total pixel count value (tc) and the repeating pixel coefficient (jc) by one step (140), the N value is added to the total pixel sum (sum) and When the total pixel count value tc and the repeating pixel coefficient jc are increased by one step, a step 150 of checking whether the total pixel sum is greater than or equal to the M value is performed.

In step 150, if the total pixel sum is greater than or equal to the M value, if the total pixel sum is greater than or equal to the M value, the total pixel count value tc is greater than or equal to the N value. Step 160 is performed. In step S160, when the total pixel count value tc is greater than or equal to the N value, if the total pixel count value tc is not greater than or equal to the N value, the M value is subtracted from the total pixel sum sum and repeated. A step S170 is performed in which the pixel coefficient jc is initialized to "0" and the step increase value ac is increased by one step. Conversely, if the total pixel count value tc is greater than or equal to the N value in step 160 of checking whether the total pixel count value tc is greater than or equal to the N value, the image is corrected using the repeating pixel coefficient jc. The image is enlarged using the repeated pixel coefficient jc calculated by performing the step S220, and then the image quality is corrected by performing tab interpolation.

If the enlargement of the image is not selected at step 130 of confirming whether the enlargement of the image is selected, the image is recognized as being reduced and the M value is added to the total pixel sum, and the total pixel count value (tc) is repeated. In step 180, the pixel coefficient jc is increased by one step. In addition to adding the M value to the total pixel sum (sum) and increasing the total pixel count value (tc) and the repeating pixel coefficient (jc) by one step, the M value is added to the total pixel sum (sum) When the total pixel count value tc and the repeating pixel coefficient jc are increased by one step, a step S190 of checking whether the total pixel sum is greater than or equal to the N value is performed.

In operation S190, if the total pixel sum is greater than or equal to the N value, if the total pixel sum is greater than or equal to the N value, the total pixel count value tc is greater than or equal to M. Step S200 is performed. In the step S200 of checking whether the total pixel count value tc is greater than or equal to M, if the total pixel count value tc is not greater than or equal to M, the N value is subtracted from the total pixel sum sum and the repeated pixel count Initializing (jc) to " 0 " and increasing the step increment value ac by one step (S210), on the contrary, if the total pixel count value tc is greater than or equal to the M value, the repetition pixel coefficient jc ) To correct the image (S220). An embodiment of calculating a repeating pixel coefficient (jc) value when the image is enlarged or reduced by the M / N magnification will be described with reference to FIGS. 8A to 8C.

8A to 8C are tables showing coefficient calculation data of the image quality correction apparatus according to the present invention. FIG. 8A is a repetitive pixel coefficient jc when the magnification is 7000/768 when the image is magnified to the M / N magnification in the horizontal direction. The process of calculating As shown in FIG. 8A, the repetition pixel coefficient jc is not calculated as an integer multiple when the image is enlarged at 7000/768 magnification. In this case, the repetition pixel coefficient jc is stored and used in advance. In FIG. 8B, the repetition pixel coefficient jc is calculated as an integer multiple when enlarged to 10240/1024, and FIG. 8C illustrates a calculation process of the repetitive pixel coefficient jc when reduced to 100/1024. When reducing to 100/1024 as shown in FIG. 8C, an output address of "0, 11, 21, ..., 1024" is output to reduce the image size.

As described above, the repetition filter coefficient value is calculated in advance, and the repetition filter coefficient value is used to correct the enlargement / reduction of the image by using the repetition filter coefficient value. It can be saved.

As described above, the present invention can reduce the hardware burden by reducing the number of multipliers by reducing the number of multipliers in the image scaler, and the repeated filter coefficients are not only integers but also magnified for any magnification that is not repeated. Provides the effect of correcting distortion.

Claims (23)

An apparatus for correcting an image quality of an image that is enlarged or reduced in an image scaler used to enlarge or reduce an image image, Receives a counter control signal and generates and continuously outputs a first selection signal for designating and outputting a repetitive filter coefficient when the image is enlarged / reduced. Counter unit for generating a continuous output; A multiplexer unit receiving the first selection signal and the second selection signal output from the counter unit and outputting a first iteration filter coefficient and a second iteration filter coefficient according to the received first selection signal and the second selection signal; Receives the first iteration filter coefficient and the input image data, and sequentially feeds back the first iteration filter coefficient to the first iteration filter coefficient received to generate a first filter coefficient value, and generates the first filter coefficient value and the received first filter coefficient value. A first data generator configured to output first image data by multiplying the input image data; The first filter coefficient value and the second repeat filter coefficient are continuously received and added to generate a second filter coefficient value, and the second filter coefficient value is fed back to receive the first filter coefficient value and is selectively received. A third filter coefficient value is generated by selectively adding the second filter coefficient value and the first filter coefficient value to the filter coefficient value, and generating the second image data by multiplying the generated third filter coefficient value and the received image data. A second data generator; And And an image data adder configured to add and output first image data output from the first data generator and second image data output from the second data generator. 2. The apparatus of claim 1, wherein the first data generator comprises: a first Ra register configured to receive and output the first iterative filter coefficient; Receiving the first iterative filter coefficient and the value '0' and receiving the first external selection signal and selecting and outputting the first iterative filter coefficient sequentially received with the '0' value according to the first external selection signal; 1 multiplexer; Receiving a first repeating filter coefficient output from the first Ra register, receiving and adding a value of '0' selected and output from the first multiplexer and the first repeating filter coefficient to generate and output a first filter coefficient value. A first adder; A second Ra register configured to receive the first repeating filter coefficient and the first filter coefficient value output from the first adder, transmit the received first repeating filter coefficient to the first multiplexer, and output the received first filter coefficient value ; A third Ra register for receiving and outputting input image data; Receives the first repeating filter coefficient and the first filter coefficient value output from the second Ra register, receives the input image data output from the third Ra register, multiplies the first filter coefficient value, and generates first image data. A first multiplier for outputting; And And a fourth Ra register configured to receive and output first image data output from the first multiplier. 3. The apparatus of claim 2, wherein the third Ra register is used to enlarge / reduce the image in a horizontal direction and to configure a line memory to enlarge / reduce the image in a vertical direction of the image. 2. The apparatus of claim 1, wherein the second data generator comprises: a first Rb register for receiving and outputting the first iterative filter coefficient; A second Rb register for receiving and outputting the second iterative filter coefficient; The first filter coefficient value and the second filter coefficient value output from the second Ra register are sequentially received, and when a second external selection signal is received, the first filter coefficient value and the first filter coefficient according to the received second external selection signal. A second multiplexer for selecting and outputting a second filter coefficient value; Receiving and adding a first repetition filter coefficient output from the first Rb register and a second repetition filter coefficient output from the second Rb register to generate and output a second filter coefficient value, and outputting the second filter coefficient value selected from the second multiplexer A second adder receiving the first filter coefficient value and the second filter coefficient value, adding a second filter coefficient value to generate and output a third filter coefficient value; Receiving the second filter coefficient value and the third filter coefficient value output from the second adder, respectively, transmitting the received second filter coefficient value to the second multiplexer, and receiving and outputting the received third filter coefficient value; 3Rb register; A fourth Rb register for receiving and outputting input image data; A second multiplier configured to receive the third filter coefficient value output from the third Rb register, receive and multiply input image data output from the fourth Rb register, and generate and output second image data; And And a fifth Rb register configured to receive and output second image data output from the second multiplier. 5. The apparatus of claim 4, wherein the fourth Rb register is used when the image is enlarged or reduced in the horizontal direction and the line memory is configured when the image is enlarged or reduced in the vertical direction of the image. The display apparatus of claim 1, wherein the counter unit comprises: a first FC register configured to continuously receive and output a first original image size value at a predetermined period when the image is enlarged; A second FC register configured to receive and store the fed back first original image size value; Receives and outputs a first original image size value output from the first FC register, and feeds the first original image size value fed back to the second FC register to add the second original image size value to the second original image size. FC adder for continuously generating and outputting values; The first original image size value and the second original image size value received from the FC adder are sequentially received and compared with the enlarged image size value, so that the first original image size value and the second original image size value correspond to the enlarged image size value. A comparator for generating and outputting a reset signal when it is reached; And Receiving the reset signal and generating and outputting a first selection signal for continuously outputting a repeating filter coefficient and outputting the second selection signal after delaying a predetermined time after the first selection signal is output and continuously outputting the second selection signal. An image scaler of an image scaler, characterized by comprising an address counter. 7. The apparatus of claim 6, wherein the first FC register receives a first reduced image size value when the image is reduced. The first reduced image size of claim 6, wherein the FC adder receives and outputs a first reduced image size value output from the first FC register when the image is reduced, and feeds back the first reduced image size value. And a second reduced image size value continuously generated and added to the value to output the image scaler. 7. The method of claim 6, wherein the comparator receives the first reduced image size value and the second reduced image size value sequentially output from the FC adder when the image is reduced, and compares the first reduced image size value with the original image size value. And generating a reset signal when the second reduced image size value reaches the original image size value and outputting the reset signal. 7. The apparatus of claim 6, wherein the address counter outputs a third selection signal and a fourth selection signal to increase the number of taps when the image is enlarged / reduced. The method according to claim 1 or 10, The multiplexer may include: a first FC multiplexer configured to receive a first repeating filter coefficient and receive a first selection signal output from the counter unit to continuously output a first repeating filter coefficient; A second FC multiplexer receiving a second repeating filter coefficient and receiving a second selection signal output from the counter unit to continuously output a second repeating filter coefficient; A third FC multiplexer which receives a third repeating filter coefficient and receives a third selection signal output from the counter unit and continuously outputs a third repeating filter coefficient; And And a fourth FC multiplexer configured to receive a fourth repeated filter coefficient and receive a fourth selection signal output from the counter to continuously output a fourth repeated filter coefficient value. The method of claim 11, wherein the first and second iterative filter coefficients, the second iterative filter coefficient and the third iterative filter coefficient received by the first FC multiplexer, the second FC multiplexer, the third FC multiplexer, and the fourth FC multiplexer respectively. An iterative filter coefficient has the same value when the magnification factor is an integer multiple, and an unequal value is used when it is not an integer multiple. 12. The method of claim 11, wherein the third image filter, the fourth image filter and the fifth image data are received by receiving the third iteration filter coefficient and the fourth iterative filter coefficient respectively output from the third FC multiplexer and the fourth FC multiplexer. And a third data generator, a fourth data generator, and a fifth data generator to generate the image quality control unit. 14. The apparatus of claim 1 or 13, wherein the third data generator comprises: a first Rc register for receiving and outputting the second iterative filter coefficient; A second Rc register configured to receive and output the third iterative filter coefficient; The second filter coefficient value and the fourth filter coefficient value output from the second Rb register are sequentially received, and when a third external selection signal is received, the second filter coefficient value and the second filter coefficient value according to the received third external selection signal. A third multiplexer for selecting and outputting four filter coefficient values; Receiving and adding a second repeating filter coefficient output from the first Rc register and a third repeating filter coefficient output from the second Rc register to generate and output a fourth filter coefficient value, and outputting the fourth filter coefficient value selected from the third multiplexer A third adder for generating and outputting a fifth filter coefficient value by adding a fourth filter coefficient value to the second filter coefficient value and the fourth filter coefficient value; Receiving a fourth filter coefficient value and a fifth filter coefficient value respectively output from the third adder, transmitting the received fourth filter coefficient value to the third multiplexer, and receiving and outputting the received fifth filter coefficient value; 3Rc register; A fourth Rc register for receiving and outputting input image data; A third multiplier that receives the fifth filter coefficient value output from the third Rc register and receives and multiplies the input image data output from the fourth Rc register to generate and output third image data; And And a fifth Rc register configured to receive and output third image data output from the third multiplier. 15. The apparatus of claim 14, wherein the fourth Rc register is used to enlarge / reduce the image in a horizontal direction and to configure a line memory to enlarge / reduce the image in a vertical direction of the image. 15. The apparatus of claim 13 or 14, wherein the fourth data generator comprises: a first Rd register configured to receive and output the third iterative filter coefficient; A second Rd register configured to receive and output the fourth iterative filter coefficient; Receiving the fourth filter coefficient value and the sixth filter coefficient value sequentially output from the second Rc register, and receiving the fourth external selection signal according to the received fourth external selection signal, the fourth filter coefficient value and the fourth filter coefficient value. A fourth multiplexer for selecting and outputting six filter coefficient values; The third repeated filter coefficients output from the first Rd register and the fourth repeated filter coefficients output from the second Rd register are received and added to generate and output a sixth filter coefficient value, and are selected and output from the fourth multiplexer. A fourth adder for generating and outputting a seventh filter coefficient value by adding a sixth filter coefficient value to the fourth filter coefficient value and the sixth filter coefficient value; Receiving the sixth filter coefficient value and the seventh filter coefficient value output from the fourth adder, respectively, transmitting the received sixth filter coefficient value to the fourth multiplexer, and receiving and outputting the received seventh filter coefficient value; 3Rd register; A fourth Rd register for receiving and outputting input image data; A fourth multiplier configured to receive the seventh filter coefficient value output from the third Rd register, receive and multiply input image data output from the fourth Rd register, and generate and output fourth image data; And And a fifth Rd register configured to receive and output fourth image data output from the fourth multiplier. 17. The apparatus of claim 16, wherein the fourth Rd register is used to enlarge / reduce the image in a horizontal direction and to configure a line memory to enlarge / reduce the image in a vertical direction of the image. 17. The apparatus of claim 13 or 16, wherein the fifth data generator comprises: a first Re register receiving and outputting the fourth iterative filter coefficient; The sixth filter coefficient value output from the second Rd register and the fourth repetition filter coefficient are sequentially received, and when the fifth external selection signal is received, the sixth filter coefficient value and the fifth filter according to the received fifth external selection signal. A fifth multiplexer for selecting and outputting four repetitive filter coefficients; Receive a fourth iterative filter coefficient output from the first Re register, add to the sixth filter coefficient value and the fourth iterative filter coefficient value selected and output from the fourth multiplexer, respectively, to generate an eighth filter coefficient value, and output the same. A fifth adder; Receiving the fourth iterative filter coefficient value and the eighth filter coefficient value respectively output from the fifth adder, transmitting the received fourth iterative filter coefficient to the fifth multiplexer, and receiving and outputting the received eighth filter coefficient value; 2Re register; A third Re register for receiving and outputting input image data; A fifth multiplier configured to receive the eighth filter coefficient value output from the second Rd register, receive and multiply input image data output from the third Re register, and generate and output fifth image data; And And a fourth Re register receiving and outputting fifth image data output from the fifth multiplier. 19. The apparatus of claim 18, wherein the third register is used to enlarge / reduce the image in the horizontal direction and to configure the line memory to enlarge / reduce the image in the vertical direction. In the method of using the image scaler to correct the image quality when the image is enlarged or reduced, Selecting an enlargement or reduction of an image by M / N magnification; Initializing the total pixel sum, the total pixel count value, the repetition pixel count, and the step increment value to “0” when the enlargement or reduction of the image is selected in the step of enlarging or reducing the image; When the total pixel sum, the total pixel count value, the repeat pixel count value, the repeat pixel count, and the step increment value are initialized to "0", respectively, in the step of initializing the total pixel sum, the total pixel count value, the repeat pixel count, and the step increment value, respectively. Confirming whether image magnification is selected; If it is determined that the enlargement of the image is selected in the step of confirming whether the enlargement of the image is selected, adding N to the total pixel sum and increasing the total pixel count value and the repeating pixel coefficient by one step; In the step of adding the N value to the total pixel sum and increasing the total pixel count value and the repeating pixel coefficient by one step, when the total pixel count value and the repeating pixel coefficient are increased by one step Checking whether the total pixel sum is greater than or equal to the M value; Checking whether the total pixel count value is greater than or equal to the N value if the total pixel sum is greater than or equal to the M value in the checking whether the total pixel sum is greater than or equal to the M value; And And if the total pixel count value is greater than or equal to an N value, correcting an image using a repeating pixel coefficient if the total pixel count value is greater than or equal to an N value. The method of claim 1, wherein in the determining whether the total pixel count value is greater than or equal to the N value, the M value is subtracted from the total pixel sum and the repetition filter coefficient is “0” if the total pixel count value is not greater than or equal to the N value. And increasing the step increment value by one step. The method of claim 1, wherein in the step of confirming whether the image enlargement is selected, if the image enlargement is not selected, the image reduction is selected and the M value is added to the total pixel sum, and the total pixel count value and the repetition pixel count are added. Increasing step by step; In the step of adding the M value to the total pixel sum and increasing the total pixel count value and the repetition filter coefficient by one step, if the M value is added to the total pixel sum and the total pixel count value and the repeating pixel coefficient are increased by one step, Checking whether the total pixel sum is greater than or equal to an N value; Checking whether the total pixel count value is greater than or equal to the M value if the total pixel sum is greater than or equal to the N value in the checking whether the total pixel sum is greater than or equal to the N value; And And if the total pixel count value is greater than or equal to the M value, correcting an image using a repeating pixel coefficient if the total pixel count value is greater than or equal to the M value. 23. The method of claim 22, wherein in the step of checking whether the total pixel count value is greater than or equal to the M value, if the total pixel count value is not greater than or equal to the M value, the N value is subtracted from the total pixel sum and the repeating pixel coefficient is "0." And increasing the step increment value by one step.