KR20020003005A - Method for forming gate electrode in semiconductor device - Google Patents
Method for forming gate electrode in semiconductor device Download PDFInfo
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- KR20020003005A KR20020003005A KR1020000037387A KR20000037387A KR20020003005A KR 20020003005 A KR20020003005 A KR 20020003005A KR 1020000037387 A KR1020000037387 A KR 1020000037387A KR 20000037387 A KR20000037387 A KR 20000037387A KR 20020003005 A KR20020003005 A KR 20020003005A
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- silicon layer
- epitaxial silicon
- gate electrode
- forming
- oxide film
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 33
- 239000010703 silicon Substances 0.000 claims abstract description 33
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 18
- 239000010937 tungsten Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 4
- 239000000126 substance Substances 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 230000009977 dual effect Effects 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- -1 boron ions Chemical class 0.000 claims 2
- 125000006850 spacer group Chemical group 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 238000000151 deposition Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 208000012868 Overgrowth Diseases 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 에피택셜 실리콘층을 이용한 게이트전극의 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming a gate electrode using an epitaxial silicon layer.
일반적으로, 반도체소자의 게이트전극은 폴리실리콘을 이용하는데, 반도체소자의 디자인룰이 감소됨에 다라 게이트전극의 두께 또한 2500Å에서 점점 작아져 700Å의 두께를 갖는 게이트전극에 대한 연구가 진행되고 있다. 그러나, 폴리실리콘의 두께가 작아지면서 게이트저항이 전체 전극에서 차지하는 부분이 커지므로 폴리실리콘에서 형성되는 기생캐패시턴스가 소자특성을 열화시킬 수 있다.In general, a gate electrode of a semiconductor device uses polysilicon. As the design rule of the semiconductor device is reduced, the thickness of the gate electrode is also gradually decreased from 2500 kV to a gate electrode having a thickness of 700 kV. However, as the thickness of the polysilicon decreases, the portion of the gate resistance occupies the entire electrode increases, so that parasitic capacitance formed in the polysilicon may deteriorate device characteristics.
특히, 듀얼 게이트전극(Dual gate electrode)을 형성하는 방법은 비정질실리콘(Amorphous Silicon)을 증착하고 도펀트(Dopant)를 이온주입한 후 열처리로 활성화시키는데, 이 방법은 도펀트의 활성화율이 낮아서 게이트저항이 높고 게이트디플리션(Gate depletion) 현상이 발생하여 소자 특성이 열화된다.In particular, a method of forming a dual gate electrode is activated by heat treatment after depositing amorphous silicon, implanting dopants and ion implantation. This method has low gate resistance due to low activation rate of dopants. High and gate depletion occurs, resulting in deterioration of device characteristics.
상기 게이트저항의 증가를 방지하기 위해 게이트전극으로 텅스텐을 이용하는 방법이 제안되었는데(도 1참조), 텅스텐(14)과 폴리실리콘(13) 사이의 반응을 억제하기 위해 텅스텐(14) 증착 후 NH3열처리를 하는데, 폴리실리콘(13)의 결정화기 완전하지 못하면 후속 열처리 공정에서 부분적으로 텅스텐(14)과 폴리실리콘(13)이 반응하여 텅스텐실리사이드(17)를 형성하는 문제점이 있다. 여기서, 미설명 도면부호 11은 반도체기판, 12는 게이트산화막, 15는 측벽스페이서, 16은 소스/드레인을 나타낸다.In order to prevent the increase of the gate resistance, a method of using tungsten as a gate electrode has been proposed (see FIG. 1), and NH 3 after deposition of tungsten 14 to suppress the reaction between tungsten 14 and polysilicon 13 is proposed. If the crystallization of the polysilicon 13 is not complete, the tungsten 14 and the polysilicon 13 partially react in the subsequent heat treatment to form the tungsten silicide 17. Here, reference numeral 11 denotes a semiconductor substrate, 12 a gate oxide film, 15 a sidewall spacer, and 16 a source / drain.
한편, 텅스텐실리사이드의 형성을 방지하기 위해 텅스텐증착전에 폴리실리콘을 열처리하기도 하지만 이 방법도 게이트저항을 감소시키는데는 한계가 있다.On the other hand, although polysilicon is heat-treated before tungsten deposition to prevent the formation of tungsten silicide, this method also has a limitation in reducing the gate resistance.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 에피택셜 성장법으로 형성된 단결정실리콘을 게이트전극으로 이용하므로써, 게이트저항의 증가를 방지하는데 적합한 게이트전극의 형성 방법을 제공함에 그 목적이 있다.The present invention has been made to solve the problems of the prior art, by using a single crystal silicon formed by the epitaxial growth method as a gate electrode, to provide a method of forming a gate electrode suitable for preventing the increase of the gate resistance have.
도 1은 종래기술에 따른 게이트전극의 형성 방법을 도시한 도면,1 is a view showing a method of forming a gate electrode according to the prior art;
도 2a 내지 도 2d는 본 발명의 실시예에 따른 게이트전극의 형성 방법을 도시한 도면.2A to 2D illustrate a method of forming a gate electrode according to an exemplary embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 필드산화막21 semiconductor substrate 22 field oxide film
23 : 게이트산화막 24 : 에피택셜 실리콘층23 gate oxide film 24 epitaxial silicon layer
25 : 텅스텐막 26 : 측벽스페이서25 tungsten film 26 side wall spacer
27 : 소스/드레인27: source / drain
상기의 목적을 달성하기 위한 본 발명의 게이트전극의 형성 방법은 반도체기판상에 산화막을 형성하는 제 1 단계; 상기 산화막을 선택적으로 식각하여 상기 반도체기판의 소스/드레인이 형성될 영역을 노출시키는 게이트산화막을 형성하는 제 2 단계; 상기 게이트산화막상에 오버랩되어 서로 접속되도록 상기 노출된 소스/드레인상에 에피택셜 실리콘층을 과도성장시키는 제 3 단계; 상기 에피택셜 실리콘층을 화학적기계적연마하는 제 4 단계; 및 상기 게이트산화막상의 에피택셜 실리콘층상에 텅스텐막을 형성한 후, 상기 텅스텐막과 에피택셜 실리콘층을 선택적으로 식각하여 게이트전극을 형성하는 제 5 단계를 포함하여 이루어짐을 특징으로 한다.A method of forming a gate electrode of the present invention for achieving the above object comprises a first step of forming an oxide film on a semiconductor substrate; Selectively etching the oxide film to form a gate oxide film exposing a region where a source / drain of the semiconductor substrate is to be formed; Overgrowing an epitaxial silicon layer on the exposed source / drain so as to overlap each other on the gate oxide layer and to be connected to each other; A fourth step of chemical mechanical polishing the epitaxial silicon layer; And forming a tungsten film on the epitaxial silicon layer on the gate oxide film, and then selectively etching the tungsten film and the epitaxial silicon layer to form a gate electrode.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2d는 본 발명의 실시예에 따른 게이트전극의 형성 방법을 도시한 도면이다.2A to 2D illustrate a method of forming a gate electrode according to an exemplary embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체기판(21)에 소자간 격리를 위한 필드산화막(22)을 형성한 다음, 상기 반도체기판(21)상에 산화막을 700℃∼1000℃에서 열산화법으로 20Å∼70Å의 두께로 형성한다. 이 때, 상기 필드산화막(22)은 STI(Shallow Trench Isolation)공정에 의해 형성된다.As shown in FIG. 2A, a field oxide film 22 for inter-element isolation is formed on the semiconductor substrate 21, and then, on the semiconductor substrate 21, the oxide film is subjected to thermal oxidation at 700 to 1000 캜 by thermal oxidation. It is formed to a thickness of 70Å. In this case, the field oxide layer 22 is formed by a shallow trench isolation (STI) process.
이어 상기 산화막을 선택적으로 식각하여 반도체기판(21)을 노출시키되, 후속 게이트전극이 형성될 부분의 산화막은 잔류시켜 게이트산화막(23)으로 이용하고, 이 때, 노출되는 부분은 후속 소스/드레인이 형성될 부분이다.Subsequently, the oxide film is selectively etched to expose the semiconductor substrate 21, but the oxide film of the portion where the subsequent gate electrode is to be formed remains to be used as the gate oxide film 23. At this time, the exposed portion is formed by the subsequent source / drain. The part to be formed.
도 2b에 도시된 바와 같이, 실리콘에피택셜 과도성장법(Silicon epitaxtial overgrowth)을 이용하여 상기 노출된 소스/드레인 영역상에 에피택셜 실리콘층(24)을 형성하되, 상기 게이트산화막(23)을 완전히 덮을때까지 에피택셜 실리콘층(24)을 형성한다.As shown in FIG. 2B, an epitaxial silicon layer 24 is formed on the exposed source / drain regions using silicon epitaxtial overgrowth, but the gate oxide layer 23 is completely removed. The epitaxial silicon layer 24 is formed until it is covered.
이 때, 상기 에피택셜 실리콘층(24)은 화학적기상증착법(Chemical Vapor Deposition; CVD)으로 500℃∼1100℃의 온도, 10-5∼103torr의 압력하에서 SiH4, Si2H6, HCl, Cl 또는 H2중 어느 하나의 가스를 사용하여 성장된다. 여기서, 상기 에피택셜 실리콘층(24)을 N형으로 사용하는 경우에는 인(Phosphorus)을 도핑하고, P형으로 이용하는 경우에는 보론(Boron)을 도핑한다.At this time, the epitaxial silicon layer 24 is chemical vapor deposition (CVD) at a temperature of 500 ℃ to 1100 ℃, SiH 4 , Si 2 H 6 , HCl at a pressure of 10 -5 to 10 3 torr It is grown using a gas of either Cl, or H 2 . In this case, when the epitaxial silicon layer 24 is used as the N type, phosphorous is doped, and when the P epitaxial silicon layer 24 is used, the boron is doped.
도 2c에 도시된 바와 같이, 화학적기계적연마공정을 실시하여 500Å∼2500Å의 두께만큼 잔류하는 에피택셜실리콘층(24a)을 형성한다. 이어 만약, 듀얼 게이트전극을 위해 도핑이 안된 상태로 성장된 경우에는 보론 또는 인을 이온주입한다.As shown in FIG. 2C, the chemical mechanical polishing process is performed to form the epitaxial silicon layer 24a remaining by the thickness of 500 kPa to 2500 kPa. Subsequently, when grown in an undoped state for the dual gate electrode, ion implanted with boron or phosphorus.
도 2d에 도시된 바와 같이, 상기 연마된 에피택셜 실리콘층(24a)상에 텅스텐(25)을 증착한 후, 상기 텅스텐(25)과 에피택셜 실리콘층(24a)을 선택적으로 식각하여 상기 게이트산화막(23)상에 에피택셜 실리콘층(24b)과 텅스텐(25)의 적층막으로 이루어지는 게이트전극을 형성한다. 이어 후속 공정으로 상기 게이트전극의 측벽에 접하는 측벽스페이서(26)를 형성하고, 상기 측벽스페이서 및 게이트전극을 마스크로 이용한 고농도 불순물 이온주입으로 상기 측벽스페이서 하측의 반도체기판에 소스/드레인(27)을 형성한다.As shown in FIG. 2D, after depositing tungsten 25 on the polished epitaxial silicon layer 24a, the tungsten 25 and the epitaxial silicon layer 24a are selectively etched to form the gate oxide layer. On 23, a gate electrode made of a laminated film of epitaxial silicon layer 24b and tungsten 25 is formed. Subsequently, a sidewall spacer 26 is formed in contact with the sidewall of the gate electrode in a subsequent process, and a source / drain 27 is formed on the semiconductor substrate under the sidewall spacer by the implantation of high concentration impurity ions using the sidewall spacer and the gate electrode as a mask. Form.
상술한 바와 같이, 게이트전극으로 에피택셜 실리콘층을 이용하면, 통상 폴리실리콘에 비해 낮은 게이트저항을 나타낸다.As described above, when the epitaxial silicon layer is used as the gate electrode, the gate resistance is generally lower than that of polysilicon.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 게이트전극의 형성 방법은 통상 폴리실리콘에 비해 낮은 저항을 갖는 에피택셜 실리콘을 게이트전극으로 이용하므로써, 게이트전극의 저항을 감소시켜 기생캐패시턴스를 감소시킬 수 있는 효과가 있다.As described above, the gate electrode forming method of the present invention uses epitaxial silicon having a lower resistance than polysilicon as the gate electrode, thereby reducing parasitic capacitance by reducing the resistance of the gate electrode.
그리고, 텅스텐 증착전에 폴리실리콘을 결정화하는 열처리 공정을 생략하고, 열처리로 결정화한 폴리실리콘에 비해 구조적으로 완전하므로 후속 열처리를 사용한 텅스텐과 에피택셜 실리콘층 사이의 반응억제막 형성이 용이한 효과가 있다.In addition, since the heat treatment process of crystallizing polysilicon before tungsten deposition is omitted and structurally complete compared to polysilicon crystallized by heat treatment, it is easy to form a reaction suppression film between tungsten and the epitaxial silicon layer using subsequent heat treatment. .
Claims (6)
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| KR1020000037387A KR20020003005A (en) | 2000-06-30 | 2000-06-30 | Method for forming gate electrode in semiconductor device |
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| KR1020000037387A KR20020003005A (en) | 2000-06-30 | 2000-06-30 | Method for forming gate electrode in semiconductor device |
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