KR20020002569A - Method for forming contact plug in semiconductor device - Google Patents
Method for forming contact plug in semiconductor device Download PDFInfo
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- KR20020002569A KR20020002569A KR1020000036778A KR20000036778A KR20020002569A KR 20020002569 A KR20020002569 A KR 20020002569A KR 1020000036778 A KR1020000036778 A KR 1020000036778A KR 20000036778 A KR20000036778 A KR 20000036778A KR 20020002569 A KR20020002569 A KR 20020002569A
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- South Korea
- Prior art keywords
- polysilicon
- plug
- contact plug
- forming
- pattern
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 68
- 229920005591 polysilicon Polymers 0.000 claims abstract description 68
- 238000009792 diffusion process Methods 0.000 claims abstract description 21
- 238000005498 polishing Methods 0.000 claims abstract description 20
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 239000000126 substance Substances 0.000 claims abstract description 14
- 239000002002 slurry Substances 0.000 claims abstract description 11
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical group O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 12
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims description 9
- 239000000460 chlorine Substances 0.000 claims description 7
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 5
- 229910052731 fluorine Inorganic materials 0.000 claims description 5
- 239000011737 fluorine Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910052801 chlorine Inorganic materials 0.000 claims description 3
- 229910004166 TaN Inorganic materials 0.000 claims description 2
- 229910010037 TiAlN Inorganic materials 0.000 claims description 2
- 229910008484 TiSi Inorganic materials 0.000 claims description 2
- 229910008482 TiSiN Inorganic materials 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- KYKAJFCTULSVSH-UHFFFAOYSA-N chloro(fluoro)methane Chemical compound F[C]Cl KYKAJFCTULSVSH-UHFFFAOYSA-N 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 239000005380 borophosphosilicate glass Substances 0.000 claims 1
- 239000003795 chemical substances by application Substances 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 239000003990 capacitor Substances 0.000 abstract description 7
- 239000012535 impurity Substances 0.000 description 9
- 125000006850 spacer group Chemical group 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- -1 CClF 3 + Cl 3 Chemical compound 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 캐패시터전극의 하부 금속플러그의 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a lower metal plug of a capacitor electrode.
일반적으로, 제 2 폴리실리콘플러그(Plug poly-2)형성 방법은 비트라인배선을 형성하고 절연막을 증착한 다음, 상기 절연막을 화학적기계적연마하여 평탄화한 다음, 제 3 폴리실리콘플러그를 위한 마스크 및 식각한후, 제 2 폴리실리콘플러그용 폴리실리콘을 증착한다. 이어 상기 제 2 폴리실리콘플러그용 폴리실리콘을 전면에치하거나 또는 화학적기계적연마(Chemical Mechanical Polishing)하여 콘택플러그를 형성하는데, 이러한 공정은 콘택마스크/식각시 비트라인 마스크질화막 또는 마스크산화막의 손실로 인한 비트라인 배선과 제 2 폴리실리콘플러그간 누설전류 증가 및 오정렬(Misalign)로 인한 제 1 폴리실리콘플러그와의 접촉면적이 감소되어 소자의 특성이 악화된다.In general, the second polysilicon plug (Plug poly-2) forming method is to form a bit line wiring, deposit an insulating film, and then planarize by chemical mechanical polishing the insulating film, and then mask and etching for the third polysilicon plug After that, polysilicon for the second polysilicon plug is deposited. Subsequently, the second polysilicon plug-type polysilicon is placed on the entire surface or chemical mechanical polishing to form a contact plug. This process is performed due to the loss of the bit line mask nitride layer or mask oxide layer during contact mask / etching. The contact area of the first polysilicon plug due to an increase in leakage current and misalignment between the bit line wiring and the second polysilicon plug is reduced, thereby deteriorating characteristics of the device.
상기의 문제점을 해결하기 위한 종래기술에 대해 설명하기로 한다.The prior art for solving the above problems will be described.
도 1a 내지 도 1d는 종래기술에 따른 금속플러그의 형성 방법을 도시한 도면이다.1A to 1D are views illustrating a method of forming a metal plug according to the prior art.
도 1a에 도시된 바와 같이, 워드라인(도시 생략), 불순물접합층(12)이 형성된 반도체 기판(11)상에 워드라인절연막(13)을 증착한후, 상기 워드라인절연막(13)을 선택적으로 식각하여 상기 불순물접합층(12)이 노출되는 플러그용 콘택홀을 형성한다. 이어 상기 플러그용 콘택홀을 포함한 전면에 플러그용 폴리실리콘을 증착한후, 전면식각하거나 화학적기계적연마하여 상기 콘택홀에 매립되는 제 1 콘택플러그(14)를 형성한다.As shown in FIG. 1A, after the word line insulating layer 13 is deposited on the semiconductor substrate 11 on which the word line (not shown) and the impurity bonding layer 12 are formed, the word line insulating layer 13 is selectively formed. Etching to form a plug contact hole through which the impurity bonding layer 12 is exposed. Subsequently, after the plug polysilicon is deposited on the front surface including the plug contact hole, the first contact plug 14 embedded in the contact hole is formed by etching the entire surface or chemical mechanical polishing.
이어 상기 제 1 콘택플러그(14)를 포함한 전면에 확산방지막(15a), 비트라인용 배선막(15b), 버퍼용 질화막(15c), 마스크산화막(15d)을 순차적으로 증착한후, 상기 마스크산화막(15d), 버퍼용 질화막(15c), 비트라인용 배선막(15b), 확산방지막(15a)을 선택적으로 패터닝하여 비트라인배선(15)을 형성한다. 이어 상기 비트라인배선(15)을 포함한 전면에 측벽용 산화막을 증착한 다음, 전면식각하여 상기 비트라인의 측벽에 접하는 측벽스페이서(15e)를 형성한다. 이어 상기 측벽스페이서 (15e)를 포함한 비트라인배선(15)의 전면에 제 2 플러그용 폴리실리콘(16)을 증착한다.Subsequently, the diffusion barrier layer 15a, the bit line interconnection layer 15b, the buffer nitride layer 15c, and the mask oxide layer 15d are sequentially deposited on the entire surface including the first contact plug 14, and then the mask oxide layer is deposited. 15d, the buffer nitride film 15c, the bit line wiring film 15b, and the diffusion barrier film 15a are selectively patterned to form the bit line wiring 15. As shown in FIG. Subsequently, an oxide film for sidewalls is deposited on the entire surface including the bit line wirings 15 and then etched to form sidewall spacers 15e that contact the sidewalls of the bit lines. Subsequently, a second plug polysilicon 16 is deposited on the entire surface of the bit line wiring 15 including the sidewall spacers 15e.
도 1b에 도시된 바와 같이, 라인형 마스크(17)를 이용하여 상기 워드라인절연막(13)이 드러날때까지 상기 제 2 플러그용 폴리실리콘(16)을 식각하여 제 2 콘택플러그패턴(16a)를 형성할 때, 상기 비트라인배선(15)의 마스크산화막(15d)이 500Å만큼 국부적으로 손실된다(A).As shown in FIG. 1B, the second contact plug pattern 16a is etched by etching the second plug polysilicon 16 until the word line insulating layer 13 is exposed using the line mask 17. When formed, the mask oxide film 15d of the bit line wiring 15 is locally lost by 500 [mu] s (A).
도 1c에 도시된 바와 같이, 상기 제 2 콘택플러그패턴(16a)을 포함한 전면에 비트라인절연막(18)을 상기 비트라인배선(15)보다 500∼3000Å만큼 두껍게 증착한다.As illustrated in FIG. 1C, a bit line insulating layer 18 is deposited on the entire surface including the second contact plug pattern 16a by 500 to 3000 Å thicker than the bit line wiring 15.
도 1d에 도시된 바와 같이, 상기 비트라인절연막(18)을 산화막용 슬러리를 이용하여 화학적기계적연마하여 국부단차를 제거하기 위해 제 2 콘택플러그패턴(16a)을 분리시킨다(16b). 이 때, 상기 비트라인배선(15)의 마스크산화막(15d)은 웨이퍼의 가장자리지역에서는 연마균일도의 악화로 인해 1000Å만큼 잔류하고(B), 웨이퍼의 중심지역에서는 1500Å만큼 잔류하며(C), 이는 후속 제 2 콘택플러그 (16b)의 리세스에치백(Recess etchbakck), 확산방지막의 화학적기계적연마(CMP) 및 캐패시터산화막의 식각공정에서 연속적으로 발생하는 마스크산화막(15d)의 손실로 인해 비트라인배선과 캐패시터간 브릿지가 형성되거나 누설전류가 증가하여 소자의 오류를 유도하는 문제점이 잇다.As shown in FIG. 1D, the bit contact insulating layer 18 is chemically mechanically polished using the slurry for the oxide film to separate the second contact plug pattern 16a to remove the local step (16b). At this time, the mask oxide film 15d of the bit line wiring 15 remains at 1000 Å in the edge region of the wafer due to deterioration of the polishing uniformity (B) and at 1500 에서는 in the center region of the wafer (C). Bit line wiring due to the loss of the mask oxide film 15d that is continuously generated in the subsequent recess etchbakck of the second contact plug 16b, chemical mechanical polishing of the diffusion barrier film, and etching of the capacitor oxide film. There is a problem of inducing device errors due to the formation of a bridge between the capacitor and the leakage current.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 캐패시터 콘택플러그형성시 비트라인의 마스크산화막의 손실을 최소화하면서 캐패시터와 비트라인간의 브릿지를 방지하는데 적합한 콘택플러그의 형성 방법을 제공함에 그 목적이 있다.The present invention has been made to solve the problems of the prior art, and provides a method for forming a contact plug suitable for preventing the bridge between the capacitor and the bit line while minimizing the loss of the mask oxide film of the bit line when forming the capacitor contact plug. There is a purpose.
도 1a 내지 도 1d는 종래기술에 따른 콘택플러그의 형성 방법을 도시한 도면,1A to 1D illustrate a method of forming a contact plug according to the prior art;
도 2는 본 발명의 실시예에 따른 콘택플러그의 형성방법을 도시한 평면도,2 is a plan view illustrating a method of forming a contact plug according to an embodiment of the present invention;
도 3a 내지 도 3d는 본 발명의 실시예에 따른 콘택플러그의 형성 방법을 도시한 도면.3A to 3D illustrate a method of forming a contact plug according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 워드라인21: semiconductor substrate 22: word line
23 : 불순물접합층 24 : 워드라인절연막23 impurity bonding layer 24 word line insulating film
25 : 제 1 콘택플러그 26 : 비트라인배선25: first contact plug 26: bit line wiring
27 : 비트라인용 확산방지막 28 : 비트라인용 배선막27: diffusion barrier film for bit line 28: wiring film for bit line
29 : 버퍼층 30 : 마스크산화막29 buffer layer 30 mask oxide film
31 : 측벽스페이서 32a : 폴리실리콘 플러그패턴31 side wall spacer 32a polysilicon plug pattern
33 : 비트라인절연막 34 : 확산방지금속막33: bit line insulating film 34: diffusion preventing metal film
상기의 목적을 달성하기 위한 본 발명의 콘택플러그의 형성 방법은 제 1 콘택플러그가 형성된 반도체기판상에 상기 제 1 콘택플러그에 접속되고 마스크산화막을 포함하는 적층구조로 이루어진 다수의 비트라인을 형성하는 제 1 단계; 상기 다수의 비트라인 사이의 제 1 콘택플러그에 접속되고 상기 비트라인보다 일정 두께 높게 폴리실리콘 플러그패턴을 형성하는 제 2 단계; 상기 폴리실리콘 플러그패턴상에 상기 비트라인보다 소정두께만큼 높게 절연막을 형성한후, 상기 폴리실리콘 플러그패턴에 대한 선택비가 높은 세리아계 산화막용 슬러리를 이용하여 상기 절연막을 화학적기계적연마하여 상기 폴리실리콘 플러그패턴을 분리시켜 노출시키는 제 3 단계; 후속 확산방지금속막연마공정에서 금속막이 잔류하지 않도록 산화막용 식각제를 이용하여 상기 노출된 폴리실리콘 플러그패턴을 상기 비트라인의 상부까지 식각하는 제 4 단계; 폴리실리콘용 식각제를 이용하여 후속 확산방지금속막이 상기 폴리실리콘플러그패턴내에 채워지는 타겟으로 상기 폴리실리콘 플러그패턴을 리세스시키는 제 5 단계; 및 상기 리세스된 폴리실리콘 플러그패턴상에 확산방지금속막을 형성한후, 화학적기계적연마하여 상기 연마된 확산방지금속막과 폴리실리콘 플러그패턴의 적층구조로 이루어진 제 2 콘택플러그를 형성하는 제 6 단계를 포함하여 이루어짐을 특징으로 한다.A method of forming a contact plug according to the present invention for achieving the above object is to form a plurality of bit lines of a stacked structure connected to the first contact plug and including a mask oxide film on a semiconductor substrate on which the first contact plug is formed. First step; A second step of forming a polysilicon plug pattern connected to a first contact plug between the plurality of bit lines and having a predetermined thickness higher than the bit lines; After the insulating film is formed on the polysilicon plug pattern by a predetermined thickness than the bit line, the polysilicon plug is formed by chemical mechanical polishing of the insulating film using a slurry for ceria oxide film having a high selectivity to the polysilicon plug pattern. A third step of separating and exposing the pattern; A fourth step of etching the exposed polysilicon plug pattern to an upper portion of the bit line by using an etchant for oxide film so that the metal film does not remain in a subsequent diffusion preventing metal film polishing process; A fifth step of recessing the polysilicon plug pattern with a target in which a subsequent diffusion barrier metal film is filled in the polysilicon plug pattern using an polysilicon etchant; And forming a diffusion barrier metal film on the recessed polysilicon plug pattern, and chemically polishing to form a second contact plug formed of a laminated structure of the polished diffusion barrier metal film and the polysilicon plug pattern. Characterized in that comprises a.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2는 본 발명의 실시예에 따른 콘택플러그의 형성방법을 나타낸 평면도로서, 다수의 워드라인(22)과 비트라인배선(26)이 서로 교차하는 방향으로 형성되며, 상기 워드라인(22) 사이의 제 1 콘택플러그(도시되지 않음)상에 제 2 콘택플러그 (35)가 형성된다. 여기서, 상기 제 2 콘택플러그(35)는 확산방지금속막(34)과 폴리실리콘플러그패턴(32a)의 적층막이고, 상기 비트라인배선(26) 사이에 증착된 플러그용 폴리실리콘상에 비트라인절연막(33)을 증착한 다음, 상기 비트라인절연막(33)을 화학적기계적연마하여 상기 플러그용 폴리실리콘을 분리시켜 폴리실리콘 플러그패턴(32)을 형성한다. 이 때, 상기 폴리실리콘 플러그패턴(32) 형성을 위한 화학적기계적연마시, 상기 비트라인배선(26)의 마스크산화막(도 3a의 30)의 손실을 최소화하기 위해 상기 폴리실리콘에 대한 연마선택비가 높은 세리아계 산화막용 슬러리를 이용한다.2 is a plan view illustrating a method of forming a contact plug according to an exemplary embodiment of the present invention, in which a plurality of word lines 22 and bit line wirings 26 are formed to cross each other, and between the word lines 22. A second contact plug 35 is formed on the first contact plug (not shown). Here, the second contact plug 35 is a laminated film of the diffusion preventing metal film 34 and the polysilicon plug pattern 32a, and the bit line is formed on the plug polysilicon deposited between the bit line wirings 26. After the insulating film 33 is deposited, the bit line insulating film 33 is chemically mechanically polished to separate the plug polysilicon to form a polysilicon plug pattern 32. At this time, in the chemical mechanical polishing for forming the polysilicon plug pattern 32, in order to minimize the loss of the mask oxide film (30 of FIG. 3A) of the bit line wiring 26, the polishing selectivity for the polysilicon is high. A slurry for ceria oxide film is used.
도 3a 내지 도 3d는 본 발명의 실시예에 따른 콘택플러그의 형성 방법을 도시한 도면으로서, 좌측은 도 2의 Ⅰ-Ⅰ'선에 따른 공정단면도이고, 우측은 도 2의 Ⅱ-Ⅱ'선에 따른 공정단면도이다.3A to 3D illustrate a method of forming a contact plug according to an exemplary embodiment of the present invention. The left side shows a process cross-sectional view along the line II ′ of FIG. 2, and the right side shows the II-II ′ line of FIG. 2. Process cross section according to.
도 3a에 도시된 바와 같이, 워드라인(도 2의 22), 불순물접합층(23)이 형성된 반도체 기판(21)상에 워드라인절연막(24)을 증착한후, 상기 워드라인절연막(24)을 선택적으로 식각하여 상기 불순물접합층(23)이 노출되는 플러그용 콘택홀을 형성한다. 이어 상기 플러그용 콘택홀을 포함한 전면에 플러그용 폴리실리콘을 증착한후, 전면식각하거나 화학적기계적연마하여 상기 콘택홀에 매립되어 상기 불순물접합층(23)에 접속되는 제 1 콘택플러그(25)를 형성한다.As shown in FIG. 3A, after the word line insulating film 24 is deposited on the semiconductor substrate 21 on which the word lines 22 and the impurity bonding layer 23 are formed, the word line insulating film 24 is formed. Is selectively etched to form a plug contact hole through which the impurity bonding layer 23 is exposed. Subsequently, after the plug polysilicon is deposited on the entire surface including the plug contact hole, the first contact plug 25 embedded in the contact hole by surface etching or chemical mechanical polishing is connected to the impurity bonding layer 23. Form.
여기서, 도면에 도시되지 않았지만, 도 2를 참조하여 도 2의 Ⅰ-Ⅰ'선에 따른 공정에 대해 설명하면, 반도체 기판(21)에 소자격리막을 형성한 후, 상기 반도체 기판(21) 상부에 게이트산화막, 폴리실리콘, 텅스텐실리사이드, 마스크산화막의 적층구조로 이루어진 워드라인(22)을 형성하고, 상기 워드라인(22)의 측벽에 접하는 측벽스페이서를 형성한다. 이어 상기 워드라인(22) 및 측벽스페이서를 마스크로 이용한 불순물 이온주입으로 불순물접합층(23)을 형성한다. 상기한 공정은 공지의기술로서 각 물질을 적용함에 있어서는 제한이 없으며, 본 발명과는 무관하기 때문에 그 자세한 설명을 생략한다.Although not shown in the drawings, a process according to line II ′ of FIG. 2 will be described with reference to FIG. 2. After the device isolation film is formed on the semiconductor substrate 21, the semiconductor substrate 21 is disposed on the semiconductor substrate 21. A word line 22 having a stacked structure of a gate oxide film, polysilicon, tungsten silicide, and a mask oxide film is formed, and sidewall spacers are formed in contact with sidewalls of the word line 22. Subsequently, the impurity junction layer 23 is formed by implanting impurity ions using the word line 22 and the sidewall spacers as a mask. The above-described process is a well-known technique, and there is no limitation in applying each substance, and thus the detailed description thereof is omitted.
이어 상기 제 1 콘택플러그(25)를 통해 상기 불순물접합층(23)과 전기적으로 연결되는 비트라인배선(도 2의 26)을 형성하되, 상기 비트라인배선(26)은 상기 워드라인(22)과 직교하는 방향으로 형성되며, 상기 비트라인배선(26)은 비트라인용 확산방지막(27), 비트라인용 배선막(28), 버퍼층(29), 마스크산화막(30)의 적층구조로 이루어지고 그 측면에 측벽스페이서(31)가 형성된다.Subsequently, a bit line wiring (26 of FIG. 2) is formed to be electrically connected to the impurity bonding layer 23 through the first contact plug 25, and the bit line wiring 26 is the word line 22. It is formed in a direction orthogonal to the bit line, the bit line wiring 26 is made of a laminated structure of the bit line diffusion barrier 27, the bit line wiring film 28, the buffer layer 29, the mask oxide film 30 The side wall spacer 31 is formed in the side surface.
이어 상기 측벽스페이서(31)를 포함한 비트라인배선(26)의 전면에 제 2 플러그용 폴리실리콘으로서 도핑실리콘 또는 폴리실리콘을 400℃∼1200℃에서 1000Å∼3000Å의 두께로 전면증착한다.Subsequently, doping silicon or polysilicon is deposited on the entire surface of the bit line wiring 26 including the sidewall spacers 31 as a second plug polysilicon at a thickness of 1000 Pa to 3000 Pa at 400 ° C to 1200 ° C.
이어 라인형 마스크를 이용하여 상기 워드라인절연막(24)이 드러날때까지 상기 제 2 플러그용 폴리실리콘을 식각하여 폴리실리콘 플러그패턴(32)을 형성할 때, 상기 비트라인배선(26)의 마스크산화막(30)이 500Å만큼 국부적으로 손실된다.Subsequently, when the polysilicon plug pattern 32 is formed by etching the second plug polysilicon until the word line insulating layer 24 is exposed using a line mask, a mask oxide layer of the bit line wiring 26 is formed. (30) is lost locally by 500 ms.
이어 상기 폴리실리콘 플러그패턴(32)을 포함한 전면에 비트라인절연막(33)으로서 BPSG(Boro Phospho Silicate Glass), PSG(Phosphorous Silicate Glass), FSG(Fluorine Silicate Glass), PETEOS(Plasma Enhanced Tetra Etyl Ortho Silicate), PE-SiH4, HDP USG(High Density Plasma Undoped Silicon Glass), HDP PSG 또는 APL(Advanced Planarization Layer) 산화막 중 어느 하나의 절연막을 3000Å∼10000Å두께로 증착한다. 이어 상기 비트라인절연막(33)을 300℃∼1000℃에서 열처리한다.Subsequently, as a bit line insulating layer 33 on the front surface including the polysilicon plug pattern 32, Boho Phospho Silicate Glass (BPSG), Phosphorous Silicate Glass (PSG), Fluorine Silicate Glass (FSG), and Plasma Enhanced Tetra Etyl Ortho Silicate (PETOS) ), An insulating film of any one of PE-SiH 4 , HDP USG (High Density Plasma Undoped Silicon Glass), HDP PSG, or APL (Advanced Planarization Layer) oxide film is deposited to a thickness of 3000 kPa to 10,000 kPa. Subsequently, the bit line insulating layer 33 is heat treated at 300 ° C to 1000 ° C.
도 3b에 도시된 바와 같이, 상기 폴리실리콘 플러그패턴(32)이 드러날때까지 상기 비트라인절연막(33)을 화학적기계적연마하여 상기 폴리실리콘 플러그패턴(32)를 분리시키는데, 이 때, 상기 비트라인절연막(33)에 대한 연마속도는 빠르면서 상기 폴리실리콘 플러그패턴(32)에 대한 연마속도는 느린 즉, 폴리실리콘에 대한 선택비가 100이상인 pH 5∼8로 유지되는 세리아계 산화막용 슬러리를 이용하여 상기 폴리실리콘 플러그패턴(32)을 연마정지막으로 하여 화학적기계적연마한다. 여기서, 미설명도면부호 33a는 연마된 비트라인절연막이다.As shown in FIG. 3B, the polysilicon plug pattern 32 is separated by chemical mechanical polishing of the bit line insulating layer 33 until the polysilicon plug pattern 32 is exposed. The polishing rate for the insulating film 33 is high, but the polishing rate for the polysilicon plug pattern 32 is slow, that is, using a slurry for ceria oxide film maintained at pH 5 to 8 having a selectivity to polysilicon of 100 or more. The polysilicon plug pattern 32 is subjected to chemical mechanical polishing using an abrasive stop film. Here, the non-explained reference numeral 33a is a polished bit line insulating film.
도 3c에 도시된 바와 같이, 희석된 HF와 같은 습식 산화막 식각제 또는 CF4+CHF3, C2F6, C3F8과 같은 플루오린(Fluorine)계 건식 산화막식각제를 이용하여 상기 비트라인배선(26)이 드러날때까지 전면식각한 다음, CClF3+Cl3, CHCl3+Cl2, SF6, NF3, CCl4, CF4+H2, C2ClF5와 같은 클로라인(Chlorine) 및 플루오린계 건식 폴리실리콘 식각제를 이용하여 폴리실리콘 플러그패턴(32)을 후속 확산방지금속막이 플러그내 1500Å정도 채워지도록 리세스(Recess)시킨다(32a). 여기서, 미설명 도면부호 33b는 연마된 비트라인절연막을 나타낸다.As shown in FIG. 3C, the bit may be prepared using a wet oxide etchant such as diluted HF or a fluorine-based dry oxide etchant such as CF 4 + CHF 3 , C 2 F 6 , or C 3 F 8. Full etch until the line wiring 26 is exposed, and then chlorine such as CClF 3 + Cl 3 , CHCl 3 + Cl 2 , SF 6 , NF 3 , CCl 4 , CF 4 + H 2 , C 2 ClF 5 Chlorine) and a fluorine-based dry polysilicon etchant are used to recess the polysilicon plug pattern 32 such that the subsequent diffusion barrier metal film is filled to about 1500 mm in the plug (32a). Here, the unexplained reference numeral 33b denotes a polished bit line insulating film.
도 3d에 도시된 바와 같이, 상기 리세스된 폴리실리콘 플러그패턴(32a)상에 확산방지금속막(34)으로서 Ti, TiN, TiSi, WN, TaN, TiSiN 또는 TiAlN 중 어느 하나의 도전층을 화학적기상증착법(Chemical Vapor Deposition; CVD) 또는 스퍼터링 (Sputtering)법을 이용하여 300℃∼600℃에서 100Å∼1000Å두께로 증착하거나, 또는 상기 금속막들을 조합하여 증착한다.As shown in FIG. 3D, a conductive layer of any one of Ti, TiN, TiSi, WN, TaN, TiSiN, or TiAlN is chemically deposited as the diffusion barrier metal film 34 on the recessed polysilicon plug pattern 32a. The deposition is performed at 300 to 600 DEG C at 300 DEG C to 600 DEG C by chemical vapor deposition (CVD) or sputtering, or a combination of the metal films.
이어 pH 2∼5로 유지되는 알루미나, 실리카 또는 세리아계 금속막용 슬러리를 이용하여 상기 확산방지금속막(34)을 화학적기계적연마하면, 상기 비트라인배선의 마스크산화막(30)이 손실되지 않고 잔류하여 안정된 제 2 콘택플러그로서, 폴리실리콘 플러그패턴(32a)과 확산방지금속막(34)의 적층구조로 이루어지는 금속 콘택플러그를 형성할 수 있다.Subsequently, when the diffusion barrier metal film 34 is chemically mechanically polished using a slurry for alumina, silica or ceria-based metal film maintained at pH 2 to 5, the mask oxide film 30 of the bit line wiring is not lost. As the stable second contact plug, a metal contact plug having a laminated structure of the polysilicon plug pattern 32a and the diffusion barrier metal film 34 can be formed.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 콘택플러그 형성 방법은 폴리실리콘에 대한 연마선택비가 큰 세리아계 산화막용 슬러리와 산화막 및 폴리실리콘의 전면식각공정을 이용하므로써 캐패시터전극 하부의 플러그형성시 발생하는 비트라인배선의 마스크산화막의 손실로 인한 비트라인과 캐패시터간 브릿지 형성을 방지하여 누설전류를 감소시킬 수 있는 효과가 있다.As described above, the method for forming a contact plug according to the present invention uses a slurry for ceria-based oxides having a high polishing selectivity for polysilicon, and an entire surface etching process of the oxide film and polysilicon. The leakage current can be reduced by preventing bridge formation between the bit line and the capacitor due to the loss of the mask oxide film.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000036778A KR20020002569A (en) | 2000-06-30 | 2000-06-30 | Method for forming contact plug in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000036778A KR20020002569A (en) | 2000-06-30 | 2000-06-30 | Method for forming contact plug in semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR20020002569A true KR20020002569A (en) | 2002-01-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000036778A KR20020002569A (en) | 2000-06-30 | 2000-06-30 | Method for forming contact plug in semiconductor device |
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| Country | Link |
|---|---|
| KR (1) | KR20020002569A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7999763B2 (en) | 2006-01-13 | 2011-08-16 | Lg Electronics Inc. | Plasma display apparatus |
-
2000
- 2000-06-30 KR KR1020000036778A patent/KR20020002569A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7999763B2 (en) | 2006-01-13 | 2011-08-16 | Lg Electronics Inc. | Plasma display apparatus |
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