KR20020002065A - Method for manufacturing a pmos transistor - Google Patents
Method for manufacturing a pmos transistor Download PDFInfo
- Publication number
- KR20020002065A KR20020002065A KR1020000036502A KR20000036502A KR20020002065A KR 20020002065 A KR20020002065 A KR 20020002065A KR 1020000036502 A KR1020000036502 A KR 1020000036502A KR 20000036502 A KR20000036502 A KR 20000036502A KR 20020002065 A KR20020002065 A KR 20020002065A
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- South Korea
- Prior art keywords
- ions
- junction region
- implanted
- plug
- semiconductor substrate
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 150000002500 ions Chemical class 0.000 claims abstract description 54
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 230000007547 defect Effects 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 6
- -1 BF2 ions Chemical class 0.000 abstract 1
- 239000007943 implant Substances 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 8
- 239000012535 impurity Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 230000005465 channeling Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
Abstract
Description
본 발명은 피모스(PMOS, 이하, P모스 ) 트랜지스터의 제조방법에 관한 것으로, 보다 구체적으로는 P모스 트랜지스터의 콘택홀 형성후, 접합 영역에 플러그 이온을 주입하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a PMOS transistor (hereinafter referred to as a PMOS transistor), and more particularly, to a method of implanting plug ions into a junction region after forming a contact hole of a PMOS transistor.
도 1은 종래의 P모스 트랜지스터의 플러그 이온 주입 방법을 설명하기 위한 도면이다.1 is a view for explaining a plug ion implantation method of a conventional P-MOS transistor.
도 1을 참조하여, 반도체 기판(1) 상부의 적소에 필드 산화막(2)을 형성한다. 반도체 기판(1)의 소정 부분에 게이트 절연막(3)을 포함하는 게이트 전극(4)을 공지의 방법으로 형성한다. 이어서, 게이트 전극(4)의 양측벽에 절연막으로 스페이서(5)를 형성한다. 스페이서(5) 외측의 반도체 기판(1)에 P타입 불순물, 예를들어, BF2이온 또는 B 이온을 주입하여 접합 영역(6)을 형성한다. 그후, 반도체 기판(1) 결과물 상부에 층간 절연막(7)을 증착한다음, 접합 영역(6)이 노출되도록 층간 절연막(7)의 소정 부분을 건식 식각하여, 콘택홀(h)을 형성한다. 이때, 콘택홀(h)을 형성하기 위한 식각 공정시, 접합 영역(5)의 표면이 일부 손실된다. 종래에는 이를 보상하기 위하여, 접합 영역(5)과 같은 타입의 불순물, 예를들어, BF2이온 또는 B 이온을 선택적으로 주입하였다. 이와같이 손상된 접합 영역에 불순물을 주입하는 것을 플러그 이온 주입이라고 한다.Referring to FIG. 1, a field oxide film 2 is formed in place on the semiconductor substrate 1. A gate electrode 4 including the gate insulating film 3 is formed in a predetermined portion of the semiconductor substrate 1 by a known method. Subsequently, spacers 5 are formed with insulating films on both side walls of the gate electrode 4. P-type impurities such as BF 2 ions or B ions are implanted into the semiconductor substrate 1 outside the spacer 5 to form the junction region 6. Thereafter, the interlayer insulating film 7 is deposited on the resultant of the semiconductor substrate 1, and then a predetermined portion of the interlayer insulating film 7 is dry-etched to expose the junction region 6, thereby forming a contact hole h. At this time, during the etching process for forming the contact hole h, the surface of the junction region 5 is partially lost. Conventionally, to compensate for this, impurities of the same type as the junction region 5, for example, BF 2 ions or B ions are selectively implanted. Injecting impurities into the damaged junction region is called plug ion implantation.
그러나, P모스 트랜지스터에서 플러그 이온으로 BF2이온을 주입하게 되면, F 이온이 B 이온의 과도 확산을 차단시켜주기는 하나, F 이온이 반도체 기판의 격자 결함을 일으킨다. 이러한 기판의 격자 결함은 950℃ 이상의 고온 열공정을 진행하여야만 치유가 가능하다.However, when BF 2 ions are implanted into the plug ions in the PMOS transistor, the F ions block the excessive diffusion of the B ions, but the F ions cause lattice defects of the semiconductor substrate. The lattice defects of such substrates can be cured only after the high temperature thermal process of 950 ° C or higher.
또한, 플러그 이온으로 B 이온을 주입하면, B 이온이 작은 질량을 가지므로, 이온 주입시 반도체 기판의 격자 사이를 관통(채널링 현상)하거나 과도 확산이 발생된다.In addition, when B ions are implanted into the plug ions, the B ions have a small mass, so that during the ion implantation, penetration (channeling phenomenon) or excessive diffusion occurs between the lattice of the semiconductor substrate.
따라서, 본 발명의 목적은 상기한 종래의 문제점을 해결하기 위한 것으로, 격자 결함 및 과도 확산없이 플러그 이온을 용이하게 주입할 수 있는 P모스 트랜지스터의 제조방법을 제공하는 것이다.Accordingly, an object of the present invention is to solve the above-mentioned conventional problems, and to provide a method of manufacturing a PMOS transistor that can easily inject plug ions without lattice defects and excessive diffusion.
도 1은 종래의 P모스 트랜지스터의 플러그 이온 주입 방법을 설명하기 위한 도면.1 is a view for explaining a plug ion implantation method of a conventional P-MOS transistor.
도 2a 내지 도 2d는 본 발명에 따른 P모스 트랜지스터의 플러그 이온 주입 방법을 설명하기 위한 각 공정별 단면도.2A to 2D are cross-sectional views of respective processes for explaining a plug ion implantation method of a PMOS transistor according to the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 - 반도체 기판 12 - 필드 산화막11-semiconductor substrate 12-field oxide film
13 - 게이트 절연막 14 - 게이트 전극13-gate insulating film 14-gate electrode
15 - 스페이서 16 - 접합 영역15-spacer 16-junction area
17 - 층간 절연막 18 - 포토레지스트 패턴17-interlayer insulating film 18-photoresist pattern
19 - 금속 배선19-metal wiring
상기한 본 발명의 목적을 달성하기 위하여, 본 발명은, P형의 접합 영역을 갖는 반도체 기판을 제공하는 단계; 상기 반도체 기판상에 P형의 접합 영역을 노출시키는 콘택홀을 갖는 층간 절연막을 형성하는 단계; 상기 노출된 P형의 접합 영역에 손상을 방지하기 위하여, BF2플러그 이온을 주입하는 단계; 및 상기 BF2플러그 이온이 주입된 접합 영역에 B11 플러그 이온을 주입하는 단계를 포함한다.In order to achieve the above object of the present invention, the present invention comprises the steps of providing a semiconductor substrate having a P-type junction region; Forming an interlayer insulating film having a contact hole exposing a P-type junction region on the semiconductor substrate; Implanting BF 2 plug ions to prevent damage to the exposed P-type junction regions; And implanting B11 plug ions into the junction region into which the BF 2 plug ions are implanted.
여기서, BF2이온은 1.0×1015내지 2.0×1015ion/㎠의 농도로 주입하는 것을 특징으로 한다. 또한, BF2이온은 접합 영역의 최저 깊이 또는 그 이하의 깊이로 주입하는 것을 특징으로 한다.Here, the BF 2 ions are characterized by being injected at a concentration of 1.0 × 10 15 to 2.0 × 10 15 ions / cm 2. In addition, BF 2 ions are characterized in that the implantation to the depth of the minimum or less than the junction region.
(실시예)(Example)
이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 도 2a 내지 도 2d는 본 발명에 따른 P모스 트랜지스터의 플러그이온 주입 방법을 설명하기 위한 각 공정별 단면도이다.2A to 2D are cross-sectional views of respective processes for explaining a plug ion implantation method of a PMOS transistor according to the present invention.
먼저 도 2a를 참조하여, 반도체 기판(11) 상부의 적소에 필드 산화막(12)을 형성한다. 반도체 기판(11)의 소정 부분에 게이트 절연막(13)을 포함하는 게이트 전극(14)을 공지의 방법으로 형성한다. 이어서, 반도체 기판(11) 상부에 절연층을 증착한다음, 비등방성 블랭킷 식각을 진행하여, 게이트 전극(14)의 양측벽에 스페이서(5)를 형성한다. 그 다음, 스페이서(15) 외측의 반도체 기판(11)에 P타입 불순물, 예를들어, BF2이온 또는 B 이온을 주입하여 접합 영역(16)을 형성한다. 그후, 반도체 기판(11) 결과물 상부에 층간 절연막(17)을 증착한다음, 접합 영역(16)을 노출시키기 위한 콘택용 포토레지스트 패턴(18)을 층간 절연막(17) 상부에 공지의 포토리소그라피 방식에 의하여 형성한다. 그후, 포토레지스트 패턴(18)을 마스크로 이용하여, 층간 절연막(17)을 건식 식각하여, 콘택홀(H)을 형성한다. 이때, 콘택홀(H)을 형성하기 위한 식각 공정으로, 접합 영역(16)의 표면은 소정 부분 손상될 수 있다.First, referring to FIG. 2A, a field oxide film 12 is formed in place on the semiconductor substrate 11. The gate electrode 14 including the gate insulating film 13 is formed in a predetermined portion of the semiconductor substrate 11 by a known method. Subsequently, an insulating layer is deposited on the semiconductor substrate 11, and then anisotropic blanket etching is performed to form spacers 5 on both sidewalls of the gate electrode 14. Next, P-type impurities such as BF 2 ions or B ions are implanted into the semiconductor substrate 11 outside the spacer 15 to form the junction region 16. Thereafter, an interlayer insulating film 17 is deposited on the semiconductor substrate 11 resultant, and then a contact photoresist pattern 18 for exposing the junction region 16 is formed on the interlayer insulating film 17. Form by Thereafter, using the photoresist pattern 18 as a mask, the interlayer insulating film 17 is dry etched to form the contact hole H. In this case, as an etching process for forming the contact hole H, the surface of the junction region 16 may be damaged at a predetermined portion.
다음, 도 2b에 도시된 바와 같이, 접합 영역(16)의 손상 부위를 치유하기 위하여, 접합 영역(16)에 1차적으로 BF2이온을 1.0×1015내지 2.0×1015ion/㎠의 농도로 이온 주입하여, 접합 영역의 표면을 비정질화 한다. 이때, BF2이온은 접합 영역의 최저 깊이(Rp:projected range) 정도 또는 그 이하의 깊이로 주입함이 바람직하다. 아울러, BF2이온은 플러그 이온 주입될 양보다 소정치 보다 작은 양으로 주입한다. 이에따라, F 이온들이 정하여진량보다 적게 이온 주입되므로, 격자 결함을 유발할 확률이 적다.Next, as shown in FIG. 2B, in order to cure the damage site of the junction region 16, the concentration of BF 2 ions in the junction region 16 is 1.0 × 10 15 to 2.0 × 10 15 ion / cm 2. By ion implantation, the surface of the junction region is amorphous. In this case, the BF 2 ions are preferably implanted at a depth of about or below the minimum depth (Rp: projected range) of the junction region. In addition, BF 2 ions are implanted in an amount smaller than a predetermined value than the amount to be plug ion implanted. Accordingly, since the F ions are ion implanted in less than the determined amount, there is less chance of causing lattice defects.
그리고나서, 도 2c에 도시된 바와 같이, 다시 접합 영역(16)에 2차적으로 B11 이온을 주입한다. 이때, B11 이온은 정하여진 플러그 이온량에 나머지량만큼 주입한다. 아울러, 1차적으로 BF2이온이 주입되어 있는 상태이므로, BF2의 F 이온이 B11 이온의 과도 확산을 방지한다.Then, as shown in FIG. 2C, B11 ions are secondarily implanted into the junction region 16 again. At this time, B11 ions are implanted in the amount of plug ions determined by the remaining amount. In addition, since BF 2 ions are first implanted, F ions of BF 2 prevent excessive diffusion of B11 ions.
그후, 도 2d에 도시된 것과 같이, 포토레지스트 패턴(18)을 예를들어, 플라즈마 에슁 방법으로 제거한다. 이어서, 노출된 접합 영역(16)과 콘택되도록 금속 배선(19)을 형성한다.Thereafter, as shown in FIG. 2D, the photoresist pattern 18 is removed by, for example, a plasma etching method. Subsequently, the metal wiring 19 is formed to contact the exposed junction region 16.
이상에서 자세히 설명한 바와 같이, 본 발명에 의하면, P모스 트랜지스터의 플러그 이온 주입 공정시, 1차적으로 BF2이온을 적정량 주입한다음, B11 이온을 2차적으로 주입한다. 이에따라, BF2이온만이 주입될 때보다 F 이온의 양이 감소되어, 격자 결함을 감소시킬 수 있다. 아울러, B11 이온은 먼저 주입된 BF2이온의 F 이온에 의하여 과도 확산 및 채널링이 방지된다. 따라서, 격자 결함 및 과도 확산 없이 플러그 이온을 용이하게 주입할 수 있다.As described in detail above, according to the present invention, during the plug ion implantation process of the P-MOS transistor, an appropriate amount of BF 2 ions is firstly implanted, followed by B11 ions. Accordingly, the amount of F ions is reduced than when only BF 2 ions are implanted, thereby reducing lattice defects. In addition, B11 ions are prevented from overdiffusion and channeling by F ions of BF 2 ions implanted first. Therefore, plug ions can be easily implanted without lattice defects and excessive diffusion.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000036502A KR20020002065A (en) | 2000-06-29 | 2000-06-29 | Method for manufacturing a pmos transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000036502A KR20020002065A (en) | 2000-06-29 | 2000-06-29 | Method for manufacturing a pmos transistor |
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| KR20020002065A true KR20020002065A (en) | 2002-01-09 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011125036A1 (en) | 2010-04-06 | 2011-10-13 | Faculdade De Ciências E Tecnologia Da Universidade Nova De Lisboa | P-type oxide alloys based on copper oxides, tin oxides, tin-copper alloy oxides and metal alloy thereof, and nickel oxide, with embedded metals thereof, fabrication process and use thereof |
-
2000
- 2000-06-29 KR KR1020000036502A patent/KR20020002065A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011125036A1 (en) | 2010-04-06 | 2011-10-13 | Faculdade De Ciências E Tecnologia Da Universidade Nova De Lisboa | P-type oxide alloys based on copper oxides, tin oxides, tin-copper alloy oxides and metal alloy thereof, and nickel oxide, with embedded metals thereof, fabrication process and use thereof |
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