KR200177260Y1 - Semiconductor memory device - Google Patents

Abstract

The semiconductor memory device of the present invention comprises a logic gate portion for inverting and logically inverting data, and two pairs of NMOS and PMOS transistors each having an output of the logic gate portion and connected to each data line at one contact point. And an inversion unit for double inverting the contact signal of each data line, and a signal of the contact portion with the data line is applied to the gate after a predetermined time delay through the inversion unit, and the pair of NMOS transistors and the ground voltage It is configured to include an EMOS transistor connected between, and when the data transitions from low to high feedback by delaying for a certain time to prevent the DC current flows to reduce the current consumption.

Description

Semiconductor memory device

1 is a write drive circuit diagram of a conventional semiconductor memory device.

2 is a write drive circuit diagram of a semiconductor memory device according to the present invention.

* Explanation of symbols for main parts of the drawings

10: logic circuit 20: inverting unit

The present invention relates to a semiconductor memory device. In particular, when a signal of a write data line falls to a low level in an SRAM, a write driver is operated to minimize the power and increase the speed. A semiconductor memory device is provided.

In the conventional SRAM, as shown in FIG. 1, an NMOS transistor MN3 having a source connected to a drain of the lead transistor ML1 and a gate connected to a word line WL, and a drain grounded and small Is connected to a power supply voltage and is connected to the drain of the NMOS transistor MN3, and the source is connected to the source of the NMOS transistor MN2 and the gate of the NMOS transistor MN6. An NMOS transistor MN5 connected to a gate line and a word line WL, a source is grounded, and a drain is connected to a power supply voltage, and an NMOS transistor MN7 connected to a source of the NMOS transistor MN5. The NMOS transistor MN3 for applying the equalizing signal EQ by sharing two data lines with the memory cell, and a power supply voltage are applied to the source and the gate. Yen connected to each data line of the MOS transistor (ML1, ML2) and the blood to which the data (DATA) to the gate MOS, NMOS pair (MP1, MN1) and the data to the gate ( ) Is applied to other PMOS and NMOS pairs MP2 and MN2, and the write operation is as follows.

First, each data (DATA, ) Is applied high and low, the NMOS transistor MN1 and the PMOS transistor MP2 are turned on, and the PMOS transistor MP1 and the NMOS transistor MN2 are turned off. turn off) and WDB is discharged low, Is charged high. At this time, a DC path is formed from the NMOS transistor ML1 to the NMOS transistor ML1 through the WDB so that a current flows. The conventional semiconductor memory device includes the PMOS transistor MP1. ) And the NMOS transistor MN1 having a large size or a multi bit, there is a problem that the current flowing in the DC path is also increased and becomes larger as the multi bit is increased.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of blocking the DC path by feeding back data when the data transitions from low to high in order to solve the above problems.

The semiconductor memory device of the present invention for achieving the above object comprises a logic gate portion for inverting and logically combining data, and two pairs of outputs of the logic gate portion as inputs, each data line and each connected at one contact point. NMOS and PMOS transistors, an inverter for double inverting the contact signal of each fraudulent data line, and a signal of the contact portion with the data line are applied to the gate after a predetermined time delay through the inverter, and each pair The NMOS transistor is connected between the ground voltage and the NMOS transistor.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

In the semiconductor memory device of the present invention, as shown in FIG. 2, the NMOS transistors MN3, MN4, MN5, and MN6 are connected between the word line WL and the data line as in the conventional art. In addition, the write drive includes an inverter I1 for inverting data DATA in each data line, and a NOR gate NOR1 for inputting a signal of the inverter I1 and a chip select signal CiEB signal. The output of the logic gate 10 is a gate input, the power supply voltage is connected to the drain, the source voltage is connected to the drain of the NMOS transistors MN11 and MN13, and the source of the NMOS transistors MN1 and MN13 is connected to the source. The drain is connected and the connection point is connected between the PMOS transistors MP11 and MP12 connected to the data line D at one contact point and between the source and the ground voltage of the NMOS transistors MN11 and MN13 and two half Electricity (I2 (I2 '), I3 (I3')) The NMOS transistors MN12 and MN14, which receive the input signal by delaying a contact signal with the data line for a predetermined time, are connected through the inverting unit 20, and only one of the data lines is operated, for example, when writing low data. This is as follows.

First, when data transitions from low to high, the data line D is already precharged to Vcc-V _TN . At this time, since the output of the inverter 20 is high, the NMOS transistor MN12 It is turned on and discharged to ground through the NMOS transistors MN11 and MN12.

When the data line D is sufficiently low, the output of the inverter becomes low after a slight delay time, and the NMOS transistor MN12 is turned off to prevent direct current flowing through the data line D. Accordingly, in the case of the memory cell, the latch can retain the data without continuing writing. When the write operation is completed, the chip select (CiEB) becomes high and the data line (D, ) Is precharged high.

As in the present invention, according to the present invention, when the data transitions from low to high, the feedback is delayed for a predetermined time, thereby preventing the DC current from flowing and reducing the current consumption.

Claims (1)

A logic gate portion for inverting and logically inverting data, an output of the logic gate portion, two pairs of NMOS and PMOS transistors each connected to each data line and one contact point, and a contact point of each data line An inverting unit for double inverting a signal and a signal of a contact unit with the data line are applied to the gate after a predetermined time delay through the inverting unit, and are connected between the pair of NMOS transistors and a ground voltage to provide an NMOS transistor. A semiconductor memory device comprising a.