KR200211232Y1 - Pull-down transistor driver for data output buffer - Google Patents

Abstract

The present invention relates to a pull-down transistor driving device of a data output buffer, and in particular, a pull-down transistor of a data output buffer which reduces power consumption by making it suitable to prevent current flowing to a pull-down transistor in an 'off' state by ground bouncing. It relates to a drive device.

However, the current trend of DRAM is gradually moving toward byte-wide deployment, and the 16-bit market is largely formed in the case of 16-megabyte (16MDRAM). Will also appear. However, the conventional transistor driving device of the data output buffer drives the pull-down transistor by using three inverters connected in series, so that the bouncing by the output becomes larger and the power of the control circuit and the output stage pull-up and pull-down transistor are separated. When the voltage state of the MOS transistor 'off' level is set to the reference voltage (Vss) level, the amount of current flowing from the output (DQ) to the reference voltage point (Vss) also increases relatively, which causes a problem in that power consumption increases.

However, in the present invention, the driving device of the transistor is designed to reduce power consumption by cutting off the current flowing from the output (DQ) to the reference voltage point (Vss) by using a back bias voltage level shifter.

Description

Pull-down transistor driver for data output buffer

1 is a block diagram of a conventional data output buffer.

2 is a detailed view of the peak level shifter of FIG.

3 is a detailed view of the transistor driver of FIG.

4 is a pull-down transistor driving device of a data output buffer of the present invention.

5 is a timing diagram of a data output buffer operation to which a pull-down transistor driving device of the present invention is applied.

* Explanation of symbols for main parts of the drawings

100: flip-flop portion 110: peak value level shifter portion

210: level shift unit 210a: inverter unit

The present invention relates to a pull-down transistor driving device of a data output buffer, and in particular, a pull-down transistor of a data output buffer which reduces power consumption by making it suitable to prevent current flowing to a pull-down transistor in an 'off' state by ground bouncing. It relates to a drive device.

As shown in FIG. 1, the data output buffer to which the conventional pull-down transistor driver is applied outputs the signals Q and Q using the output buffer enable signal OECEB and the data line pair DQINB and DQIN as inputs, respectively. A peak level shifter for receiving the signal Q from the output terminal of the flip-flop unit 100 to increase the drop and speed of the flip-flop unit 100 and the threshold voltage V _T of the pull-up transistor. The unit 110, an NMOS transistor MN11 that receives the output from the peak level shifter 110 as a gate, and a pull-down having a large load receiving the signal Q output from the flip-flop unit 100. A transistor driver 120 for driving the transistor and an NMOS transistor MN12 for driving the output from the transistor driver 120 as a gate.

The peak level shifter 110 driving the pull-up transistor MN11 includes an MOS transistor MN21 'on' and 'off' according to an input signal IN, as shown in FIG. Inverter INV21 for inverting and outputting the signal of the input signal IN, the NMOS transistor MN22 which receives the output from the inverter INV21 as a gate, and the drain and blood of the NMOS transistor MN22. A gate of the MOS transistor MP22 is connected, and a drain of the NMOS transistor MN21 is connected to a source terminal of the PMOS transistor MP21, and a drain of the NMOS transistor MN22 is connected to the NMOS transistor MP21. An inverter unit 110a connected to a gate and a source of the MP22, respectively, and having a drain of the NMOS transistor MN22 and a source of the PMOS transistor MP22 combined to form a PMOS transistor MP23 and an NMOS transistor MN23. Enter The inverter unit 110a receives a signal and outputs the output OUT.

In addition, as illustrated in FIG. 3, the transistor driver 120 sequentially drives three inverters INV I1, INV I2, and INV I3 in series to drive a pull-down transistor MN12 having a large loading.

The operation of the conventional data output buffer configured as described above is as follows.

The conventional operation of the data output buffer is divided into two cases of reading the output data 'high' and reading 'low'.

First, a case of reading 'high' will be described as a case in which the input signal DQIN is 'high' and the input signal DQIB is 'low'. 'Low' and 'high' are inputted to the input terminal of the), and 'low' is outputted. These outputs are respectively input to the NAND gates NAND11 and NAND12 so that the outputs Q and Q of the flip-flop unit 100 both output high.

In addition, the peak level shifter 110 outputs a 'low' level voltage by inputting the signal of the output Q, and the transistor driver 120 outputs the signal of the output Q of the flip-flop unit 100. Outputs a 'low' level signal. At this time, since the output of the peak level shifter 110 and the transistor driver 120 is at a 'low' level, the NMOS transistors MN11 and MN12 are 'off' so that the output DQ is in a 'high impedance' state. .

When the read signal is performed and the enable signal OECEB becomes 'low', the signal passing through the flip-flop unit 100 and the peak level shifter 110 becomes 'high' and the flip-flop unit The signal passing through the transistor 100 and the transistor driver 120 becomes a low state, the NMOS transistor MN11 is turned on, the NMOS transistor MN12 is turned off, and the current is an NMOS transistor. It flows from the power supply voltage Vcc to the output DQ through MN11) and the state of the output DQ becomes a 'high' level voltage state.

In addition, in the case of reading 'low' data, the input signal DQIN is 'low' and the input signal DQINB is 'high'. When the enable signal is set to 'low', the NMOS transistor Only MN12 is 'on' so that current flows from the output DQ to the reference voltage point Vss so that the state of the output DQ becomes 'low', and the enable signal OECEB is 'high'. NMOS transistors (MN11 and MN12) are both 'off' and the output (DQ) is 'high impedance'.

Meanwhile, the operation of the peak level shifter 110 driving the pull-up transistor MN11 will be described in detail as follows.

If the input signal IN is 'high', the NMOS transistor MN21 is 'on', and the 'MOS' transistor MN22, to which the signal 'low' through the inverter INV21 is applied to the gate, is 'off', Only the PMOS transistor MP22 is turned 'on', and the voltage of the peak level voltage source Vpp is applied to the inverter unit 110a through the PMOS transistor MP23, so that the NMOS transistor MN23 of the inverter unit 110a is applied. By this 'on', the voltage level of the reference voltage (Vss) is output to the output (OUT).

In addition, when the input signal IN is 'low', the NMOS transistor MN22 is 'on', thereby causing the PMOS transistor MP21 to be turned on, and the 'low' level voltage of the reference voltage point Vss is increased. The NMOS transistor MN22 is applied to the inverter unit 110a. At this time, the PMOS transistor MP23 of the inverter unit 110a is turned on to output the voltage of the peak level Vpp.

For reference, this peak level Vpp is usually the sum of the power supply voltage Vcc and the threshold voltage 2V _T twice that of the transistor.

In addition, in the pull-down transistor driver 120 that drives the large-load pull-down transistor MN12, three inverters INVI1, INVI2, and INVI3 are connected in series to input an output Q signal from the flip-flop unit 100. The pull-down transistor MN12 is driven by outputting the signal inverted to the gate of the pull-down transistor MN12.

However, since the bouncing of the power supply voltage Vcc and the reference voltage Vss is large when the state of the output DQ in FIG. 1 changes, the pull-up and pull-down NMOS transistors MN11 and MN12 are separated from the control circuit. Let it be. In other words, the bounce by the output does not affect the control circuit.

However, the current trend of DRAM is gradually moving toward byte-wide development, and the 16-bit market is largely formed in the case of 16-mega-RAM, and 32-bit is increased as memory capacity increases. Will appear. As a result, bouncing by the output becomes larger, and the pull-up and pull-down of the control circuit and the output stage are separated, so that the power supply of the NMOS transistors (MN11 and MN12) is separated so that the voltage state of the 'off' level of the NMOS transistor (MN12) is referred to as the reference voltage point. In the case of (Vss) level, the amount of current flowing from the output (DQ) to the reference voltage point (Vss) also increases relatively, which causes a problem of increased power consumption.

Accordingly, the present invention aims at reducing power consumption by not generating a current path to be formed by bouncing when the pull-down transistor of the data output buffer is turned off. The present invention having this purpose will be described in detail with reference to the accompanying drawings. Is as follows.

4 is a pull-down transistor driving device of the data output buffer of the present invention, which is composed of a back-bias voltage level shifter, a level shift means for delivering an input signal consisting of an NMOS, PMOS transistor, and an inverter, and a transfer through the input means. And inverter means for inverting and outputting the set value.

In the level shifting means, the PMO transistors MP31 and MP32 receiving the input signal and the inverted input signal through the inverter INV31 and the drains of the PMOS transistor MP31 and MP32 are commonly connected. The gate is formed of an NMOS transistor MN31 and an MN32 to which drains of the PMOS transistors MP32 and MP31 are connected.

When described in detail with respect to the operation and effect of the present invention configured as described above.

When the input signal IN is 'high', the PMOS transistor MP31 is 'off', and the PMOS transistor MP32, which receives the low signal inverted through the inverter INV31 as the gate, is 'on', thereby supplying the power voltage. The external power supply voltage Vcc is applied to the inverter unit 220 so that the 'low' level voltage of the back bias voltage V _BB becomes 'EnMOS' as the NMOS transistor MN33 of the inverter unit 210a is 'on'. It is applied to the inverter unit 220 through the transistor MN32, and at this time, the PMOS transistor MP33 of the inverter unit 210a is 'on' so that the output OUT is outputted with the voltage of the power supply voltage Vcc level. do.

Therefore, when the 'low' voltage level is applied to the gate of the pull-down transistor MN12 of FIG. 1, that is, in the 'off' state, the voltage level of the internally generated voltage of FIG. 3 is equal to the back bias voltage V _BB level. do. For reference, this back bias voltage (V _BB ) is a value of about -1.5 to -2.5 volts.

As a result, in the case of reading a lot of 'low' data, the conventional data output buffer of FIG. 1 has a difference in the change of the reference voltage point Vss of the control circuit and the reference voltage point Vss connected to the pull-down transistor MN12. A current path is formed from DQ) to the reference voltage point Vss, and power consumption occurs as shown in FIG. 5A, but as in the present invention of FIG. 3, the back bias voltage V _BB level, that is, the negative voltage is negative. If the current state is 'off', since no current path is formed, a current flowing through the pull-down transistor MN12 may be prevented as shown in FIG. 5b.

As described in detail above, the present invention does not use the reference voltage point (Vss) voltage level when the pull-down transistor of the data output buffer is 'off', but uses the byte-wide (by the back bias voltage level shifter of FIG. 3). By increasing the number of outputs (DQ) to 16, 32 or more, it does not generate the current path to be formed by the ground bounce that will be increased, thereby reducing power consumption.

Claims (1)

An input means for outputting two mutually complementary output signals by a logical combination of an output buffer enable signal and a data input signal, and receiving a positive output signal of the input means and shifting the level of the positive output signal to pull up the data output buffer Driving a pull-down transistor of a data output buffer comprising a level shift means for outputting an output signal for controlling the transistor and an inverter means for outputting an output signal for controlling the pull-down transistor of the data output buffer by inverting the sub-output signal of the input means. In the apparatus, the level shifting means is applied to the gate and the input signal and the input signal inverted through the inverter, respectively, the first and second PMOS transistor to receive a power supply voltage to each source, and the first and second Each drain is connected to a drain of the PMOS transistor, and each gate is connected to the second and second gates. First and second NMOS transistors connected to the drains of the first PMOS transistors and receiving a back bias voltage from each source, and respective gates are connected to the drains of the second PMOS transistors, respectively, A pull-down transistor drive device for a data output buffer, comprising a third PMOS transistor and a third NMOS transistor connected in series between bias voltages and outputting an output signal at the connection point.