KR200156138Y1 - Ashing apparatus for semiconductor wafer - Google Patents
Ashing apparatus for semiconductor wafer Download PDFInfo
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- KR200156138Y1 KR200156138Y1 KR2019960019634U KR19960019634U KR200156138Y1 KR 200156138 Y1 KR200156138 Y1 KR 200156138Y1 KR 2019960019634 U KR2019960019634 U KR 2019960019634U KR 19960019634 U KR19960019634 U KR 19960019634U KR 200156138 Y1 KR200156138 Y1 KR 200156138Y1
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- Prior art keywords
- gas
- wafer
- semiconductor wafer
- ashing
- ashing apparatus
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- 238000004380 ashing Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000002347 injection Methods 0.000 claims abstract description 38
- 239000007924 injection Substances 0.000 claims abstract description 38
- 238000004080 punching Methods 0.000 claims description 12
- 239000010453 quartz Substances 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 230000006698 induction Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 238000005260 corrosion Methods 0.000 abstract description 3
- 230000007797 corrosion Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 고안은 반도체 웨이퍼 에싱(ASHING)장치에 관한 것으로, 종래에는 가스분사관의 내측에 대각선 방향으로 2개의 분사공이 형성되어 있어서 웨이퍼에 균일한 가스분사가 이루어지지 못하여 균일한 에싱이 되지 못하는 문제점이 있었다. 본 발명 반도체 웨이퍼 에싱장치는 가스분사관에 다수개의 분사공을 등간격으로 형성하여 에싱공정 진행시 균일하게 가스를 분사함으로서 균일한 에싱이 되는 효과가 있고, 따라서 알루미늄의 부식을 방지하는 효과가 있다.The present invention relates to a semiconductor wafer ashing apparatus, and conventionally, two injection holes are formed in the gas injection tube in a diagonal direction, so that uniform gas injection cannot be performed on the wafer, thereby preventing uniform ashing. there was. The semiconductor wafer ashing apparatus of the present invention has the effect of uniform ashing by forming a plurality of injection holes in the gas injection pipe at equal intervals and injecting the gas uniformly during the ashing process, thus preventing the corrosion of aluminum. .
Description
제1도는 종래 반도체 웨이퍼 에싱장치의 구성을 보인 종단면도.1 is a longitudinal sectional view showing the structure of a conventional semiconductor wafer ashing apparatus.
제2도는 종래 에싱장치의 펀칭메탈을 보인 평면도.2 is a plan view showing a punching metal of the conventional ashing apparatus.
제3도는 종래 에싱장치의 구성을 보인 평면도.3 is a plan view showing the configuration of a conventional ashing apparatus.
제4도는 본 고안의 요부인 가스분사관이 구비된 반도체 웨이퍼 에싱장치의 구성을 보인 종단면도.Figure 4 is a longitudinal sectional view showing the configuration of a semiconductor wafer ashing apparatus equipped with a gas injection pipe which is a main part of the present invention.
제5도는 본 고안 반도체 웨이퍼 에싱장치의 가스분사관을 보인 평면도.Figure 5 is a plan view showing a gas injection pipe of the semiconductor wafer ashing device of the present invention.
제6도는 제5도의 변형예를 보인 것으로,6 shows a modification of FIG.
(a)는 사시도.(a) is a perspective view.
(b)는 종단면도.(b) is a longitudinal cross-sectional view.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 도파관 11 : 쿼츠벨자10: waveguide 11: quartz bellza
12 : 펀칭메탈 13a : 분사공12: punching metal 13a: injection hole
13 : 가스분사관 14 : 스테이지13 gas injector 14 stage
20 : 가스유동관 W : 웨이퍼20: gas flow pipe W: wafer
본 고안은 반도체 웨이퍼 에싱장치에 관한 것으로, 특히 에싱공정 진행시 웨이퍼에 균일하게 가스가 공급되도록 하는데 적합한 반도체 웨이퍼 에싱장치에 관한 것이다.The present invention relates to a semiconductor wafer ashing apparatus, and more particularly, to a semiconductor wafer ashing apparatus suitable for supplying a uniform gas to the wafer during an ashing process.
일반적으로 반도체 웨이퍼 제조공정 중 에싱(ASHING)공정은 감광막(PHOTO RESIST)이 도포되어 있는 웨이퍼를 에칭(ETCHING)하고, 그 웨이퍼에 남아 있는 감광막을 제거하는 일명 피알 스트립(PHOTO RESIST STRIP)공정이라고 하는 공정을 말한다. 이와 같은 종래의 일반적인 에싱공정을 진행하는 에싱장치가 제1도에 도시되어 있는 바, 이를 간단히 설명하면 다음과 같다.In general, an ashing process in a semiconductor wafer manufacturing process involves etching a wafer on which a photoresist film is applied, and removing a photoresist film remaining on the wafer. Say fair. An ashing apparatus for performing such a conventional general ashing process is illustrated in FIG. 1, which will be briefly described as follows.
제1도는 종래 반도체 웨이퍼 에싱장치의 구성을 보인 개략구성도이고, 제2도는 종래 에싱장치의 펀칭메탈을 보인 평면도이며, 제3도는 종래 에싱장치의 가스분사관을 보인 평면도이다.1 is a schematic configuration diagram showing a conventional semiconductor wafer ashing apparatus, and FIG. 2 is a plan view showing a punching metal of a conventional ashing apparatus, and FIG. 3 is a plan view showing a gas injection pipe of a conventional ashing apparatus.
도시된 바와 같이, 종래의 에싱장치는 마이크로 웨이브가 통과하는 도파관(1)의 하부에 쿼츠벨자(QUARTZ BELLJAR)(2)가 설치되어 있고, 그 쿼츠벨자(QUARTZ BELLJAR)(2)의 하부에 이온을 걸러주기 위한 다수개의 관통공(3a)이 형성된 펀칭메탈(3)이 설치되어 있으며, 그 펀칭메탈(3)의 하부에는 대각선 방향에 2개의 분사공(4a)(4b)이 형성되어 웨이퍼(W)에 가스를 분사하기 위한 가스분사관(4)이 설치되어 있고, 그 가스분사관(4)의 하부에는 웨이퍼(W)가 얹혀지는 스테이지(5)가 설치되어 있다.As shown, the conventional ashing apparatus is provided with a quartz bell (2) in the lower portion of the waveguide (1) through which microwaves pass, and the ion in the lower part of the quartz bell (2). Punching metal (3) having a plurality of through holes (3a) for filtering the filter is provided, and two injection holes (4a) (4b) in a diagonal direction are formed in the lower portion of the punching metal (3) The gas injection pipe 4 for injecting gas is provided in W), and the stage 5 in which the wafer W is mounted is provided in the lower part of the gas injection pipe 4.
상기와 같이 구성되어 있는 종래 반도체 웨이퍼 에싱장치의 동작을 설명하면 다음과 같다.The operation of the conventional semiconductor wafer ashing apparatus configured as described above is as follows.
공정이 진행되면 도파관(1)과 쿼츠벨자(2)를 통하여 웨이퍼(W)의 상부로 마이크로 웨이브가 공급되고, 가스분사관(4)으로 가스가 공급되어 직경 1㎝가량의 분사공(4a)(4b)을 통하여 가스가 공급되면 상기 마이크로 웨이브와 가스에 의해 플라즈마가 발생되어 웨이퍼(W)의 상면에 잔류하는 포토레지스를 제거한다. 이때 상기 펀칭메탈(3)은 아래로 이동하는 이온을 걸러주게 된다.When the process proceeds, the microwave is supplied to the upper portion of the wafer W through the waveguide 1 and the quartz bell jar 2, and the gas is supplied to the gas injection tube 4, so that the injection hole 4a having a diameter of about 1 cm is provided. When gas is supplied through 4b, plasma is generated by the microwaves and the gas to remove the photoresist remaining on the upper surface of the wafer (W). In this case, the punching metal 3 filters ions moving downward.
그러나, 상기와 같은 종래 반도체 웨이퍼 에싱장치에서는 가스분사관(4)에 대각선 방향으로 2개의 분사공(4a)(4b)이 형성되어 있어서, 웨이퍼에 균일한 가스분사가 이루어지지 못하여 균일한 에싱이 이루어지지 못하는 문제점이 있었다. 이와 같이 균일한 에싱이 이루어지지 못할 경우에는 알루미늄의 측벽에 남아있는 잔류Cl-의 제거가 불량하게 되어 알루미늄에 부식을 발생시키는 원인이 된다.However, in the conventional semiconductor wafer ashing apparatus as described above, two injection holes 4a and 4b are formed in the gas injection pipe 4 in a diagonal direction, so that uniform gas injection is not performed on the wafer, so that uniform ashing is performed. There was a problem that could not be achieved. In this case, if the uniform ashing is not performed, the removal of residual Cl − remaining on the sidewall of aluminum becomes poor, which causes corrosion of the aluminum.
상기와 같은 문제점을 감안하여 안출한 본 고안의 목적은 웨이퍼의 상부에 균일하게 가스가 분사되도록 하는데 적합한 반도체 웨이퍼 에싱장치를 제공함에 있다.SUMMARY OF THE INVENTION An object of the present invention devised in view of the above problems is to provide a semiconductor wafer ashing apparatus suitable for uniformly injecting gas onto the wafer.
상기와 같은 본 고안의 목적을 달성하기 위하여 도파관의 하부에 쿼츠벨자가 설치되어 있고, 그 쿼츠벨자의 하측에 내부에 펀칭메탈이 설치되어 있으며, 그 펀칭메칼의 하측에 웨이퍼의 얹혀지는 스테이지가 설치되어 있고, 그 스테이지의 상면에 웨이퍼로 가스를 분사하기 위한 링형의 가스분사관이 설치되어 있는 반도체 웨이퍼 에싱장치에 있어서, 상기 가스분사관에는 웨이퍼의 상부에 가스를 분사하기 위한 다수개의 분사공이 등간격으로 형성되어 있는 것을 특징으로 하는 반도체 웨이퍼 에싱장치가 제공된다.In order to achieve the object of the present invention as described above, a quartz bell is installed in the lower part of the waveguide, a punching metal is installed in the lower side of the quartz bell, and a stage on which the wafer is placed below the punching knife is installed. A semiconductor wafer ashing apparatus having a ring-shaped gas injection tube for injecting gas into a wafer on an upper surface of the stage, wherein the gas injection tube includes a plurality of injection holes for injecting gas into the upper portion of the wafer. Provided is a semiconductor wafer ashing apparatus, which is formed at intervals.
이하, 상기와 같이 구성되는 본 고안 반도체 웨이퍼 에싱장치를 첨부된 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Hereinafter, with reference to an embodiment of the accompanying drawings, the subject innovation semiconductor wafer ashing device configured as described above in detail as follows.
제4도는 본 고안 반도체 웨이퍼 에싱장치의 구성을 보인 종단면도이고, 제5도는 본 고안 반도체 웨이퍼 에싱장치의 가스분사관을 보인 평면도이다.4 is a longitudinal sectional view showing the configuration of the semiconductor wafer ashing device of the present invention, and FIG. 5 is a plan view showing a gas injection pipe of the semiconductor wafer ashing device of the present invention.
도시된 바와 같이, 본 고안 반도체 웨이퍼 에싱장치는 도파관(10)의 하부에 쿼츠벨자(11)가 설치되고, 그 쿼츠벨자(11)의 하부에 펀칭메탈(12)이 설치되며, 그 펀칭메탈(12)의 하부에 링형(RING TYPE) 가스분사관(13)이 설치되고, 그 가스분사관(13)의 하부에 웨이퍼(W)가 얹혀지는 스테이지(14)가 설치되어 있는 구성은 종래와 동일하다.As shown in the drawing, the semiconductor wafer ashing device of the present invention is provided with a quartz bell 11 at the lower portion of the waveguide 10, a punching metal 12 is disposed at the lower portion of the quartz bell 11, and a punching metal ( The structure in which the ring type gas injection pipe 13 is provided in the lower part of 12, and the stage 14 on which the wafer W is placed on the lower part of the gas injection pipe 13 is provided. Do.
여기서, 본 고안은 상기 가스분사관(13)의 상면에 등간격으로 다수개의 분사공(13a)이 형성된 것을 특징으로 한다.Here, the present invention is characterized in that a plurality of injection holes (13a) is formed at equal intervals on the upper surface of the gas injection pipe (13).
상기 가스분사관(13)의 재질은 스테인레스로 하는 것이 바람직하며, 상기 분사공(13a)은 20mm간격으로 형성하고, 상기 분사공의 크기는 2mm로 하는 것이 바람직하다.It is preferable that the material of the gas injection pipe 13 is made of stainless, and the injection holes 13a are formed at intervals of 20 mm, and the size of the injection holes is preferably 2 mm.
상기와 같이 구성된 본 발명 가스분사관이 구비된 반도체 웨이퍼 에싱장치의 동작은 종래와 유사하다.The operation of the semiconductor wafer ashing apparatus provided with the gas injection pipe of the present invention configured as described above is similar to the conventional operation.
즉, 공정이 진행되면 도파관(10)과 쿼츠벨자(11)를 통하여 웨이퍼(W)의 상부로 마이크로 웨이브가 공급되고, 가스분사관(13)으로 가스가 공급되어 분사공(13a)을 통하여 가스가 분사되면 상기 마이크로 웨이브와 가스에 의해 플라즈마가 발생되어 웨이퍼(W)의 상면에 잔류하는 포토레지스를 제거하게 되는데, 이때 본 고안 가스분사관(13)에는 상방향으로 다수개의 분사공(13a)이 다수개 형성되어 있어서, 웨이퍼(W)의 상부로 가스를 균일하게 분사하게 되고 따라서 균일한 포토레지스트 제거가 이루어진다.That is, when the process proceeds, the microwave is supplied to the upper portion of the wafer W through the wave guide 10 and the quartz bell 11, and the gas is supplied to the gas injection pipe 13 to supply the gas through the injection hole 13a. When the plasma is injected by the microwave and the gas to remove the photoresist remaining on the upper surface of the wafer (W), the gas injection pipe 13 of the present invention a plurality of injection holes (13a) in the upward direction Since a plurality of these are formed, the gas is uniformly sprayed onto the wafer W, and thus uniform photoresist is removed.
제6도는 제5도의 변형예를 보인 것으로, (a)는 사시도이고, (b)는 종단면도이다.6 shows a modification of FIG. 5, (a) is a perspective view, and (b) is a longitudinal sectional view.
도시한 바와 같이, 상기 가스분사관(13)의 내측에 높이 30MM정도의 원통형 가스유도관(20)을 설치하여 가스가 가스유도관(20)을 따라 웨이퍼(W)의 상부에서 균일하게 공급되므로, 웨이퍼(W)의 외측과 내측에 균일한 에싱이 진행된다.As shown, since the cylindrical gas induction pipe 20 having a height of about 30MM is installed inside the gas injection pipe 13, the gas is uniformly supplied from the upper portion of the wafer W along the gas induction pipe 20. Uniform ashing proceeds to the outside and the inside of the wafer W. FIG.
상기 가스유도관(20)의 재질은 세라믹(CERIMIC)으로 하는 것이 바람직하다.The material of the gas induction pipe 20 is preferably made of ceramic (CERIMIC).
이상에서 상세히 설명한 바와 같이 본 발명 반도체 웨이퍼 에싱장치는 가스분사관에 다수개의 분사공을 등간격으로 형성하여 에싱공정 진행시 균일하게 가스를 분사함으로서 균일한 에싱이 되는 효과가 있고, 따라서 알루미늄의 부식을 방지하는 효과가 있다.As described in detail above, the semiconductor wafer ashing apparatus of the present invention has the effect of uniformly ashing by forming a plurality of injection holes in the gas injection pipe at equal intervals and injecting the gas uniformly during the ashing process, and thus corrosion of aluminum It is effective to prevent.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019960019634U KR200156138Y1 (en) | 1996-07-02 | 1996-07-02 | Ashing apparatus for semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019960019634U KR200156138Y1 (en) | 1996-07-02 | 1996-07-02 | Ashing apparatus for semiconductor wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR980009687U KR980009687U (en) | 1998-04-30 |
| KR200156138Y1 true KR200156138Y1 (en) | 1999-09-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019960019634U KR200156138Y1 (en) | 1996-07-02 | 1996-07-02 | Ashing apparatus for semiconductor wafer |
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| Country | Link |
|---|---|
| KR (1) | KR200156138Y1 (en) |
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1996
- 1996-07-02 KR KR2019960019634U patent/KR200156138Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR980009687U (en) | 1998-04-30 |
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