KR200183543Y1 - Etching device for semiconductor wafer - Google Patents
Etching device for semiconductor wafer Download PDFInfo
- Publication number
- KR200183543Y1 KR200183543Y1 KR2019970036101U KR19970036101U KR200183543Y1 KR 200183543 Y1 KR200183543 Y1 KR 200183543Y1 KR 2019970036101 U KR2019970036101 U KR 2019970036101U KR 19970036101 U KR19970036101 U KR 19970036101U KR 200183543 Y1 KR200183543 Y1 KR 200183543Y1
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- Prior art keywords
- semiconductor wafer
- wafer
- etching apparatus
- electrostatic chuck
- plasma
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
- H01J37/3211—Antennas, e.g. particular shapes of coils
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32532—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
Abstract
본 고안은 반도체 웨이퍼 식각장치에 관한 것으로, 종래에는 상부전극의 상부 중앙에 알 에프 안테나가 설치되어 있어서, 웨이퍼의 상부에 균일한 플라즈마가 형성되지 못하고, 따라서 웨이퍼의 중앙부와 에지부분의 식각차이가 발생되는 문제점이 있었다. 본 고안 반도체 웨이퍼 식각장치는 각각 알 에프 파워를 인가할 수 있도록 되어 있는 원형의 내,외측 알 에프 안테나(15)(15')를 설치하여, 웨이퍼(W)의 상부에 균일한 밀도의 플라즈마가 형성되도록 조절함으로서, 웨이퍼의 식각균일도를 향상시키게 되는 효과가 있다.The present invention relates to a semiconductor wafer etching apparatus, and in the related art, an RF antenna is installed in the upper center of the upper electrode, so that a uniform plasma cannot be formed on the upper portion of the wafer, so that the etching difference between the center portion and the edge portion of the wafer is different. There was a problem that occurred. The semiconductor wafer etching apparatus of the present invention is provided with circular inner and outer RF antennas 15 and 15 ', each of which is capable of applying RF power, so that a plasma having a uniform density is formed on top of the wafer W. By adjusting to form, there is an effect to improve the etching uniformity of the wafer.
Description
본 고안은 반도체 웨이퍼 식각장치에 관한 것으로, 특히 웨이퍼의 상부에 균일하게 플라즈마가 형성되도록 하는데 적합한 반도체 웨이퍼 식각장치에 관한 것이다.The present invention relates to a semiconductor wafer etching apparatus, and more particularly to a semiconductor wafer etching apparatus suitable for forming a plasma uniformly on top of the wafer.
반도체 웨이퍼 제조공정 중 현상 및 최종 베이크 공정을 마친 다음에는 식각공정을 실시하게 되는데, 이와 같은 식각공정을 실시하는 식각장비가 제1도에 도시되어 있는 바, 이를 간단히 설명하면 다음과 같다.After completion of development and final baking in the semiconductor wafer manufacturing process, an etching process is performed. An etching apparatus for performing such an etching process is illustrated in FIG. 1, which will be briefly described as follows.
제1도는 종래 반도체 웨이퍼 식각장치의 구성을 개략적으로 보인 종단면도이고, 제2도는 종래 반도체 웨이퍼 식각장치의 구성을 개략적으로 보인 평면도로서, 도시된 바와 같이, 공정 챔버(1)의 내측에는 웨이퍼(W)가 얹혀지는 정전척(2)이 설치되어 있고, 그 정전척(2)의 하부에는 하부전극(3)이 설치되어 있으며, 상기 정전척(2)의 상부에는 상부전극(4)이 설치되어 있고, 그 상부전극(4)의 상부 중앙에는 알 에프 안테나(5)가 설치되어 있다.FIG. 1 is a longitudinal cross-sectional view schematically showing a configuration of a conventional semiconductor wafer etching apparatus, and FIG. 2 is a plan view schematically showing a configuration of a conventional semiconductor wafer etching apparatus. As shown in FIG. An electrostatic chuck 2 on which W) is mounted is provided, and a lower electrode 3 is provided below the electrostatic chuck 2, and an upper electrode 4 is installed above the electrostatic chuck 2. An RF antenna 5 is provided in the upper center of the upper electrode 4.
그리고, 상기 알 에프 안테나(5)는 알 에프 파워를 인가할 수 있도록 연결되어 있고, 하부전극(3)은 알 에프 바이아스를 인가할 수 있도록 연결되어 있다.The RF antenna 5 is connected to apply RF power, and the lower electrode 3 is connected to apply RF vias.
도면중 미설명 부호 6은 가스주입구이고, 7은 가스배기구이다.In the figure, reference numeral 6 denotes a gas injection port, and 7 denotes a gas exhaust port.
상기와 같이 구성되어 있는 종래 반도체 웨이퍼 식각장비는 정전척(2)의 상면에 웨이퍼(W)를 얹어놓고 고정시킨 다음, 가스주입구(6)를 통하여 공정가스를 주입하여 상부전극(4)을 통하여 웨이퍼(W)의 상부에 분사되도록 한다. 이와 같이 챔버(1)의 내측에 공정가스가 주입되면 알 에프 안테나(5)를 통하여 상부전극(4)에 알 에프 파워를 인가하고, 하부전극(3)에 알 에프 바이아스를 인가하여 챔버(1)의 내측에 플라즈마를 형성시키고, 이와 같이 형성된 플라즈마에 의하여 웨이퍼(W)의 식각이 이루어진다.In the conventional semiconductor wafer etching apparatus configured as described above, the wafer W is placed and fixed on the upper surface of the electrostatic chuck 2, and then the process gas is injected through the gas inlet 6 through the upper electrode 4. It is to be injected on top of the wafer (W). As described above, when the process gas is injected into the chamber 1, the RF power is applied to the upper electrode 4 through the RF antenna 5, and the RF vias are applied to the lower electrode 3. Plasma is formed inside 1), and the wafer W is etched by the plasma thus formed.
그러나, 상기와 같이 구성되어 있는 종래 반도체 웨이퍼 식각장치는 상부전극(4)의 상부 중앙에 1개의 알 에프 안테나(5)가 설치되어 있어서, 상부전극(4)과 웨이퍼(W)의 사이에 형성되는 플라즈마의 밀도는 가장자리 보다는 중앙부가 높게 되고, 따라서 웨이퍼(W)의 가장자리 보다는 중앙부가 많이 식각되어 식각균일도를 향상시키는데 한계가 있는 문제점이 있었다.However, in the conventional semiconductor wafer etching apparatus constructed as described above, one RF antenna 5 is provided in the upper center of the upper electrode 4, and is formed between the upper electrode 4 and the wafer W. FIG. The density of the plasma is higher than the edge portion, and thus, the center portion is etched more than the edge of the wafer W, so there is a limit in improving the etching uniformity.
상기와 같은 문제점을 감안하여 안출한 본 고안의 목적은 웨이퍼의 상부에 균일하게 플라즈마가 형성되도록 하여 식각균일도를 향상시키도록 하는데 적합한 반도체 웨이퍼 식각장비의 플라즈마 인가장치를 제공함에 있다.An object of the present invention devised in view of the above problems is to provide a plasma applying apparatus of a semiconductor wafer etching equipment suitable for improving the etching uniformity by forming a plasma uniformly on top of the wafer.
제1도는 종래 반도체 웨이퍼 식각장치의 구성을 개략적으로 보인 종단면도.1 is a longitudinal sectional view schematically showing the configuration of a conventional semiconductor wafer etching apparatus.
제2도는 종래 반도체 웨이퍼 식각장치의 구성을 개략적으로 보인 평면도.2 is a plan view schematically showing the configuration of a conventional semiconductor wafer etching apparatus.
제3도는 본 고안 반도체 웨이퍼 식각장치의 구성을 개략적으로 보인 종단면도.Figure 3 is a longitudinal sectional view schematically showing the configuration of the semiconductor wafer etching apparatus of the present invention.
제4도는 본 고안 반도체 웨이퍼 식각장치의 구성을 개략적으로 보인 평면도.Figure 4 is a plan view schematically showing the configuration of the semiconductor wafer etching apparatus of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 챔버 12 : 정전척11 chamber 12 electrostatic chuck
13 : 하부전극 14 : 상부전극13: lower electrode 14: upper electrode
15, 15' : 알 에프 안테나 W : 웨이퍼15, 15 ': RF antenna W: wafer
상기와 같은 본 고안의 목적을 달성하기 위하여 공정 챔버와, 그 공정 챔버의 내측하부에 설치되며 웨이퍼를 고정시키기 위한 정전척과, 그 정전척의 하부에 설치되는 하부전극과, 상기 정전척의 상부에 설치되는 상부전극과, 그 상부전극의 상부에 설치되며 알 에프 파워를 각각 인가할 수 있도록 설치된 크기가 다른 복수개의 원형 알 에프 안테나를 포함하여서 구성되는 것을 특징으로 하는 반도체 웨이퍼 식각장치가 제공된다.In order to achieve the object of the present invention as described above, a process chamber, an electrostatic chuck for fixing the wafer and installed in the inner lower portion of the process chamber, a lower electrode provided in the lower portion of the electrostatic chuck, and is installed on the upper A semiconductor wafer etching apparatus is provided comprising an upper electrode and a plurality of circular R antennas of different sizes installed on top of the upper electrode and adapted to apply RF power, respectively.
이하, 상기와 같이 구성되는 본 고안 반도체 웨이퍼 식각장치를 첨부된 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Hereinafter, the semiconductor wafer etching apparatus of the present invention configured as described above will be described in more detail with reference to embodiments of the accompanying drawings.
제3도는 본 고안 반도체 웨이퍼 식각장치의 구성을 개략적으로 보인 종단면도이고, 제4도는 본 고안 반도체 웨이퍼 식각장치의 구성을 개략적으로 보인 평면도로서, 도시된 바와 같이, 본 고안은 반도체 웨이퍼 식각장치는 원통형의 공정 챔버(11) 내측에 웨이퍼(W)를 얹어놓기 위한 정전척(12)이 설치되어 있고, 그 정전척(12)의 하부에는 하부전극(13)이 설치되어 있으며, 그 하부전극(13)의 하측으로는 알 에프 바이아스를 인가할 수 있도록 연결되어 있다.3 is a longitudinal cross-sectional view schematically showing the configuration of the semiconductor wafer etching apparatus of the present invention, Figure 4 is a plan view schematically showing the configuration of the semiconductor wafer etching apparatus of the present invention, as shown, the present invention is a semiconductor wafer etching apparatus An electrostatic chuck 12 for mounting the wafer W is provided inside the cylindrical process chamber 11, and a lower electrode 13 is provided below the electrostatic chuck 12, and the lower electrode ( The lower side of 13) is connected to apply RF vias.
그리고, 상기 정전척(12)의 상부에는 상부전극(14)이 설치되어 있고, 그 상부전극(14)의 상측으로는 알 에프 파워를 각각 인가할 수 있도록 크기가 다른 2개의 원형 내,외측 알 에프 안테나(15), (15')가 설치되어 있다.In addition, an upper electrode 14 is provided on an upper portion of the electrostatic chuck 12, and two inner and outer eggs having different sizes so as to be able to apply an RF power to the upper electrode 14. F antennas 15 and 15 'are provided.
도면중 미설명부호 16은 가스주입구이고, 17은 가스배출관이다.In the figure, reference numeral 16 is a gas inlet, and 17 is a gas discharge pipe.
상기와 같이 구성되어 있는 본 고안 반도체 웨이퍼 식각장치는 정전척(12)의 상면에 웨이퍼(W)를 얹어놓고, 가스주입구(16)를 통하여 챔버(11)의 내측으로 공정가스를 주입한다. 그런 다음, 2개의 내, 외측 알 에프 안테나(15), (15')에 알 에프 파워를 인가하여 챔버(11)의 내측에 플라즈마가 형성되도록 함으로서, 플라즈마에 의한 웨이퍼(W)의 식각이 이루어지도록 한다. 그리고, 상기와 같이 설치되어 있는 내,외측 알 에프 안테나(15), (15')는 각각 알 에프 파워를 콘트롤할 수 있도록 되어 있기 때문에 웨이퍼(W)의 상부에 형성되는 플라즈마 밀도를 조절하여 균일한 식각이 이루어지도록 콘트롤하게 된다.In the semiconductor wafer etching apparatus of the present invention configured as described above, the wafer W is placed on the upper surface of the electrostatic chuck 12, and the process gas is injected into the chamber 11 through the gas injection hole 16. Then, the plasma is formed inside the chamber 11 by applying the RF power to the two inner and outer RF antennas 15 and 15 ', thereby etching the wafer W by the plasma. To lose. In addition, since the inner and outer RF antennas 15 and 15 'installed as described above can control the RF power, respectively, the plasma density formed on the upper portion of the wafer W is uniformly adjusted. It is controlled to make an etch.
이상에서 상세히 설명한 바와 같이, 본 고안 반도체 웨이퍼 식각장치는 각각 알 에프 파워를 인가할 수 있도록 되어 있는 원형의 내, 외측 알 에프 안테나를 설치하여, 웨이퍼의 상부에 균일한 밀도의 플라즈마가 형성되도록 조절함으로서, 웨이퍼의 식각균일도를 향상시키게 되는 효과가 있다.As described in detail above, the inventive semiconductor wafer etching apparatus is provided with circular inner and outer RF antennas each capable of applying RF power, so that plasma of a uniform density is formed on the wafer. By doing so, there is an effect of improving the etching uniformity of the wafer.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019970036101U KR200183543Y1 (en) | 1997-12-08 | 1997-12-08 | Etching device for semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019970036101U KR200183543Y1 (en) | 1997-12-08 | 1997-12-08 | Etching device for semiconductor wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990023698U KR19990023698U (en) | 1999-07-05 |
| KR200183543Y1 true KR200183543Y1 (en) | 2000-08-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019970036101U KR200183543Y1 (en) | 1997-12-08 | 1997-12-08 | Etching device for semiconductor wafer |
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| KR (1) | KR200183543Y1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100478106B1 (en) * | 2001-12-10 | 2005-03-24 | (주)울텍 | Apparatus of high density plasma |
| KR100486712B1 (en) * | 2002-09-04 | 2005-05-03 | 삼성전자주식회사 | Inductively coupled plasma generating apparatus with double layer coil antenna |
| KR100780021B1 (en) * | 2006-05-31 | 2007-11-27 | 가부시키가이샤 히다치 하이테크놀로지즈 | Plasma processing method and plasma processing apparatus |
-
1997
- 1997-12-08 KR KR2019970036101U patent/KR200183543Y1/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100478106B1 (en) * | 2001-12-10 | 2005-03-24 | (주)울텍 | Apparatus of high density plasma |
| KR100486712B1 (en) * | 2002-09-04 | 2005-05-03 | 삼성전자주식회사 | Inductively coupled plasma generating apparatus with double layer coil antenna |
| KR100780021B1 (en) * | 2006-05-31 | 2007-11-27 | 가부시키가이샤 히다치 하이테크놀로지즈 | Plasma processing method and plasma processing apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990023698U (en) | 1999-07-05 |
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