KR200155998Y1 - Circuit for limitting over-range by discriminating synchronous signals - Google Patents

Abstract

The present invention relates to an over-range limit circuit by synchronizing a signal, and includes a horizontal / vertical sync signal input terminal 10 for receiving a horizontal / vertical sync signal input to a monitor from a video card of a computer, and the horizontal / vertical sync. A synchronization signal polarity conversion unit 20 connected to an output terminal of the signal input terminal 10 to convert polarity of the horizontal / vertical synchronization signal, and an output terminal of the synchronization signal polarity conversion unit 20 to the synchronization signal polarity conversion unit 20. An over-range limiter 30 for limiting the over-range to an abnormal external signal inputted to the coupled signal, and connected to an output terminal of the over-range limiter 30 to control a sync signal duty. 40 and a synchronization signal polarity reduction unit 40 connected to the output terminal of the synchronization signal duty control unit 40 to reduce the synchronization signal polarity, and the vertical and horizontal synchronization By limiting the over range from the sync signal input terminal to external signals that fall outside the monitor specifications when is input to the monitor, there is an effect of preventing damage to the circuit, preventing malfunctions and providing an overall environment for safe operation. .

Description

Over-range limit circuit by discriminating synchronization signal

The present invention relates to an over-range limit circuit by synchronizing a signal, and more particularly, to determine the polarity of a sync signal input to the monitor to limit the over-range of the sync signal so as to protect the monitor circuit and prevent malfunction. It relates to an over range limiting circuit by signal discrimination.

In general, a computer peripheral device refers to an input / output device such as a monitor, a printer, and a compact disk-read only memory (CD-ROM) connected to a computer system.

Among the input and output devices, with the development of computers which have changed rapidly in recent years, multi-sync monitors that accommodate various resolutions also occupy most of the market.

As a result, the circuit part to be controlled by each mode of the multi-sync has been increased, and the function of the microcomputer for controlling various functions has been increased. The monitor using the function of the microcomputer will be described.

1 is a block diagram showing an internal circuit of a display monitor generally used. As shown in the drawing, the PC 100 receives and processes a keyboard signal and generates data according to the processed result, and receives the data output from the CPU 110 and receives the image signals R and G. And a video card 120 for outputting the horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V-SYNC for synchronizing and outputting the image signal R, G, and B to be processed and output. It is.

The display monitor 200 receiving the image signals R, G, and B, the horizontal synchronizing signal H-SYNC, and the vertical synchronizing signal V-SYNC output from the video card 120 in the PC 100. The microcomputer 210 determines the resolution by receiving the horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V-SYNC, and generates a screen control signal for controlling the display monitor screen and generates the generated monitor screen control signal. A control button unit 220 for outputting a horizontal and vertical output circuit unit 230 for synchronizing a raster by receiving a monitor screen control signal and a reference oscillation signal output from the microcomputer 210; And a video circuit unit 240 that receives and amplifies and displays an image signal output from the video card 120, and the microcomputer 210, the horizontal and vertical output circuit units 230, and the image signal processor 240. Supplying the driving voltage A power supply circuit section 250 is provided.

Looking at each block in the display monitor 200 having such a configuration in more detail as follows.

The horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V-SYNC output from the video card 120 of the PC 100 are applied by the microcomputer 210 which stores various screen control data. The microcomputer 210 receiving the horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V-SYNC adjusts an image displayed on the screen according to a screen control signal applied from the control button unit 220. The phase adjustment signal and the reference oscillation signal are output.

The horizontal and vertical oscillation signal processor 231 receiving the phase adjustment signal and the reference oscillation signal output from the microcomputer 210 receive the horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V- applied from the video card 120. SYNC) applies a vertical pulse to the vertical drive circuit 236 for controlling the switching speed of the on / off operation of the sawtooth generating circuit.

The vertical drive circuit 236, which receives a vertical pulse, is generally used with one stage of vertical amplification type, and has an emitter follower type that applies an input to a base terminal of a transistor and extracts an output voltage from an emitter terminal. It is used a lot. Therefore, the linearity improvement operation is performed rather than the gain. The vertical output circuit 237 receiving the current signal output from the vertical drive circuit 236 generates a sawtooth current corresponding to the vertical synchronizing pulse flowing through the V-DY 239, whereby the vertical scan period is determined. do.

In addition, the horizontal oscillation signal output from the horizontal and vertical oscillation signal processor 231 is applied by the horizontal drive circuit 234. The horizontal oscillation signal causes the horizontal drive circuit 234 to supply sufficient current to turn on / off the horizontal output circuit 235. The horizontal drive circuit 235 has an in-phase (dynamic polarity) method in which the output stage is turned on when the drive stage is on, and an inverted phase (inverse polarity) scheme in which the output stage is turned off when the drive stage used in the current stage is turned on. The horizontal output circuit 235, which receives the current output from the horizontal drive circuit 234 having such characteristics, generates a sawtooth wave current in the H-DY 238. This sawtooth current determines the horizontal scanning period.

In addition, through a flyback transformer (FBT) 233 to supply a stable direct current (DC) voltage to an anode of a cathode ray tube (hereinafter referred to as a CRT) 243. By using the retrace collector and using harmonics due to the leakage inductance and the distribution capacity of the high voltage circuit 232, even when the collector pulse is small, a large high voltage is generated and applied to the anode terminal 245 of the CRT 244.

The anode terminal 245 which is applied with the high voltage forms a high voltage on the anode surface by the applied high voltage, and the luminance of the image signals R, G, and B that are amplified and output from the image signal processor 240 are output. Will be adjusted. At this time, the image signal processor 240 receives the OSD data according to the screen control from the microcomputer 210 from the OSD unit 241 and outputs an OSD gain signal.

The OSD gain signal output from the OSD unit 241 and the image signals R, G, and B applied from the video card 120 are applied by the video preamplifier 242. The video preamplifier 242, which receives the OSD gain signal and the image signals R, G, and B, is a low voltage amplifier to amplify low image signals R, G, and B to maintain a constant voltage level.

E.g., for example, it amplifies a signal of less than 1V _PP into a signal of 4 ~ 6V _PP. In this way four to signal that a video output amplifier 243 is amplified by a 6V _PP will supply the energy in each pixel to amplify a signal of 40 ~ 60V _PP. The video signal amplified by the video output amplifier 243 is applied to the cathode of the CRT 244 to display the video signals R, G, and B on the screen.

The power supply circuit unit 250, which supplies a driving voltage for displaying the image signals R, G, and B through the display monitor screen, receives an alternating current (hereinafter, referred to as AC) input terminal 251 for receiving commercial AC. The exchange is input through. The degaussing coil 252, which receives the alternating current output through the AC input terminal 251, restores the color bleeding state of the screen to the original color due to the geomagnetic field or external conditions.

In this operation, when alternating current is applied to the degaussing coil 252 for 2 to 8 seconds, the magnetic field formed in the shadow mask in the display monitor 200 is dispersed to restore the color bleeding state.

In addition, a direct current rectified and output through the rectifier 253 is applied to the switching transformer 254. The switching transformer 254 receiving direct current performs a switching operation to supply various driving voltages required in the monitor 200 through the voltage output terminal 255. At this time, if the vertical synchronization signal V-SYNC is not applied from the video card 120, the microcomputer 210 applies the suspend mode signal to the voltage regulator 256 to block the deflection voltage.

The square wave pulse of the pulse width modulation (PWM) unit 256 performs on / off drive operation of the switching device, and the change in the pulse width increases and decreases the conduction time to stabilize the output voltage. Let's go.

In addition, the microcomputer 210 may power off depending on whether the horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V-SYNC are detected in order to reduce power consumption consumed in the display monitor 200. Mode and Suspend modes are generated.

As described above, the monitor 200 is a peripheral device that displays horizontal / vertical synchronization signals and video signals R, G, and B generated from a video card mounted in a computer on a CRT. The synchronous signal output from has various timing modes ranging from 30KHz to 100KHz depending on the resolution.

As such, a multi-sync monitor is used to fully compatible with various timing modes.

However, there is a reference range of sync signals that can display vertical and horizontal sync signals output from the computer's video card and input to the monitor, so that the monitor does not meet its design specifications. ), Only a little back raster appears on the picture of the CRT and no scanning pattern is displayed.

As described above, there is a problem that the circuit can cope with an overrange in which the synchronization signal input from the video card of the computer does not meet the specifications of the monitor, so there is a problem in that it operates abnormally or breaks the components configured in the circuit.

Accordingly, the present invention is a monitor that operates by receiving synchronization signals generated from various video cards of a computer, and when the vertical and horizontal synchronization signals are input to the monitor, an external signal that deviates from the monitor specification is overwritten from the synchronization signal input terminal. The purpose is to limit the range to prevent damage to the circuit and to provide an overall environment for safe operation.

In order to achieve the above object, a horizontal / vertical sync signal input terminal 10 for receiving a horizontal / vertical sync signal input to a monitor from a video card of a computer, and an output terminal of the horizontal / vertical sync signal input terminal 10. A synchronous signal polarity converting unit 20 connected to convert the polarity of the horizontal / vertical synchronous signal and an output terminal of the synchronous signal polarity converting unit 20, an abnormal external signal input to the synchronous signal polarity converting unit 20. An over-range limiter 30 for limiting the over-range with respect to the synchronous signal, and a synchronous signal duty controller 40 for controlling the synchronous signal duty connected to an output terminal of the over-range limiter 30. The synchronization signal polarity reducing unit 40 is connected to the output terminal of the duty controller 40 to reduce the synchronization signal polarity.

1 shows an internal circuit block of a typical display monitor,

2 shows a block diagram constructed according to the present invention,

3 illustrates a logic circuit of an exclusive OR gate,

4 is a circuit diagram illustrating the configuration of FIG. 2 in detail;

5 and 6 show waveform diagrams of a synchronization signal input to a monitor.

Referring to the configuration according to the present invention having such a feature using the accompanying drawings as follows.

2 is a block diagram for implementing the present invention, a horizontal / vertical sync signal input stage 10 for receiving a horizontal / vertical sync signal input to a monitor from a video card of a computer, and the horizontal A synchronization signal polarity converting unit 20 for converting the polarity of the input horizontal / vertical synchronizing signal is connected to the output terminal of the vertical / vertical synchronizing signal input terminal 10, and to the output terminal of the synchronization signal polarity converting unit 20, An over range limiter 30 is connected to limit an overrange to an abnormal external signal inputted to the signal polarity converting unit 20, and an output end of the overrange limiter 30 is optimally accommodated by the monitor. A synchronization signal duty control unit 40 is provided to provide an environment of the synchronization signal, and an output terminal of the synchronization signal duty control unit 40 has a synchronization signal ring for reducing the polarity of the synchronization signal. The part 50 is connected.

In addition, FIG. 3 is a logic circuit showing the configuration of an exclusive OR gate (XOR). When both input terminals are low, the output terminal is low, and when one terminal is high, the output is high. When both terminals are high, the output is low.

The operation of the present invention according to such a configuration will be described in detail with reference to the circuit diagram of FIG. 4.

As shown, the synchronization signal polarity conversion unit 20 includes a polarity determination filter 21 composed of a resistor R0 and a capacitance C0 and a synchronization signal input from the synchronization signal input terminal 10. And an exclusive OR gate (XOR1) 22 which receives the synchronization signal determined by the polarity discrimination filter 21 and always outputs the positive polarity regardless of the polarity.

In addition, the clear terminal of the over-range limiter 30 is connected to a power input terminal Vcc, the 1A input terminal operating by recognizing an input pulse is grounded, and is output from the synchronization signal polarity converter 20. Multi-Vibrator 1 (hereinafter, M), which combines a positive positive signal into the input terminals of C and R / C, with a time constant of resistor R1 and capacitance C1 to determine the output duty. / V 1), and the clear stage is connected to the power input terminal (Vcc), the 2A input terminal operating by recognizing the input pulse is grounded, the resistor (R2) and the input terminal of the C and R / C Synchronization signal duty control unit 40 composed of Multi Vibrator 2 (hereinafter referred to as M / V 2) which is combined with capacitance (C2) to make the duty optimally acceptable to the monitor. )

One input terminal of the synchronization signal reduction unit 50 receives a synchronization signal determined by the polarity discrimination filter 21, and the other input terminal receives the synchronization signal output from the output terminal of the synchronization signal duty controller 40. It consists of an exclusive oar gate (XOR2).

5 and 6 illustrate waveform diagrams of a synchronization signal input to the over-range restriction and synchronization signal duty controller 30 in FIG. 4, and FIG. 5 illustrates that a synchronization signal input to a monitor does not exceed a specification of the monitor. FIG. 6 is a waveform diagram illustrating a case in which a synchronization signal exceeds a monitor specification.

Referring to the operation according to this configuration, the horizontal / vertical synchronization signal output from the video card of the computer is input to the synchronization signal input terminal 10 of the monitor. In this way, the synchronization signal input to the synchronization signal input terminal 10 is input to one input terminal of the exclusive OR gate XOR1 22 for always outputting the positive polarity regardless of the polarity. Further, the synchronization signal input to the polarity discrimination filter 21 and discriminated by the resistor R0 and the capacitance C0 is input to either input terminal of the exclusive OR gate XOR1 22 and at the same time the synchronization signal polarity. It is input to either input terminal of the exclusive OR gate XOR2 of the reduction part 50.

As described above, the exclusive OR gate (XOR1) 22 that receives the sync signal output from the sync signal input terminal 10 and the sync signal determined from the polarity discrimination filter 21 is used to operate the logic circuit as shown in FIG. 3. As a result, regardless of the polarity, the positive polarity is always output to the over range limiter 30 with positive polarity.

In this way, regardless of the polarity of the synchronization signal polarity conversion unit 20, the synchronization signal always output with positive polarity is input to 1B, which is an input terminal of the M / V 1 of the over range limiter. In this case, if the positive sync signal input to the M / V 1 input terminal does not exceed the monitor specification, the normal signal is sent to 1Q of the output terminal as shown in FIG. If an abnormal signal exceeding the specification of, i.e., Spec-Over, as shown in FIG. 6, the overrange is retriggered in the Tw duty period by time constants R1 and C1 that determine the duty of the output stage 1Q. The over range is thereby limited.

In this way, the synchronization signal having the duty reproduced in M / V 1 is input to 2B which is the input terminal of M / V 2. At this time, by adjusting the output pulse by the resistor R2 and the capacitance C2, which are time constants, the monitor is outputted through 2Q of the output stage, making the monitor an optimally acceptable duty.

In addition, a synchronization signal output through 2Q, which is an output terminal of M / V 2, is input to any input terminal of the synchronization signal polarity reducing unit 50, and another input terminal is a synchronization signal determined by the polarity determination filter 21. The polarity of the synchronization signal is reduced by the operation characteristic of the exclusive logic circuit.

As described above, when the synchronization signal input to the monitor exceeds the monitor's design specification, the over-range is limited to prevent the monitor from protecting the circuit and malfunctioning.

Claims (4)

A synchronization signal input stage 10 for receiving a horizontal / vertical synchronization signal input to a monitor from a video card of a computer, A sync signal polarity converting unit 20 for converting the polarity of the horizontal / vertical sync signal output from the sync signal input terminal 10; An over-range limiter 30 for limiting an over-range to an abnormal external signal input from the sync signal polarity converter 20; A synchronization signal duty controller 40 which receives the signal output from the over range limiter 30 and makes an optimal duty acceptable to the monitor; An over-range limit circuit by synchronizing signal discrimination comprising a synchronizing signal polarity reducing unit 50 which receives the signal output from the synchronizing signal duty control unit 40 and the synchronizing signal polarity converting unit 20 and reduces the polarity of the synchronizing signal. . The method of claim 1, The synchronization signal polarity conversion unit 20 includes a polarity determination filter 21 including a resistor R0 and a capacitance C0, a synchronization signal input from the synchronization signal input terminal 10, and the polarity. A synchronization signal comprising an exclusive OR gate (XOR1) 22 that receives a synchronization signal determined by the discrimination filter 21 and always outputs a positive polarity regardless of the polarity. Overrange limit circuit by discrimination. The method of claim 1, The over range limiter 30 includes an M / V 1 coupled to a resistor R1 and a capacitance C1 as time constants to determine an output duty. Circuit. The method of claim 1, The synchronization signal duty controller 40 includes M / V 2 for adjusting the output pulse to an optimum condition that the monitor can accept by the resistance R 2 and the capacitance C 2, which are time constants. An over-range limit circuit by determining the synchronization signal.