KR20010106711A - Method for forming contact in semiconductor device - Google Patents
Method for forming contact in semiconductor device Download PDFInfo
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- KR20010106711A KR20010106711A KR1020000027635A KR20000027635A KR20010106711A KR 20010106711 A KR20010106711 A KR 20010106711A KR 1020000027635 A KR1020000027635 A KR 1020000027635A KR 20000027635 A KR20000027635 A KR 20000027635A KR 20010106711 A KR20010106711 A KR 20010106711A
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- Prior art keywords
- forming
- epitaxial silicon
- contact
- silicon layer
- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000010410 layer Substances 0.000 claims abstract description 78
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 53
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 53
- 239000010703 silicon Substances 0.000 claims abstract description 53
- 238000009792 diffusion process Methods 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 12
- 238000002955 isolation Methods 0.000 claims abstract description 12
- 150000004767 nitrides Chemical class 0.000 claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000001039 wet etching Methods 0.000 claims abstract description 6
- 238000004519 manufacturing process Methods 0.000 claims abstract description 4
- 239000007789 gas Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 7
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 7
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 3
- 239000012159 carrier gas Substances 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims 1
- 230000002265 prevention Effects 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
- H01L21/28562—Selective deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
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- H01—ELECTRIC ELEMENTS
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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Abstract
본 발명은 선택적 에피택셜 성장을 이용한 콘택 형성 방법에 관한 것으로, 이를 위한 본 발명은 워드라인, 소오스/드레인과 소자격리층이 형성된 반도체 소자의 제조 방법에 있어서, 상기 워드라인의 양측면에 접하는 질화막스페이서를 형성하는 제 1 단계, 상기 소오스/드레인의 표면상에 1차 선택적 에피택셜 성장을 실시하여 상기 워드라인의 절반높이만큼 제 1 에피택셜실리콘층을 형성하는 제 2 단계, 상기 제 1 에피택셜실리콘층 사이의 소자격리층을 포함한 전면에 산화물층을 형성하는 제 3 단계, 상기 산화물층을 습식식각하여 상기 제 1 에피택셜실리콘층의 측면확산을 방지하는 측면확산방지막을 형성하는 제 4 단계, 상기 제 1 에피택셜실리콘층상에 2차 선택적 에피택셜 성장을 실시하여 상기 워드라인 높이만큼 제 2 에피택셜실리콘층을 형성하는 제 5 단계, 및 상기 제 2 에피택셜실리콘층을 포함한 전면에 층간절연막을 형성하고 상기 층간절연막을 선택적으로 식각하여 콘택을 형성하는 제 6 단계를 포함하여 이루어진다.The present invention relates to a method for forming a contact using selective epitaxial growth. The present invention provides a method for manufacturing a semiconductor device having a word line, a source / drain, and an isolation layer, wherein the nitride film spacer is in contact with both sides of the word line. A second step of forming a first epitaxial silicon layer by half the height of the word line by performing a first selective epitaxial growth on the surface of the source / drain A third step of forming an oxide layer on the entire surface including the device isolation layer between the layers, and a fourth step of forming a side diffusion prevention film that prevents side diffusion of the first epitaxial silicon layer by wet etching the oxide layer. Second selective epitaxial growth is performed on the first epitaxial silicon layer to form a second epitaxial silicon layer by the word line height. Is achieved by forming an interlayer insulating film on the front, including the step of claim 5, and wherein the second epitaxial silicon layer and a sixth step of forming a contact by selectively etching the interlayer insulating film.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 선택적 에피택셜 실리콘성장을 이용한 콘택의 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and a method for forming a contact using selective epitaxial silicon growth.
일반적으로 도핑된 선택적에피택셜 실리콘을 이용하여 셀지역의 비트라인콘택을 형성하는 방법으로 워드라인 형성후 소오스/드레인 영역의 상부에 도핑된 선택적에피택셜실리콘을 워드라인 높이만큼 성장시키면 별도의 자기정렬콘택 공정없이 비트라인콘택을 형성할 수 있다.In general, a bit line contact of a cell region is formed by using doped selective epitaxial silicon. When a doped selective epitaxial silicon grown on the top of a source / drain region by the word line height is formed after word line formation, a separate self-alignment is performed. Bit line contacts can be formed without a contact process.
도 1 은 종래기술에 따른 콘택의 형성 방법을 나타낸 도면으로서, 소자격리층(12)에 의해 활성영역이 정의된 반도체 기판(11) 상에 게이트절연막(13)을 개재하여 폴리실리콘(14)과 텅스텐실리사이드(15)로 구성된 워드라인을 형성하고, 상기 워드라인의 양측면에 접하는 측벽(16)을 형성한다.1 is a view illustrating a method of forming a contact according to the prior art, wherein a polysilicon 14 is formed on a semiconductor substrate 11 having an active region defined by an element isolation layer 12 via a gate insulating film 13. A word line composed of tungsten silicide 15 is formed, and sidewalls 16 are formed to contact both sides of the word line.
그리고 상기 측벽(16)을 포함한 워드라인을 마스크로 이용한 불순물 이온주입으로 상기 반도체 기판(11) 표면내에 소오스/드레인 영역(17)을 형성한다.The source / drain regions 17 are formed in the surface of the semiconductor substrate 11 by implanting impurity ions using a word line including the sidewalls 16 as a mask.
이어 선택적 에피택셜 성장을 이용하여 상기 소오스/드레인 영역(17)의 표면에 에피택셜 실리콘층(18)을 형성한다. 이 때 상기 선택적 에피택셜 성장의 주요 특성인 과도측면확산(Over lateral growth)에 의해 인접한 소자간 소오스/드레인 영역(17)이 쇼트된다.The epitaxial silicon layer 18 is then formed on the surface of the source / drain regions 17 using selective epitaxial growth. At this time, the source / drain regions 17 adjacent to each other are shortened by over lateral growth, which is a main characteristic of the selective epitaxial growth.
이와 같이, 초미세 소자에서는 워드라인 사이에 에피택셜실리콘을 성장하는 활성영역간의 거리가 너무 가깝기 때문에 한번에 워드라인 높이까지 에피택셜실리콘을 성장시키면 에피택셜실리콘의 측면성장때문에 활성영역끼리 서로 연결되어 인접한 소자간 쇼트가 발생된다.As such, in the ultra-fine devices, the distance between the active regions for growing epitaxial silicon between word lines is too close. Therefore, when epitaxial silicon is grown up to the word line height at one time, the active regions are connected to each other due to lateral growth of epitaxial silicon. Short circuit between devices occurs.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로서, 유동성이 우수한 산화물을 이용하여 에피택셜실리콘 사이를 분리시키므로써 소자간 쇼트를 방지하는데 적합한 콘택의 형성 방법에 관한 것이다.The present invention has been made to solve the above problems, and relates to a method for forming a contact suitable for preventing short circuit between devices by separating epitaxial silicon using an oxide having excellent fluidity.
도 1 은 종래기술에 따른 콘택 형성 방법을 나타낸 도면,1 is a view showing a contact forming method according to the prior art,
도 2a 내지 도 2d 는 본 발명의 실시예에 따른 콘택의 형성 방법을 나타낸 도면.2A-2D illustrate a method of forming a contact in accordance with an embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
21 : 반도체 기판 22 : 소자격리층21 semiconductor substrate 22 device isolation layer
23 : 게이트절연막 24a : 폴리실리콘23: gate insulating film 24a: polysilicon
24b : 텅스텐실리사이드 24 : 워드라인24b: tungsten silicide 24: word line
25 : 측벽 26 : 소오스/드레인 영역25 side wall 26 source / drain region
27 : 제1 에피택셜실리콘층 28 : 산화물층27: first epitaxial silicon layer 28: oxide layer
29 : 측면확산방지막 30 : 제2 에피택셜실리콘층29: side diffusion prevention film 30: second epitaxial silicon layer
31 : 층간절연막 32 : 비트라인콘택31 interlayer insulating film 32 bit line contact
상기의 목적을 달성하기 위한 본 발명의 콘택 형성 방법은 워드라인, 소오스/드레인과 소자격리층이 형성된 반도체 소자의 제조 방법에 있어서, 상기 워드라인의 양측면에 접하는 질화막스페이서를 형성하는 제 1 단계, 상기 소오스/드레인의 표면상에 1차 선택적 에피택셜 성장을 실시하여 상기 워드라인의 절반높이만큼 제 1 에피택셜실리콘층을 형성하는 제 2 단계, 상기 제 1 에피택셜실리콘층 사이의 소자격리층을 포함한 전면에 산화물층을 형성하는 제 3 단계, 상기 산화물층을 습식식각하여 상기 제 1 에피택셜실리콘층의 측면확산을 방지하는 측면확산방지막을 형성하는 제 4 단계, 상기 제 1 에피택셜실리콘층상에 2차 선택적 에피택셜 성장을 실시하여 상기 워드라인 높이만큼 제 2 에피택셜실리콘층을 형성하는 제 5 단계, 및 상기 제 2 에피택셜실리콘층을 포함한 전면에 층간절연막을 형성하고 상기 층간절연막을 선택적으로 식각하여 콘택을 형성하는 제 6 단계를 포함하여 이루어짐을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a semiconductor device including a word line, a source / drain, and an isolation layer, the method comprising: forming a nitride film spacer in contact with both sides of the word line; A second step of forming a first epitaxial silicon layer on the surface of the source / drain by forming a first epitaxial silicon layer by half the height of the word line, and forming a device isolation layer between the first epitaxial silicon layer A third step of forming an oxide layer on the entire surface thereof, a fourth step of forming a side diffusion prevention film to prevent side diffusion of the first epitaxial silicon layer by wet etching the oxide layer, and on the first epitaxial silicon layer A fifth step of performing a second selective epitaxial growth to form a second epitaxial silicon layer by the word line height, and the second epitaxial Forming an interlayer insulating film over the silicon containing layer is characterized by a yirueojim a sixth step of forming a contact by selectively etching the interlayer insulating film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 콘택 형성 방법을 나타낸 도면이다.2A to 2D illustrate a method of forming a contact for a semiconductor device according to an exemplary embodiment of the present invention.
도 2a 에 도시된 바와 같이, 소자 격리층(22)에 의해 활성 영역이 정의된 반도체 기판(21)상에 게이트 산화막(23)을 형성한다.As shown in FIG. 2A, the gate oxide film 23 is formed on the semiconductor substrate 21 where the active region is defined by the device isolation layer 22.
여기서 상기 소자 격리층(22)은 LOCOS(Local Oxidation of Silicon)공정 또는 STI(Shallow Trench Isolation)공정을 이용하여 형성되며, 그리고 상기 게이트 산화막(23)은 30Å∼100Å 두께로 형성된다.The device isolation layer 22 may be formed using a local oxide of silicon (LOCOS) process or a shallow trench isolation (STI) process, and the gate oxide layer 23 may be formed to have a thickness of about 30 to about 100 kHz.
이어 상기 게이트 산화막(23)상에 워드라인용 전도층으로서 폴리실리콘 (24a), 텅스텐 실리사이드(24b)를 차례로 증착한 후, 상기 텅스텐 실리사이드(24b)상에 감광막(도시 생략)을 도포하고 노광 및 현상 공정으로 선택적으로 패터닝한다.Subsequently, polysilicon 24a and tungsten silicide 24b are sequentially deposited on the gate oxide film 23 as a conductive layer for word lines, and then a photoresist film (not shown) is applied on the tungsten silicide 24b and exposed and exposed. It is selectively patterned by a developing process.
이어 상기 패터닝된 감광막을 식각 마스크로 이용하고 상기 텅스텐 실리사이드(24b), 폴리실리콘(24a)을 선택적으로 식각하여 반도체 기판(21)의 활성 영역 상부에 다수개의 워드라인(24)을 형성한다.Subsequently, the patterned photoresist layer is used as an etching mask, and the tungsten silicide 24b and the polysilicon 24a are selectively etched to form a plurality of word lines 24 over the active region of the semiconductor substrate 21.
여기서 상기 워드라인(24)은 폴리실리콘(24a) 상부에 텅스텐 실리사이드 (WSix) 대신 텅스텐(W)을 형성할 수 도 있다.The word line 24 may form tungsten (W) instead of tungsten silicide (WSi x ) on the polysilicon 24a.
이어 상기 워드라인(24)을 포함한 전면에 질화막(도시 생략)을 증착하고 상기 질화막을 에치백(etch back)하여 상기 워드라인(24) 양측에 접하는 측벽 스페이서(25)를 형성한다.Subsequently, a nitride film (not shown) is deposited on the entire surface including the word line 24, and the sidewall spacer 25 contacting both sides of the word line 24 is formed by etching back the nitride film.
여기서, 상기 측벽 스페이서(25)는 100Å∼500Å의 두께로 형성된다. 그리고, 상기 측벽 스페이서(25)는 질화막 대신 산화막을 사용할 수 도 있지만, 후속 공정에서 산화물층(28)의 습식식각시 측벽 스페이서(25)가 동시에 식각되는 것을 방지하기 위해서는 질화막을 사용하는 것이 바람직하다.In this case, the sidewall spacers 25 are formed to have a thickness of 100 kPa to 500 kPa. In addition, the sidewall spacer 25 may use an oxide film instead of a nitride film. However, in order to prevent the sidewall spacers 25 from being simultaneously etched during the wet etching of the oxide layer 28 in the subsequent process, a nitride film is preferably used. .
이어 상기 측벽 스페이서(25)를 포함한 워드라인(24)을 마스크로 이용한 불순물 이온 주입으로 측벽 스페이서(25) 양측의 반도체 기판(21) 표면내에 LDD (Lightly Doped Drain) 구조의 소오스/드레인 영역(26)을 형성한다.Subsequently, source / drain regions 26 of LDD (Lightly Doped Drain) structures are formed in the surface of the semiconductor substrate 21 on both sides of the sidewall spacer 25 by impurity ion implantation using the word line 24 including the sidewall spacers 25 as a mask. ).
이어 HF 용액 또는 BOE(Buffered Oxide Etch) 용액을 이용하여 소오스/드레인 영역(26)을 포함한 반도체 기판(21) 표면에 형성된 자연산화막(도시 생략)을 세정한다.Subsequently, a natural oxide film (not shown) formed on the surface of the semiconductor substrate 21 including the source / drain regions 26 is cleaned using an HF solution or a buffered oxide etching (BOE) solution.
이어서, 선택적 에피택셜 실리콘층 형성전에 인시투(IN-SITU) 공정으로 수소(H2) 경화(Bake) 공정을 800℃∼1000℃에서 약 1분∼5분동안 실시한다.Subsequently, a hydrogen (H 2 ) hardening process is performed at 800 ° C. to 1000 ° C. for about 1 to 5 minutes in an IN-SITU process before the formation of the selective epitaxial silicon layer.
이 때 상기 수소(H2)는 5 Torr∼100 Torr 의 압력을 유지한다.At this time, the hydrogen (H 2 ) is maintained at a pressure of 5 Torr ~ 100 Torr.
도 2b 에 도시된 바와 같이, 소오스/드레인 영역(26)의 표면에 선택적 에피택셜 성장(SEG)을 이용하여 제1 에피택셜실리콘층(27)을 형성한다.As shown in FIG. 2B, the first epitaxial silicon layer 27 is formed on the surface of the source / drain region 26 using selective epitaxial growth (SEG).
이 때 상기 제1 에피택셜실리콘층(27)의 성장 조건은 LPCVD(Low PressureChemical Vapor Deposition)법으로 H2를 캐리어가스(carrier gas)로 사용하며 ,DCS와 HCl을 이용하고, 성장 온도는 800℃∼900℃를 유지한다. 여기서 수소(H2)는 5∼30 sccm, DCS(Dichlorosilane)는 50∼300sccm, HCl은 50∼200 sccm의 유량을 갖고 흐르며, 도핑 가스(doping gas)로는 PH3또는 AsH3를 이용한다.At this time, the growth condition of the first epitaxial silicon layer 27 is LP 2 (Low Pressure Chemical Vapor Deposition) method using H 2 as a carrier gas (carrier gas), using DCS and HCl, the growth temperature is 800 ℃ Maintain ˜900 ° C. Here, hydrogen (H 2 ) flows at a flow rate of 5 to 30 sccm, DCS (Dichlorosilane) to 50 to 300 sccm, HCl to 50 to 200 sccm, and as a doping gas (PH 3 or AsH 3 ) is used.
여기서 PH3또는 AsH3가스는 50∼200 sccm의 유량으로 흐른다.Wherein the PH 3 or AsH 3 gas flows at a flow rate of 50-200 sccm.
이처럼 성장되는 제1 에피택셜실리콘층(27)은 인접한 소자의 활성영역이 접하지 않을 정도의 높이 예를 들면, 워드라인(24)의 높이의 절반정도로 형성되며, 인(P), 비소(As)와 같은 불순물이 포함된 가스를 도핑가스로 이용하므로 소오스/드레인 영역(26)과 전기적으로 연결된다. 또한 선택적에피택셜 성장은 소오스/드레인 영역(26)의 표면상에만 형성되며 워드라인(24) 상부 및 소자격리층(22) 상에는 형성되지 않으나, 상기 제1 에피택셜실리콘층(27)의 측면확산에 의해 일정영역 오버랩된다.The first epitaxial silicon layer 27 grown as described above is formed at a height such that the active region of the adjacent device does not come into contact with, for example, about half of the height of the word line 24, and is formed of phosphorus (P) and arsenic (As). Since a gas containing impurities such as) is used as the doping gas, the gas is electrically connected to the source / drain region 26. In addition, selective epitaxial growth is formed only on the surface of the source / drain region 26 and is not formed on the word line 24 and the device isolation layer 22, but the side diffusion of the first epitaxial silicon layer 27 is increased. By a certain area.
이어 상기 제1 에피택셜실리콘층(27)을 포함한 전면에 유동성이 우수한 산화물층(28)을 1000∼2000Å두께로 형성한다. 여기서 상기 산화물층(28)으로 O3-TEOS(Tetra Ethyl Ortho Silicate)산화물을 이용한다. 또한 갭필(Gap-fill) 성능이 우수한 고밀도플라즈마 화학기상증착법(High Density Plasma Chemical Vapor Deposition; HDP CVD)을 이용할 수도 있다.Subsequently, an oxide layer 28 having excellent fluidity is formed on the entire surface including the first epitaxial silicon layer 27 at a thickness of 1000 to 2000 GPa. Herein, an O 3 -TEOS (Tetra Ethyl Ortho Silicate) oxide is used as the oxide layer 28. In addition, High Density Plasma Chemical Vapor Deposition (HDP CVD) may be used.
도 2c에 도시된 바와 같이, 상기 산화물층(28)을 HF용액이나 BOE용액을 이용한 습식식각으로 식각하여 상기 제 1 에피택셜실리콘층(27)의 소자간 측면확산을방지하는 측면확산방지막(29)을 형성한다.As shown in FIG. 2C, the oxide layer 28 is etched by wet etching using an HF solution or a BOE solution to prevent side diffusion between the elements of the first epitaxial silicon layer 27. ).
도 2d에 도시된 바와 같이, 상기 제1 에피택셜실리콘층(27) 상부에 선택적 에피택셜 성장을 이용하여 상기 제1 에피택셜실리콘층(27)과 전기적으로 연결되고 상기 워드라인(24)의 높이와 실질적으로 동일하게 제2 에피택셜실리콘층(30)을 성장시킨다. 이 때 선택적 에피택셜 성장 공정의 특성인 측면확산이 이루어지나 상기 측면확산방지막(29)에 의해 제2 에피택셜실리콘층(30)은 그 측면확산폭이 작다. 따라서, 이웃하는 다른 트랜지스터 사이의 소스/드레인이 서로 연결되지 않고 격리된다.As shown in FIG. 2D, the epitaxial silicon layer 27 is electrically connected to the first epitaxial silicon layer 27 using selective epitaxial growth on the first epitaxial silicon layer 27 and has a height of the word line 24. And grow the second epitaxial silicon layer 30 substantially the same. At this time, the side diffusion, which is a characteristic of the selective epitaxial growth process, is performed, but the side diffusion width of the second epitaxial silicon layer 30 is small due to the side diffusion prevention film 29. Thus, the source / drain between neighboring other transistors is isolated without being connected to each other.
이어 상기 제2 에피택셜실리콘층(30)을 포함한 전면에 층간절연막(31)을 증착한다. 이 때 상기 층간절연막(30)은 BPSG(Boron Phospho Silicate Glass), HDP CVD(High Density Plasma Chemical Vapor Deposition), 또는 APL 산화물을 사용하며 5000Å∼15000Å의 두께로 형성된다.Subsequently, an interlayer insulating layer 31 is deposited on the entire surface including the second epitaxial silicon layer 30. In this case, the interlayer insulating layer 30 is formed of boron phospho silicate glass (BPSG), HDP CVD (High Density Plasma Chemical Vapor Deposition), or APL oxide, and has a thickness of 5000 kV to 15000 kPa.
또한 상기 층간절연막(31)은 소자간 제1,2 에피택셜실리콘층(27,30)들의 쇼트 그리고 워드라인(24)과 후에 형성되는 비트라인콘택간의 쇼트를 방지하도록 유동성이 우수한 산화물을 이용하여 워드라인(24)과 제1,2 에피택셜 실리콘층(27,30)을 완전히 덮는다.In addition, the interlayer insulating layer 31 uses an oxide having excellent fluidity to prevent a short between the first and second epitaxial silicon layers 27 and 30 between devices and a short between the word line 24 and the bit line contact formed later. The word line 24 and the first and second epitaxial silicon layers 27 and 30 are completely covered.
이어 콘택마스크 공정을 쉽게 하도록 하기 위해 화학적기계적연마 공정을 이용하여 층간절연막(31)을 평탄화한다. 이어 콘택마스크를 이용하여 상기 제2 에피택셜실리콘층(30)의 일정 표면이 노출되도록 식각하여 콘택홀을 형성한 후에 상기 콘택홀을 통해 제2 에피택셜실리콘층(30)과 전기적으로 연결되도록 메탈을 증착하여 비트라인콘택(32)을 형성한다.In order to facilitate the contact mask process, the interlayer insulating layer 31 is planarized using a chemical mechanical polishing process. Subsequently, a contact hole is formed by etching a surface of the second epitaxial silicon layer 30 using a contact mask to form a contact hole, and then the metal is electrically connected to the second epitaxial silicon layer 30 through the contact hole. Deposited to form a bit line contact (32).
도면에 도시되지 않았지만, 본 발명의 다른 적용예로, 에피택셜 실리콘층 사이를 분리시켜 소자간 쇼트를 방지하기 위해 측면확산방지막으로서 질화물을 이용할 수 도 있으며, 이 때 측벽 스페이서(25) 물질로는 산화막을 이용하는 것이 바람직하다. 그리고, 상기 에피택셜 실리콘층을 서로 접하지 않는 폭으로 다수 번에 걸쳐 성장시키므로써 소자를 격리시킬 수 도 있다.Although not shown in the drawings, as another application example of the present invention, nitride may be used as a side diffusion barrier to separate the epitaxial silicon layers and prevent short circuits between the elements. It is preferable to use an oxide film. In addition, the device may be isolated by growing the epitaxial silicon layer a plurality of times so as not to contact each other.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 콘택 형성 방법은 디자인룰이 작은 초미세 소자에서 비트라인 및 다른 콘택 형성시 식각공정의 식각마진을 확보할 수 있으며, 실리콘기판에 직접 콘택식각을 하지 않기 때문에 접합 누설 전류를 감소시킬 수 있다. 또한 초미세소자에서 산화물층이 에피택셜 실리콘층의 측면확산을 방지하므로 인접한 소자간 활성영역의 쇼트를 방지할 수 있다.The contact formation method of the present invention as described above can secure the etching margin of the etching process when forming the bit line and other contacts in the ultra-fine device with a small design rule, and the contact leakage current is not directly contacted to the silicon substrate Can be reduced. In addition, since the oxide layer prevents side diffusion of the epitaxial silicon layer in the ultrafine device, it is possible to prevent the shorting of the active region between adjacent devices.
그리고 화학적기계적연마 공정을 이용한 워드라인의 평탄화가 불필요하므로 제조 공정을 단순화할 수 있는 효과가 있다.In addition, since the planarization of the word line using the chemical mechanical polishing process is unnecessary, the manufacturing process can be simplified.
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000027635A KR20010106711A (en) | 2000-05-23 | 2000-05-23 | Method for forming contact in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20010106711A (en) |
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2000
- 2000-05-23 KR KR1020000027635A patent/KR20010106711A/en not_active Application Discontinuation
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| WITN | Withdrawal due to no request for examination |