KR20010105497A - Energy recovery circuit for data drive in a Plasma Display Panel - Google Patents

Abstract

A dual- zoned, three-dimensional, resilient absorbent web is disclosed which is suitable as body-side liner for absorbent articles such as feminine pads, diapers and the like. When used as a liner in absorbent articles, the dual-zoned web combines the advantages of apertured films and soft, nonwoven cover layers in one structure while still being inherently hydrophilic. The liner comprises a web of wet-resilient, hydrophilic basesheet having a three-dimensional topography comprising elevated regions onto which hydrophobic matter is deposited or printed and a plurality of spaced apart depressed regions. In a preferred embodiment, the hydrophobic matter applied to the elevated regions of the basesheet comprises hydrophobic fibers in a contiguous nonwoven web which has been apertured or provided with slits or other openings, such that the apertures or openings overlay a portion of the depressed regions. The elevated hydrophobic regions enhance dry feel and promote fluid flow toward the lower hydrophilic regions, which comprise the exposed depressed regions of the basesheet. The basesheet is preferably in liquid communication with underlying absorbent material, most preferably a stabilized airlaid cellulosic material or compressed stabilized fluff such that the absorbent material can wick fluid out of the basesheet by capillary action. When soft, hydrophobic fibers are deposited on the elevated regions, the liner also has a soft, cloth-like feel in addition to a dry feel in use.

Description

PD recovery data drive energy recovery circuit {Energy recovery circuit for data drive in a Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data driving energy recovery circuit of a PDP, and more particularly, to a data driving energy recovery circuit of a PDP that can reduce data addressing time by performing data processing and energy recovery operations in a plasma display panel (PDP).

In general, a plasma display panel is a light emitting device that displays an image by using a gas discharge phenomenon occurring in each discharge cell. The manufacturing process is simple, the screen is easy to be enlarged, and the response speed is fast. In particular, the image display device has been in the spotlight as a display element of an image display device for the HDTV (High Definition Television) era.

Referring to the configuration, the plasma display panel includes a pair of sustain electrodes and one address electrode (X electrode), each pixel cell comprising a scan / hold (sustain) electrode (Y electrode) and a common sustain (sustain) electrode (Z electrode). M x n pixel matrix.

In addition, the plasma display panel includes an electrode, a dielectric layer, a discharge gas, and the like, which acts as a capacitive, that is, a capacitor, which functions as a charge and a discharge.

On the other hand, the plasma display panel consumes a lot of power during driving, that is, when the panel capacitor is charged and discharged, and such power consumption increases as the inch of the panel increases, which is a major obstacle to the popularization of the plasma display panel.

Therefore, in order to reduce the power consumption of the driving circuit for driving the plasma display panel, it is common to recover and use the energy supplied to the panel. The energy recovery circuit is applied to the sustain waveform to be universally applied to the sustain electrode. In recent years, it has been used for data electrodes.

1 is a view schematically showing a configuration of a conventional data driving energy recovery circuit.

Referring to FIG. 1, a conventional data electrode energy recovery circuit is largely composed of an energy recovery unit 100 and a data driver IC 200, and the energy recovery circuit 100 includes an energy recovery capacitor having one end connected to ground. 101, four switching elements 102, 103, 104, and 105 connected in series and in parallel, an inductor 106, and a power supply (not shown).

In addition, the data driver IC 200 may include two logic processor 201 for small signal processing and two serially connected outputs of the logic processor 201 as gate inputs for a field effect transistor (FET) switching operation. And a high voltage processing unit 206 composed of FETs 202 and 203 and parasitic diodes 204 and 205 of the FETs 202 and 203. In addition, the logic processor 201 and the high pressure processor 206 are connected to the same ground.

First, the operation of the energy recovery circuit in the conventional data drive energy recovery circuit having the above configuration will be described in detail.

When the power of the entire system is turned on at the beginning of the operation of the conventional energy recovery circuit 100 and a plurality of discharges continue to occur at the data electrode (not shown), the discharge current of the data electrode is energized through the inductor 106. The recovery capacitor 101 is charged, at which time the energy recovery capacitor 101 is charged with the voltage Vs / 2.

Thereafter, the first switching device 102 is turned on to supply the voltage charged in the energy recovery capacitor 101 to the data driver IC 200 through the inductor 106, and the second switching device 103 is turned on to supply the voltage. Supply (Vs).

Then, the third switching device 104 is turned on to recover the voltage supplied to the data electrode to the energy recovery capacitor 101, and finally, the fourth switching device 105 is turned on to set the ground level. Hold it.

Next, the operation of the data driver IC 200 will be described in connection with the energy recovery circuit 100.

2 is a view showing switching operation and data output waveforms of the internal FETs 202 and 203 of the conventional data driver IC.

1 and 2, the Vs voltage is supplied from the energy recovery circuit 100 only when data is supplied, and the energy recovery operation is performed by recovering the voltage at the data electrode after the voltage supply. That is, data switching is performed according to the scan time.

Referring to the operation of the data driver IC 200 in detail, the first FET 202 is turned on by the high signal of the logic processing unit 201 and started to be supplied from the energy recovery circuit 100. (section (a)). The first FET 202 is turned on until the section (b) that maintains high data, and the voltage is continuously supplied from the energy recovery circuit 100.

At this time, the second FET 203 is turned off. Section (c) of FIG. 2 is an operation when data is changed from high to low, and a period of recovering energy supplied to the data electrode to the energy recovery circuit 100 through the first FET 202 and the parasitic diode 204. to be.

This is the time the data should change from high to low but must be devoted to energy recovery. That is, the time has nothing to do with data switching. When the second FET 203 is turned on in a state where energy is not recovered, energy that has been supplied to the data electrode is returned to the ground without being fully recovered, and energy is consumed, affecting the entire data driver IC 200. It may be.

As described above, the conventional data driving energy recovery circuit has a problem in that the data addressing time is long because the time for the energy recovery operation is allowed regardless of data switching. In addition, since energy is recovered only by the FET, energy recovery takes a long time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and reduces data addressing time by simultaneously performing data switching and energy recovery operations in a PDP, and improves energy recovery and supply time by operating an energy recovery circuit through a diode. It is an object of the present invention to provide a data driving energy recovery circuit of a PDP that can be quickly performed.

1 is a view schematically showing a configuration of a conventional data driving energy recovery circuit.

Fig. 2 shows the switching operation and data output waveforms of the internal FETs 202 and 203 of the conventional data driving energy recovery circuit.

3 is a diagram schematically showing a configuration of a data driving energy recovery circuit of the present invention.

4A to 4D are diagrams for comparing the data switching time of the prior art and the present invention, and for explaining the operation of elements for the output operation of the present invention.

5 is a detailed circuit diagram showing in detail the configuration of a data driving energy recovery circuit of the present invention.

FIG. 6 is a diagram schematically illustrating a configuration in which the data driver IC outputs a low signal when the logic processing unit and the high voltage processing unit of the data driving energy recovery circuit of the present invention are separated from each other; FIG.

<Description of the symbols for the main parts of the drawings>

100308 ... energy recovery circuit 101 ... energy recovery capacitor

102,103,104,105,306,307 ... switching elements

106,510,511 ... Inductors 200,300,500,602 ... Data Driver ICs

201,301,501 ... logic processing unit

202,203,302,303,502,503,504,505,513,514 ... FET

204,205,304,305,506,507,508,509,515,516 ... parasitic diode

206,309,600 ... High Pressure Processing Unit 601 ... Photo Coupler

The data drive energy recovery circuit of the present invention for achieving the above object,

An energy recovery circuit for supplying or recovering a voltage to the data electrode; And a data drive circuit connected to the energy recovery circuit, the data drive circuit including a small signal processing section and a high voltage processing section composed of a plurality of FETs.

A plurality of switching elements may be provided between the energy recovery circuit and the data driving circuit to selectively separate the grounds of the small signal processor and the high voltage processor.

Preferably, when the ground of the small signal processing unit and the ground of the high pressure processing unit are separated, the ground of the high pressure processing unit may be connected to the energy recovery circuit.

3 is a diagram schematically showing a configuration of a data driving energy recovery circuit of the present invention.

Referring to FIG. 3, the data driving energy recovery circuit of the present invention includes an energy recovery circuit 308, a logic processing unit 301, and first and second FETs 302 and 303, and parasitic diodes 304 and 305 of the first and second FETs. Data driver IC 300 consisting of a high-pressure processing unit 300 consisting of a) and the first logic to selectively separate the high voltage ground (G2) of the logic ground (G1) and the high-pressure processing unit 309 of the logic processing unit 301. And a second switching element 307 which forms a selective path with the switching element 306 and the energy recovery circuit 308.

Referring to the operation of the data driving energy recovery circuit of the present invention having the above configuration, first, when the first switching element 306 is on, the second switching element 307 is off, the logic processing unit 301 and the high-pressure processing unit ( The grounds G1 and G2 of 300 become the same ground to perform normal data output operation. However, when the first switching element 306 is turned off and the second switching element 307 is turned on, the ground G2 of the high voltage processor 300 is separated and the energy that has been supplied to the data driver IC 300 is supplied to the high voltage processor 300. Is recovered to the energy recovery circuit 308 via ground (G2).

4A to 4D are diagrams for comparing the data switching time of the prior art and the present invention, and for explaining the operation of elements for the output operation of the present invention.

Comparing FIG. 4A and FIG. 4B, it can be seen that the data addressing speed of the present invention is faster than that of the related art by performing data switching at the same time as energy recovery.

In addition, Figure 4c is a view showing the output operation according to the present invention, Figure 4d is a view showing the operation of the two FETs and two switching elements of Figure 3 for the output operation as shown in Figure 4c.

3 and 4c to 4d, the operation of the present invention will be described based on the energy recovery period.

In the energy recovery period of FIG. 4C, the first FET 302 is turned off and the second FET 303 is turned on. In addition, the first switching device 306 is turned off and the second switching device 307 is turned on to separate the ground G2 of the high voltage processor 300 from the ground G1 of the logic processor 301 and simultaneously recover energy. To the circuit 308.

The energy supplied to the data electrode by the switching operation of the elements is recovered to the energy recovery capacitor (not shown) of the energy recovery circuit through the parasitic diode 304 of the second FET 303 and the first FET 302. do.

Therefore, unlike the conventional method in which data switching is performed after the energy recovery operation is completed, data switching can be performed at the same time as the start of the energy recovery operation, thereby enabling faster data addressing time.

5 is a detailed circuit diagram showing in detail the configuration of the data driving energy recovery circuit of the present invention.

Referring to FIG. 5, the data driving energy recovery circuit of the present invention includes an energy recovery capacitor 501, first, second, third, and fourth FETs 502, 503, 504, 505 connected in series and in parallel, and parasitic diodes of the plurality of FETs. (506, 507, 508, 509), an energy recovery circuit composed of a plurality of inductors (510, 511), a logic processor 501, and fourth and fifth FETs (513 and 514), and parasitic diodes (515 and 516) of the fourth and fifth FETs (513 and 514). The sixth FET 517 for selectively separating the data driver IC 500 having the high voltage processor 600 and the logic ground G1 of the logic processor 512 and the high voltage ground G2 of the high voltage processor 600. ) And a parasitic diode 518, a seventh FET 505 and a parasitic diode 509 that selectively connect the high voltage processor 600 and the energy recovery circuit.

Hereinafter, the operation of the data driving energy recovery circuit of the present invention having the configuration as described above will be described.

In the data driving energy recovery circuit of the present invention, the operation of the energy recovery circuit is the same as that of the conventional operation and will be omitted. However, there is a difference in that the fourth FET 505 is conventionally connected to the ground and is connected to the ground G2 of the high voltage processor 600 of the data drive IC to provide an energy recovery and supply path.

In the above configuration, the seventh FET 517 is turned on when the data driver IC 500 is normally operated so that the ground G1 of the logic processing unit 512 and the ground G2 of the high voltage processing unit 600 are the same. In the recovery operation, the signal is turned off so as to be separated from the ground G1 of the logic processing unit 512.

According to the present invention as described above, energy is rapidly recovered in two paths through the parasitic diode 515 and the fifth FET 514 of the fourth FET 513, and when the recovered energy is supplied again, the fourth FET 513 ) And the parasitic diode 516 of the fifth FET 514 are quickly supplied through two paths.

As described above, the data driving energy recovery circuit of the present invention does not need to set a separate energy recovery time by recovering energy during data switching.

In addition, since the ground G1 of the logic processor 512, which is a small signal processor, and the ground G2 of the high voltage processor 600, are separated while energy is recovered, the data driver IC 500 may not operate normally. In contrast, the data driver IC 500 can only output a low during this period.

FIG. 6 is a diagram schematically illustrating a configuration in which the data driver IC outputs a low signal when the logic processing unit and the high voltage processing unit of the data driving energy recovery circuit of the present invention are separated.

As shown in FIG. 6, the data driving energy recovery circuit of the present invention sets the output of the data driver IC 602 low, such as a blank signal, in order to allow the data driver IC 602 to output only low during the energy recovery period. Only the signal to be fixed can use the photo coupler 601.

According to the data driving energy recovery circuit of the present invention as described above, by recovering energy through the low active FET of the data driver IC, it is not necessary to spend extra time for energy recovery, thereby making data addressing faster and continuous. Effective data processing is possible.

In addition, the energy recovery and supply are both through parasitic diodes, which are faster in time than FETs.

Claims (6)

An energy recovery circuit for supplying or recovering a voltage to the data electrode; And a data drive circuit connected to the energy recovery circuit, the data drive circuit including a small signal processing section and a high voltage processing section composed of a plurality of FETs. And a plurality of switching elements provided between the energy recovery circuit and the data driving circuit to selectively separate the grounds of the small signal processing section and the high voltage processing section. The method of claim 1, When the ground of the small signal processor and the ground of the high voltage processor are separated, the ground of the high voltage processor is connected to the energy recovery circuit. The method of claim 1, And energy recovery of the energy recovery circuit is performed in parallel with data switching. The method of claim 1, Energy supply and recovery of the energy recovery circuit is a data drive energy recovery circuit, characterized in that through the diode. The method of claim 1, And said switching elements comprise a field effect transistor and a parasitic diode thereof. The method of claim 1, And means for generating a signal such that the data drive circuit outputs only a low signal during the energy recovery period.