KR20010102475A - Electronic tag assembly and method therefor - Google Patents

Electronic tag assembly and method therefor Download PDF

Info

Publication number
KR20010102475A
KR20010102475A KR1020017011167A KR20017011167A KR20010102475A KR 20010102475 A KR20010102475 A KR 20010102475A KR 1020017011167 A KR1020017011167 A KR 1020017011167A KR 20017011167 A KR20017011167 A KR 20017011167A KR 20010102475 A KR20010102475 A KR 20010102475A
Authority
KR
South Korea
Prior art keywords
integrated circuit
substrate
circuit die
antenna pattern
electronic tag
Prior art date
Application number
KR1020017011167A
Other languages
Korean (ko)
Other versions
KR100460473B1 (en
Inventor
노엘 에이치. 에버하트
션 러빙
Original Assignee
비센트 비.인그라시아, 알크 엠 아헨
모토로라 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 비센트 비.인그라시아, 알크 엠 아헨, 모토로라 인코포레이티드 filed Critical 비센트 비.인그라시아, 알크 엠 아헨
Publication of KR20010102475A publication Critical patent/KR20010102475A/en
Application granted granted Critical
Publication of KR100460473B1 publication Critical patent/KR100460473B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773—Antenna details
    • G06K19/07786—Antenna details the antenna being of the HF type, such as a dipole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01044—Ruthenium [Ru]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01056—Barium [Ba]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

전자 태그 어셈블리(100)는 안테나 패턴(104, 106)이 상부에 형성되어 있는 기판(102), 안테나 패턴(103, 106)과 직접 접촉하거나 인터페이스하는 전기 인터페이스 단자(204, 206), 및 기판과 집적 회로 다이(108) 사이에 삽입되어 그들을 고정시키며 전기 인터페이스의 일체성을 유지시키는 전기적으로 비도전성인 접착제(202)를 포함한다. 비도전성 접착제(202)가 도입되는 동안, 집적 회로 다이(108)에 형체력을 가하여 전기 단자(204, 206)와 안테나 패턴(104, 106) 간의 접촉을 유지하는 것이 바람직하다.The electronic tag assembly 100 includes a substrate 102 having the antenna patterns 104 and 106 formed thereon, an electrical interface terminal 204 and 206 that directly contacts or interfaces with the antenna patterns 103 and 106, and a substrate. An electrically nonconductive adhesive 202 inserted between the integrated circuit dies 108 to secure them and maintain the integrity of the electrical interface. While the non-conductive adhesive 202 is introduced, it is desirable to apply a clamping force to the integrated circuit die 108 to maintain contact between the electrical terminals 204, 206 and the antenna patterns 104, 106.

Description

전자 태그 어셈블리 및 그 방법{ELECTRONIC TAG ASSEMBLY AND METHOD THEREFOR}Electronic tag assembly and its method {ELECTRONIC TAG ASSEMBLY AND METHOD THEREFOR}

전자 어플리케이션에 있어서, 종종 전자 회로 부품과 캐리어 기판이 서로 접속되어 포함되어 있는 어셈블리를 형성해야 할 필요가 있다. 집적 회로 다이와 캐리어 기판간의 전기 인터페이스는, 솔더링, 와이어 본딩, 전기 도금 또는 이방성 도전성 접착제에 의해 성립된다. 이들 종래 기술의 방법들 각각은, 특정 종류의 부품 및 제조 공정에서의 이용의 적합성과 어셈블리 비용 등에 따라 각자 장단점을 갖고 있다.In electronic applications, it is often necessary to form an assembly in which the electronic circuit components and the carrier substrate are connected to each other and included. The electrical interface between the integrated circuit die and the carrier substrate is established by soldering, wire bonding, electroplating or anisotropic conductive adhesive. Each of these prior art methods has advantages and disadvantages, depending on the suitability of the particular type of component and its use in the manufacturing process and the cost of the assembly.

이방성 도전성 접착제는 제조 공정에서 확인된 특정한 장점으로 인해 보편화되어 있다. 전형적인 이방성 도전성 접착제는, 전기 인터페이스들 간에서 압착될 때 그 인터페이스들 간에 단향성(unidirectional) 전기 접착을 형성하는 금속 등의 도전 입자를 포함한다. 전기 인터페이스들 중 하나 이상에 범프 또는 볼록부를 제공하여 압착을 증진시킬 수 있다. 그러나, 소형의 부품에 도전성 접착제를 이용할 때는 제조상의 일정한 어려움이 발생한다. 예를 들어, 접착제는 인접한 단자들간의 단락을 발생시키지 않도록 정확하게 도포되어야 한다. 또한, 적합한 전기 접속을 증진시키기 위해, 접촉면이 특별하게 제공되어야 할 수도 있다. 상기한 내용과 그 이외의 비용상의 단점으로 인해, 집적 회로 다이를 캐리어 기판에 접착하는 데에 도전성 접착제를 사용하는 것에는 한계가 있다.Anisotropic conductive adhesives are commonplace due to certain advantages identified in the manufacturing process. Typical anisotropic conductive adhesives include conductive particles, such as metal, which, when pressed between electrical interfaces, form a unidirectional electrical bond between the interfaces. One or more of the electrical interfaces may be provided with bumps or convexities to enhance compression. However, certain difficulties arise in manufacturing when using a conductive adhesive for small parts. For example, the adhesive must be applied accurately so as not to cause short circuits between adjacent terminals. In addition, in order to promote a suitable electrical connection, a special contact surface may have to be provided. Due to the foregoing and other costly disadvantages, there is a limit to the use of conductive adhesives for bonding the integrated circuit die to the carrier substrate.

전자 태그 어셈블리는 부피가 큰 제품에 적합한 집적 회로 다이를 부착하는 저가의 방법을 필요로 한다. 종래 기술에서의 집적 회로 다이 접착 방법은 이러한 요구를 적절하게 만족시키지 못한다. 따라서, 집적 회로 다이를 접착하여 전자 태그 어셈블리 등의 어셈블리를 형성하기 위한 개선된 방법이 필요하다.Electronic tag assemblies require a low cost method of attaching an integrated circuit die suitable for bulky products. The integrated circuit die attach method in the prior art does not adequately meet this need. Therefore, there is a need for an improved method for bonding integrated circuit die to form an assembly, such as an electronic tag assembly.

본 발명은 일반적으로 전자 어셈블리에 관한 것으로, 특히 집적 회로 부품의 이용을 포함하는 전자 태그 어셈블리에 관한 것이다.BACKGROUND OF THE INVENTION The present invention relates generally to electronic assemblies, and more particularly to electronic tag assemblies that include the use of integrated circuit components.

도 1은 본 발명에 따른 전자 태그 어셈블리의 평면도.1 is a plan view of an electronic tag assembly according to the present invention.

도 2는 도 1의 전자 태그 어셈블리의 단면도.FIG. 2 is a cross-sectional view of the electronic tag assembly of FIG. 1. FIG.

도 3은 본 발명에 따른 조립 전 단계에서 기판과 집적 회로를 나타낸 도면.3 shows a substrate and integrated circuit at a pre-assembly stage in accordance with the present invention.

도 4는 본 발명에 따른 기판 상의 도전성 패턴 형태의 안테나와 접속된 집적 회로 상의 전기 인터페이스 단자를 나타낸 도면.4 shows an electrical interface terminal on an integrated circuit connected with an antenna in the form of a conductive pattern on a substrate according to the invention.

도 5는 본 발명에 따라 집적 회로 다이와 기판 사이에 비도전성 접착제가 도입되오 있는 것을 나타낸 도면.5 illustrates the introduction of a non-conductive adhesive between an integrated circuit die and a substrate in accordance with the present invention.

도 6은, 접착제가 집적 회로 다이의 전기 인터페이스 단자와 기판의 도전성 패턴 간의 전기적 접촉을 유지시키고 있는 집적 회로 어셈블리를 나타낸 도면.6 illustrates an integrated circuit assembly in which the adhesive maintains electrical contact between the electrical interface terminal of the integrated circuit die and the conductive pattern of the substrate.

본 발명은, 집적 회로 다이가 비도전성 접착제를 이용하여 기판에 접착되는대형의 저렴한 어플리케이션에 적합한 전자 태그 어셈블리를 제공한다. 집적 회로 다이는, 그 위의 전기 단자가 기판 상의 도전성 패턴 형태의 안테나에 접촉하도록 기판 상에 배치된다. 전기 단자와 도전성 패턴 간의 접촉을 유지한 채로, 회로 다이와 기판 사이에 비도전성 접착체가 도입되어, 집적 회로 다이를 기판에 고정시키고 전기 도전체와 도전성 패턴 간의 접촉을 유지한다. 비도전성 접착제가 도입되는 동안 집적 회로 다이 상에 형체력(clamping force)을 가하여, 전기 단자와 도전성 패턴 간의 접촉을 유지하는 것이 바람직하다.The present invention provides an electronic tag assembly suitable for large, low cost applications in which the integrated circuit die is bonded to a substrate using a non-conductive adhesive. The integrated circuit die is disposed on the substrate such that the electrical terminals thereon contact the antenna in the form of a conductive pattern on the substrate. While maintaining contact between the electrical terminal and the conductive pattern, a non-conductive adhesive is introduced between the circuit die and the substrate to secure the integrated circuit die to the substrate and maintain contact between the electrical conductor and the conductive pattern. It is desirable to apply a clamping force on the integrated circuit die while introducing the nonconductive adhesive to maintain contact between the electrical terminals and the conductive pattern.

도 1은 본 발명에 따른 전자 태그 어셈블리(100)의 평면도이고, 도 2는 그 단면도이다. 전자 태그 어셈블리(100)는 통신 회로망이 형성되어 있는 칩형 부품(108) 및 전기적으로 결합된 안테나(104, 106)를 포함한다. 칩형 부품(108)은 표준 제조 공정을 이용하여 형성된 반도체 다이이다. 다이(108)는 볼록한 전기 도전체(204, 206) 형태의 전기 인터페이스 단자, 또는 전기 인터페이스 접촉부로서 기능하는 범프를 포함하는 것이 바람직하다.1 is a plan view of an electronic tag assembly 100 according to the present invention, Figure 2 is a cross-sectional view thereof. The electronic tag assembly 100 includes a chip-like component 108 in which a communication network is formed and electrically coupled antennas 104 and 106. The chipped component 108 is a semiconductor die formed using standard fabrication processes. The die 108 preferably includes electrical interface terminals in the form of convex electrical conductors 204 and 206, or bumps that function as electrical interface contacts.

바람직한 실시예에서, 안테나(104, 106)는 기판(102) 상에 구현되며, 종이나 또는 천 등의 섬유 재료나, 플라스틱 또는 다른 저렴한 재료로 형성되는 것이 바람직하다. 안테나(104, 106)는 2개의 서로 이격된 도전성 재료의 퇴적물 패턴으로서 형성된다. 바람직한 도전성 재료는 탄소 잉크, 폴리머로 충전된 탄소, 또는 저가 응용에 적합한 다른 재료를 포함한다. 도전성 패턴은 인쇄되거나 페인트되거나 저렴한 방식으로 기판 상에 퇴적될 수 있다. 바람직한 실시예에서, 도전성 패턴 및 전기 인터페이스 도전체들은 전이 원소를 포함하지 않는다.In a preferred embodiment, the antennas 104 and 106 are implemented on the substrate 102 and are preferably formed of fibrous material, such as paper or cloth, or plastic or other inexpensive material. Antennas 104 and 106 are formed as a deposit pattern of two spaced apart conductive materials. Preferred conductive materials include carbon inks, polymer filled carbon, or other materials suitable for low cost applications. The conductive pattern can be printed, painted or deposited on the substrate in an inexpensive manner. In a preferred embodiment, the conductive pattern and the electrical interface conductors do not contain a transition element.

집적 회로 다이(108)는 전기적으로 비도전성인 접착제(202)를 이용하여 기판(102)에 접착 고정된다. 전기 인터페이스 접촉부(204, 206)가 집적 회로 다이(108)로부터 돌출되어 기판(102) 상의 도전성 패턴(104, 16)과 직접 접촉하거나 인터페이스한다. 전기적으로 비도전성인 접착제(202)가 집적 회로 다이(108)와 기판 사이(102) 사이에 개재되어 직접 접촉한다. 접착제(202)는 집적 회로 다이(108)를 기판(102)에 유지시키고, 전기적 도전체(204, 206)와 도전성 패턴(104, 106) 사이에 전기적 접촉을 유지시킨다.The integrated circuit die 108 is adhesively fixed to the substrate 102 using an electrically nonconductive adhesive 202. Electrical interface contacts 204 and 206 protrude from the integrated circuit die 108 to directly contact or interface with the conductive patterns 104 and 16 on the substrate 102. An electrically non-conductive adhesive 202 is interposed between the integrated circuit die 108 and the substrate 102 and is in direct contact. Adhesive 202 maintains integrated circuit die 108 on substrate 102 and maintains electrical contact between electrical conductors 204 and 206 and conductive patterns 104 and 106.

도 3, 4, 5 및 6은 본 발명에 따른 각종 구성의 전자 태그 조립체(100)를 도시한다. 도 3을 참조하면, 안테나 또는 도전체 패턴(104, 106)이 기판 상에 인쇄되거나 도포되고, 집적 회로 다이(108)는, 표준 제조 공정을 이용하여 별도로 준비된다. 도 4를 참조하면, 집적 회로 다이(108) 및 기판(102)은 접촉부가 다이(108) 상의 전기적 도전체(204, 206)와 기판(102) 상의 도전성 패턴(104, 106) 사이에 설치되도록 된다. 형체력이 인가되어 전기적 도전체(204, 206)와 도전성 패턴(104, 106) 간의 접촉을 유지시킨다.3, 4, 5 and 6 illustrate an electronic tag assembly 100 of various configurations in accordance with the present invention. Referring to FIG. 3, antenna or conductor patterns 104, 106 are printed or applied onto a substrate, and integrated circuit die 108 is separately prepared using standard fabrication processes. Referring to FIG. 4, the integrated circuit die 108 and the substrate 102 are such that the contacts are installed between the electrical conductors 204 and 206 on the die 108 and the conductive patterns 104 and 106 on the substrate 102. do. A clamping force is applied to maintain contact between the electrical conductors 204 and 206 and the conductive patterns 104 and 106.

도 5를 참조하면, 비도전성 접착제는 전기적 도전체(204, 206)와 도전성 패턴(104, 106) 간의 접촉을 유지하면서, 집적 회로 다이(108)와 기판(102) 사이에 도입된다. 양호하게는, 집적 회로 다이(108)는 형체력에 의해 그 자리에 유지되고, 접착제 투여 니들(needle)(502)이 다이(108)와 기판(102) 사이에 배치되어 접착제가 투여된다. 접착제가 경화됨에 따라 형체력이 유지된다. 이러한 형제력을 제거하면, 전기적 도전체(204, 206)와 도전성 패턴(104, 106) 사이의 접촉부가 접착제(602)에 의해 유지된다 (도 6 참조).Referring to FIG. 5, a nonconductive adhesive is introduced between the integrated circuit die 108 and the substrate 102 while maintaining contact between the electrical conductors 204 and 206 and the conductive patterns 104 and 106. Preferably, the integrated circuit die 108 is held in place by the clamping force, and an adhesive administration needle 502 is disposed between the die 108 and the substrate 102 to administer the adhesive. As the adhesive cures, the clamping force is maintained. Removing this sibling force maintains the contact between the electrical conductors 204 and 206 and the conductive patterns 104 and 106 by the adhesive 602 (see FIG. 6).

본 발명은 종래 기술에 비해 현저한 이점을 제공한다. 고가의 이방성 접착제를 사용하지 않고, 특수한 재료 그리고 상당한 비용이나 복잡성을 부가하는 공정 없이도, 부피가 큰 저가의 응용에 적합한 전자 태그 조립체가 제공된다. 집적 회로 다이 단자와 안테나 패턴 사이에 직접적인 전기적 접촉부를 설치함으로써, 또한 전기적으로 비도전성인 접착제로 전기적 접촉부를 유지함으로써, 저렴한 제조 공정이 제공된다.The present invention provides significant advantages over the prior art. Electronic tag assemblies are provided that are suitable for bulky low cost applications without the use of expensive anisotropic adhesives and without the need for special materials and processes that add significant cost or complexity. An inexpensive manufacturing process is provided by providing direct electrical contacts between the integrated circuit die terminals and the antenna pattern, and by maintaining the electrical contacts with an electrically nonconductive adhesive.

Claims (10)

집적 회로 어셈블리를 형성하기 위한 방법에 있어서,A method for forming an integrated circuit assembly, the method comprising: 전기 단자들이 상부에 형성되어 있는 집적 회로 다이와 안테나 패턴이 상부에 형성되어 있는 기판을 상기 전기 단자들 및 상기 안테나 패턴 간에 접촉이 확립되도록 함께 배치시키는 단계와,Arranging an integrated circuit die having electrical terminals formed thereon and a substrate having an antenna pattern formed thereon so that contact is established between the electrical terminals and the antenna pattern; 상기 전기 단자들과 상기 안테나 패턴 간에 직접 접촉을 확립시키는 단계와,Establishing direct contact between the electrical terminals and the antenna pattern; 상기 집적 회로 다이와 상기 기판 간에 전기적으로 비도전성인 접착제를 도입시키는 단계와,Introducing an electrically nonconductive adhesive between the integrated circuit die and the substrate; 상기 전기 단자들과 상기 안테나 패턴 간에서의 직접 접촉을 상기 전기적으로 비도전성인 접착제를 사용하여 유지시키는 단계Maintaining direct contact between the electrical terminals and the antenna pattern using the electrically nonconductive adhesive 를 포함하는 집적 회로 어셈블리 형성 방법.Integrated circuit assembly forming method comprising a. 제1항에 있어서, 상기 기판 상에 상기 안테나 패턴을 인쇄하는 단계를 더 포함하는 집적 회로 어셈블리 형성 방법.The method of claim 1, further comprising printing the antenna pattern on the substrate. 제2항에 있어서, 상기 인쇄 단계는 탄소 함유 재료를 사용하여 도전성 패턴을 인쇄하는 단계를 포함하는 집적 회로 어셈블리 형성 방법.The method of claim 2, wherein printing comprises printing a conductive pattern using a carbon containing material. 제3항에 있어서, 상기 인쇄 단계는 종이 상에 상기 도전성 패턴을 인쇄하는단계를 포함하는 집적 회로 어셈블리 형성 방법.The method of claim 3, wherein the printing step includes printing the conductive pattern on paper. 전자 태그 어셈블리를 형성하기 위한 방법에 있어서,A method for forming an electronic tag assembly, the method comprising: (a) 기판 상에 집적 회로 다이를 배치시키는 단계로서, 상기 집적 회로 다이 상의 전기 도체들과 상기 기판 상에 배치된 안테나 패턴이 접촉되도록 배치시키는 단계와,(a) disposing an integrated circuit die on a substrate, the electrical conductors on the integrated circuit die being disposed in contact with an antenna pattern disposed on the substrate; (b) 상기 전기 도체들과 상기 안테나 패턴 간에서의 접촉을 유지시키면서, 상기 집적 회로 다이와 상기 기판 간에 접착제를 도입시켜 상기 집적 회로 다이를 상기 기판에 고정시키며, 또한 상기 전기 도체들과 상기 안테나 패턴 간에서의 접촉을 견고히 하기 위한 단계(b) while maintaining contact between the electrical conductors and the antenna pattern, an adhesive is introduced between the integrated circuit die and the substrate to secure the integrated circuit die to the substrate, and furthermore the electrical conductors and the antenna pattern Steps to Strengthen Contact in the Liver 를 기술된 순으로 포함하는 전자 태그 어셈블리 형성 방법.Electronic tag assembly forming method comprising the described order. 제5항에 있어서, 상기 접착제는 전기적으로 비도전성인 접착제로 이루어지는 전자 태그 어셈블리 형성 방법.The method of claim 5, wherein the adhesive consists of an electrically nonconductive adhesive. 제5항에 있어서, 상기 단계 (b)는 상기 집적 회로 다이와 상기 안테나 패턴을 접촉시키기 위한 상기 접착제를 상기 집적 회로 다이와 상기 안테나 패턴 간에서의 결합이 형성되도록 배치하는 단계를 포함하는 전자 태그 어셈블리 형성 방법.6. The electronic tag assembly of claim 5, wherein said step (b) comprises disposing said adhesive for contacting said integrated circuit die and said antenna pattern such that a bond between said integrated circuit die and said antenna pattern is formed. Way. 제5항에 있어서, 상기 기판은 종이로 형성되고, 상기 종이 상에 상기 안테나 패턴을 인쇄하는 단계를 더 포함하는 전자 태그 어셈블리 형성 방법.The method of claim 5, wherein the substrate is formed of paper, and further comprising printing the antenna pattern on the paper. 전자 태그에 있어서,In the electronic tag, 기판과,Substrate, 상기 기판 상에 형성되고 이격되어 배치되는 제1 및 제2 도전 패턴을 구비하는 안테나와,An antenna having first and second conductive patterns formed on the substrate and spaced apart from each other; 제1 및 제2 전기 인터페이스 도체가 돌출되어 형성되어 있는 집적 회로 다이-상기 제1 및 제2 전기 인터페이스 도체는 이격되어 배치된 상기 제1 및 제2 도전 패턴 각각과 직접 인터페이스되어짐-와,An integrated circuit die in which first and second electrical interface conductors are formed to protrude, the first and second electrical interface conductors being directly interfaced with each of the first and second conductive patterns spaced apart; 상기 제1 및 제2 전기 인터페이스 도체 주위과 이격되어 있는 상기 제1 및 제2 도전 패턴 상에 배치되어 상기 집적 회로 다이를 상기 기판에 고정시키는 전기적으로 비도전성인 접착제An electrically nonconductive adhesive disposed on the first and second conductive patterns spaced apart around the first and second electrical interface conductors to secure the integrated circuit die to the substrate 를 포함하는 전자 태그.Electronic tag comprising a. 제9항에 있어서, 상기 기판은 섬유 재질로 형성되고, 상기 도전 패턴은 상부에 배치되는 도전성 잉크를 포함하는 전자 태그.The electronic tag of claim 9, wherein the substrate is formed of a fiber material, and the conductive pattern includes a conductive ink disposed thereon.
KR10-2001-7011167A 1999-03-02 2000-03-02 Electronic tag assembly and method therefor KR100460473B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12254799P 1999-03-02 1999-03-02
US60/122,547 1999-03-02
PCT/US2000/005522 WO2000052109A1 (en) 1999-03-02 2000-03-02 Electronic tag assembly and method therefor

Publications (2)

Publication Number Publication Date
KR20010102475A true KR20010102475A (en) 2001-11-15
KR100460473B1 KR100460473B1 (en) 2004-12-08

Family

ID=22403347

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2001-7011167A KR100460473B1 (en) 1999-03-02 2000-03-02 Electronic tag assembly and method therefor

Country Status (5)

Country Link
KR (1) KR100460473B1 (en)
CN (1) CN1374993A (en)
AU (1) AU3719000A (en)
CA (1) CA2364448C (en)
WO (1) WO2000052109A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012103203A2 (en) * 2011-01-27 2012-08-02 Texas Instruments Incorporated Frid transponder and method for connecting semiconductor die to antenna

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2828570B1 (en) * 2001-08-09 2003-10-31 Cybernetix METHOD FOR MANUFACTURING CONTACTLESS AND / OR MIXED CHIP CARDS
US7218527B1 (en) 2001-08-17 2007-05-15 Alien Technology Corporation Apparatuses and methods for forming smart labels
US7214569B2 (en) * 2002-01-23 2007-05-08 Alien Technology Corporation Apparatus incorporating small-feature-size and large-feature-size components and method for making same
JP4109039B2 (en) * 2002-08-28 2008-06-25 株式会社ルネサステクノロジ Inlet for electronic tag and manufacturing method thereof
US7224280B2 (en) 2002-12-31 2007-05-29 Avery Dennison Corporation RFID device and method of forming
US6940408B2 (en) * 2002-12-31 2005-09-06 Avery Dennison Corporation RFID device and method of forming
US7253735B2 (en) 2003-03-24 2007-08-07 Alien Technology Corporation RFID tags and processes for producing RFID tags
US7323993B2 (en) * 2004-11-02 2008-01-29 Zih Corp. Variation of conductive cross section and/or material to enhance performance and/or reduce material consumption of electronic assemblies
US7688206B2 (en) 2004-11-22 2010-03-30 Alien Technology Corporation Radio frequency identification (RFID) tag for an item having a conductive layer included or attached
WO2006068286A1 (en) * 2004-12-24 2006-06-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2007108894A (en) * 2005-10-12 2007-04-26 Brother Ind Ltd Tag tape roll-manufacturing device and tag tape roll-manufacturing method
JP4915323B2 (en) * 2006-11-28 2012-04-11 ブラザー工業株式会社 Wireless tag information communication device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5842273A (en) * 1996-01-26 1998-12-01 Hewlett-Packard Company Method of forming electrical interconnects using isotropic conductive adhesives and connections formed thereby
IL119509A (en) * 1996-10-28 2000-02-17 Hi G Tek Ltd Electronic tag
JP3333417B2 (en) * 1997-02-04 2002-10-15 松下電器産業株式会社 IC chip sealing method and device
FR2769389B1 (en) * 1997-10-07 2000-01-28 Rue Cartes Et Systemes De MICROCIRCUIT CARD COMBINING EXTERIOR CONTACT RANGES AND AN ANTENNA, AND METHOD FOR MANUFACTURING SUCH A CARD
US6018299A (en) * 1998-06-09 2000-01-25 Motorola, Inc. Radio frequency identification tag having a printed antenna and method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012103203A2 (en) * 2011-01-27 2012-08-02 Texas Instruments Incorporated Frid transponder and method for connecting semiconductor die to antenna
WO2012103203A3 (en) * 2011-01-27 2012-11-01 Texas Instruments Incorporated Frid transponder and method for connecting semiconductor die to antenna

Also Published As

Publication number Publication date
CN1374993A (en) 2002-10-16
AU3719000A (en) 2000-09-21
CA2364448C (en) 2004-10-26
CA2364448A1 (en) 2000-09-08
WO2000052109A1 (en) 2000-09-08
KR100460473B1 (en) 2004-12-08

Similar Documents

Publication Publication Date Title
EP0439256B1 (en) Electronic device employing a conductive adhesive
KR100382759B1 (en) Method of packaging semiconductor device using anisotropic conductive adhesive
US6051093A (en) Mounting method of semiconductor element
KR100460473B1 (en) Electronic tag assembly and method therefor
US7477194B2 (en) Conductive pattern and method of making
US4804574A (en) Laminated printed coil structure
KR100284725B1 (en) Manufacturing method of chip size package
US6147311A (en) Multi layer circuit board using anisotropic electroconductive adhesive layer and method for producing same
US20040183182A1 (en) Apparatus incorporating small-feature-size and large-feature-size components and method for making same
US6717249B2 (en) Non-contact type IC card and process for manufacturing-same
US6580369B1 (en) Electronic tag assembly and method therefor
US6281048B1 (en) Method of making an electronic component, and an electronic component
US6559523B2 (en) Device for attaching a semiconductor chip to a chip carrier
EP0739579B1 (en) A circuit board with specifically designed connection terminals
US6101098A (en) Structure and method for mounting an electric part
KR100756873B1 (en) The thick copper printed circuit board enhanced adhesive strength and the manufacturing method of it
JPS61118977A (en) Multi-electrode connector construction
MX2008012339A (en) Methods for attaching a flip chip integrated circuit assembly to a substrate.
JPH087957A (en) Connecting method of circuit board and connecting structure body, and adhesive film using for it
JP2901941B2 (en) High frequency power semiconductor device
JPH05297398A (en) Electrode connecting structure
KR20010041051A (en) Data carrier with chip and fully enclosed connection means
JP2002118350A (en) Method for connecting connector to flexible printed circuit board
JP2004062634A (en) Connectless communication device and method for connecting the same
JPS60133789A (en) Circuit board and method of producing same

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20111028

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee