KR20010096309A - Apparatus and method for driving plasma display panel - Google Patents

Abstract

PURPOSE: An apparatus for driving a plasma display panel and a method thereof are provided to prevent a damage of an FET by blocking a wrong driving pulse output or by stabilizing a driving circuit by detecting the abnormality of a control signal output of a control part or a power supply. CONSTITUTION: The apparatus comprises an address electrode driving part(11), a scan electrode driving part(12) and a common electrode driving part(13). A control part(14) outputs a driving pulse to the address electrode driving part and the scan electrode driving part and the common electrode driving part to realize a screen corresponding to input image data. An AND gate(15) performs a logic AND operation of a state verify signal being output through a state verify pin to verify a normal operation of an FPGA(Field Programmable Gate Array) or ASIC in the control part. And a buffer(18) transfers a driving pulse of the control part to a corresponding driving part according to an output of the AND gate.

Description

Plasma display panel driving device and method {APPARATUS AND METHOD FOR DRIVING PLASMA DISPLAY PANEL}

The present invention relates to a plasma display panel, and more particularly, to an apparatus and method for driving a plasma display panel.

In general, PDP is an image display device using gas discharge, and the image quality on the large screen is improved by the recent technology development.

PDPs are roughly classified into direct current driving methods that face large discharges and alternating current methods that perform surface discharges. AC type PDP has the advantages of less power consumption and longer life than DC type, and it discharges every half cycle by applying AC voltage across the dielectric. Subfield method and subframe ( Sub frame).

When representing 256 gray levels, the subfield method time-divisions one frame into eight subfields. Each subfield is time-divided into a reset period for initializing the full screen, an address period for writing data while scanning the full screen in a line-sequential manner, and a sustain period for maintaining the light emission state of cells in which data is written. Here, the reset period and the address period of each subfield are the same in each subfield, whereas each sustain period is a ratio of 2 ⁿ (n = 0,1,2,3,4,5,6,7) according to the luminance relative ratio. The time is allocated to increase. Each subfield implements a gray scale proportional to the corresponding sustain period, and the gray scales implemented in each subfield are combined to express 256 gray scales in one frame.

At this time, since the power consumption during the sustain discharge of the sustain period in the sub-field system has a large problem, an energy recovery circuit for recharging the voltage discharged from the panel to charge the panel.

As shown in FIG. 1, the PDP driving apparatus according to the related art is configured to drive an address electrode driver 1 for driving an address electrode, a scan electrode driver 2 for driving a scan electrode, and a common electrode. The common electrode driver 3 and the received R / G / B image data through gamma correction, gain control, and the like, and process the image data processed on the PDP. The controller 4 generates a driving pulse for driving the scan electrode driver 2 and the common electrode driver 3. The address electrode driver 1, the scan electrode driver 2, and the common electrode are controlled by the controller 4. And a buffer (5) (6) (7) for transmitting the control signal to the driver (3).

As shown in FIG. 2, the address electrode driver 1 of each electrode driver includes a first FET Q1, a second FET Q2, a capacitor C1, and a first and second diode D1 ( An energy recovery circuit composed of D2), a sustain circuit composed of a third FET Q3 and a fourth FET Q4, and a data driving IC 10.

The operation of the PDP driving apparatus configured as described above is as follows.

The controller 4 processes the input image and outputs a predetermined driving pulse through the buffers 5, 6 and 7 to each electrode driver so that the signal processed image data is implemented on the PDP screen.

The detailed operation according to the driving pulse output from the controller 4 will be described by using the address electrode driver 1 as an example. First, the controller 4 outputs an 'E / R-up' pulse so that the first FET Q1 can be used. ) Is turned on and the charged capacitor C1 discharges the charging voltage when the previous PDP panel is discharged, thereby raising the voltage level G applied to the data driving IC 10.

At this time, the controller 4 supplies the 'Sus-DN' pulse to keep the fourth FET Q4 turned on so that the address voltage is not supplied to the data driving IC 10.

Subsequently, the controller 4 outputs a 'Sus-up' pulse to turn on the third FET Q3 when 'G' reaches a predetermined level, thereby supplying an address voltage to the data driving IC 10 to supply 'G'. Is raised to an appropriate level and the state is maintained for a predetermined time.

The controller 4 cuts off the 'Sus-up' pulse to turn off the third FET Q3 and outputs the 'E / R-DN' pulse to turn on the second FET Q2 to discharge the voltage from the panel. This capacitor C1 is to be charged.

Subsequently, when the capacitor C1 is charged to a predetermined level or more, the controller 4 outputs a 'Sus-DN' pulse to turn on the fourth FET Q4 so that the power supply to the data driving IC 10 is cut off. do.

This process is repeated to drive the address electrodes.

In addition, the scan electrode driver 2 and the common electrode driver 3 have a similar configuration, that is, a pair of FETs connected in series is basically configured to drive all the electrodes on one panel.

In the case of the pair of FETs, a driving pulse is output so as not to be turned on at the same time. If a driving pulse is applied to the portion generating the driving pulse, that is, a pair of FETs are simultaneously turned on due to a malfunction of the controller, the FET may be damaged. .

The PDP driving apparatus according to the related art does not detect a driving pulse for turning on the driving FET at the same time due to a malfunction of the control unit or a reason for a sudden power change when the power is turned off. There is a problem that causes damage.

Therefore, the present invention has been made to solve the above-described problems, and by detecting an abnormal control signal output or power supply abnormality of the control unit to block the wrong drive pulse output or to stabilize the driving circuit to prevent damage to the FET It is an object of the present invention to provide a plasma display panel driving apparatus and method.

1 is a block diagram showing the configuration of a general PDP driving apparatus

FIG. 2 is a circuit diagram illustrating a configuration of an address electrode driver of FIG. 1. FIG.

3 is a block diagram showing the construction of a first embodiment of a PDP driving apparatus according to the present invention;

4 is a block diagram showing the configuration of a second embodiment of a PDP driving apparatus according to the present invention;

FIG. 5 is a waveform diagram illustrating an output form of the stabilization signal of FIG. 4. FIG.

6 is a block diagram showing the construction of a third embodiment of a PDP driving apparatus according to the present invention;

Explanation of symbols for main parts of the drawings

11, 21, 31: address electrode driver 12, 22, 32: scan electrode driver

13, 23, 33: common electrode driver 14, 25, 34: control unit

15: Endgate 16-18, 26-28, 35-37: Buffer

24: power off detection unit 41: signal error detection unit

42: safety mode signal generator

The first embodiment of the plasma display panel driving apparatus according to the present invention includes an address electrode driver, a scan electrode driver, a common electrode driver, and an address electrode driver, a scan electrode driver, and a common electrode to implement a screen corresponding to the input image data. The control unit outputs the driving pulse to the drive unit, the AND gate for outputting the result by multiplying the status check signal to check the normal operation of the drive pulse generation logic in the control unit, and the controller is enabled according to the output of the end gate. And a buffer for transmitting the pulse to the corresponding driver.

A second embodiment of the plasma display panel driving apparatus according to the present invention includes an address electrode driver, a scan electrode driver, a common electrode driver, a power off detector for detecting an off of input power and outputting a power off signal, and an input image. Outputting a driving pulse to the address electrode driver, the scan electrode driver and the common electrode driver to implement a screen corresponding to the data, and outputs a control signal for stabilizing the address driver, the scan electrode driver and the common electrode driver when a power-off signal is input. Characterized in that it comprises a control unit.

A third embodiment of the plasma display panel driving apparatus according to the present invention generates a driving pulse for driving an address electrode driver, a scan electrode driver, a common electrode driver, an address electrode driver, a scan electrode driver and a common electrode driver. And a control unit for outputting a safety mode signal when an error of the driving pulse is detected.

Hereinafter, the first to third embodiments of the plasma display panel driving apparatus and method according to the present invention will be described with reference to the accompanying drawings.

3 is a block diagram showing a configuration of a first embodiment of a PDP driving apparatus according to the present invention, FIG. 4 is a block diagram showing a configuration of a second embodiment of a PDP driving apparatus according to the present invention, and FIG. 5 is a stabilization signal of FIG. Fig. 6 is a block diagram showing the configuration of the third embodiment of the PDP driving apparatus according to the present invention.

First Embodiment

According to the first embodiment of the PDP driving apparatus according to the present invention, as shown in FIG. 3, a screen corresponding to the address electrode driver 11, the scan electrode driver 12, the common electrode driver 13, and the input image data is displayed. The controller 14 outputs driving pulses to the address electrode driver 11, the scan electrode driver 12, and the common electrode driver 13 so that the driving pulses are generated in the controller 14, namely, FPGA (Field Programmable). AND gate 15 for multiplying the status check signal outputted through the status check pin for checking the normal operation of the gate array or ASIC and outputting the result, and is enabled according to the output of the AND gate 15. And a buffer 18 for transmitting the driving pulse of the control unit 14 to the corresponding driving unit.

Referring to the operation of the present invention configured as described above are as follows.

The controller 14 processes the input image and outputs driving pulses to the electrode drivers 11, 12 and 13 so that a screen corresponding to the image data is implemented through the PDP.

The AND gate 15 logically multiplies the status check signal output from the status check pin for checking the normal operation state of the FPGA or the ASIC in the controller 14 to enable the buffers 16, 17, and 18. Supply to stage.

At this time, if the state of all the components in the control unit 14 is normal, all of the status check signals are 'high', so the AND gate 15 outputs 'high' and accordingly all the buffers 16, 17, 18 are enabled. Therefore, the driving pulse output from the control unit 14 is normally input to each of the driving units 11, 12 and 13, and normal PDP driving is performed.

Meanwhile, when any one of all the components in the controller 14 is abnormal, that is, when at least one of the status check signals is 'low', the AND gate 15 outputs 'low' and accordingly all buffers 16 ( 17) and 18 are disabled, so that driving pulses output from the control unit 14 are not input to each of the driving units 11 and 12 and 13, thereby preventing damage to the FETs in each driving unit due to driving pulse output errors. .

Second Embodiment

According to the second embodiment of the PDP driving apparatus according to the present invention, as shown in FIG. 4, the address electrode driver 21, the scan electrode driver 22, the common electrode driver 23, and the input power are detected to detect power off. A power-off detector 24 for outputting an off signal and outputting a driving pulse to the address electrode driver 21, the scan electrode driver 22, and the common electrode driver 23 so that a screen corresponding to the input image data is realized. The control unit 25 outputs a control signal for stabilizing the respective driving units when the off signal is input, and buffers 26, 27, 28 for transmitting the driving pulses of the control unit 25 to the corresponding driving units. .

Referring to the operation of the present invention configured as described above are as follows.

The controller 14 processes the input image and displays an E / R-up, E / R-DN, Sus-up, Sus-DN, or IC driving pulse for driving the electrode so that a screen corresponding to the corresponding image data is implemented through the PDP. And so on.

Accordingly, each driver 21, 22, 23 drives the corresponding electrode to perform normal PDP driving.

On the other hand, the power off detection unit 24 compares the input voltage and the predetermined reference voltage, and outputs a 'low' if the input voltage is greater than the reference voltage, otherwise outputs a 'high'.

At this time, if the PDP uses 5V power supply, setting the reference voltage to about 3.5V is suitable for stable operation. When the input power voltage is higher than 3.5V in the state of setting the reference voltage as described above, it outputs 'low' to inform the controller 25 that the power supply is normal, and outputs 'high' when the input power supply voltage drops below 3.5V. The controller 25 is notified of a power failure, that is, power off.

Therefore, when the 'high' signal is output from the power-off detection unit 24, the controller 25 recognizes the power-off, and outputs and drives a stabilization signal of a characteristic level at which the corresponding component can be stabilized as shown in FIG. This is to prevent damage to the FET.

Third embodiment

As shown in FIG. 6, the third embodiment of the PDP driving apparatus according to the present invention has an address electrode driver 31 for driving an address electrode, a scan electrode driver 32 for driving a scan electrode, and a common configuration. The common electrode driver 33 for driving an electrode, the address electrode driver 31, and the scan electrode driver 32 to signal-process input R / G / B image data and to implement the signal-processed image data on a PDP. And a control unit 34 for generating a driving pulse for driving the common electrode driver 33 and outputting a safety mode signal when an error of the driving pulse is detected, and the address electrode driver 31 from the control unit 34. And a buffer 35, 36, 37 for transmitting control signals to the scan electrode driver 32 and the common electrode driver 33.

At this time, the controller 34 checks the driving pulse generated therein and detects a driving pulse in which an error has occurred, that is, a driving pulse for turning on the FET which should not be turned on at the same time, and outputs a detection signal. And outputting a safety mode signal for turning off the corresponding FET when the detection signal is output from the signal error detection unit 41, and outputting the original driving pulse as it is if the detection signal is not output from the signal error detection unit 41. A safety mode signal generator 42 is provided.

Referring to the operation of the present invention configured as described above are as follows.

The controller 34 processes the input image and generates a driving pulse so that a screen corresponding to the image data is implemented through the PDP.

Subsequently, the signal abnormality detecting unit 41 checks whether there is a driving pulse in which an error occurs among the driving pulses, and outputs a detection signal if there is any.

Therefore, when the detection signal is output from the signal abnormality detection unit 41, the safety mode signal generator 42 outputs a safety mode signal for turning off the FET of the corresponding driving unit instead of a driving pulse in which an error occurs. The driving pulse of is output as it is to the corresponding drive part.

PDP driving apparatus and method according to the present invention prevents the output of the wrong drive pulse that can lead to damage of the FET which is a key component for driving the PDP to prevent image degradation, failure, etc. due to the damage of the FET product life cycle And there is an effect that can improve the reliability.

Claims (5)

Address electrode driver, Scan electrode driving unit, Common electrode driver, A controller for outputting driving pulses to the address electrode driver, the scan electrode driver, and the common electrode driver to implement a screen corresponding to the input image data; An AND gate for multiplying a status check signal to check the normal operation of the driving pulse generating logic in the controller and outputting a result; And a buffer configured to be enabled according to the output of the AND gate to transmit driving pulses of the control unit to the corresponding driving unit. Address electrode driver, Scan electrode driving unit, Common electrode driver, A power-off detector for detecting the power supply off and outputting a power-off signal; A control pulse for outputting a driving pulse to the address electrode driver, the scan electrode driver and the common electrode driver so as to implement a screen corresponding to the input image data, and stabilizing the address driver, the scan electrode driver and the common electrode driver when a power-off signal is input; Plasma display panel driving apparatus comprising a control unit for outputting a signal. Address electrode driver, Scan electrode driving unit, Common electrode driver, And a controller for generating a driving pulse for driving the address electrode driver, the scan electrode driver, and the common electrode driver and outputting a safety mode signal when an error of the driving pulse is detected. . The method of claim 3, wherein The control unit A signal abnormality detector which detects a driving pulse error for inspecting a driving pulse generated therein and turns on a FET which should not be turned on at the same time and outputs a detection signal; And a safety mode signal generator for outputting a safety mode signal for turning off the corresponding FET when the detection signal is output from the signal error detection unit, and outputting the original driving pulse as it is if the detection signal is not output from the signal error detection unit. A plasma display panel drive device. In the method of driving a plasma display panel driving apparatus having an address electrode driver, a scan electrode driver, a common electrode driver, and a controller using a field effect transistor (FET) as a driving element, Generating a driving pulse in the address electrode driving unit, the scan electrode driving unit, and the common electrode driving unit such that a screen corresponding to the input image is realized by a controller; Determining whether the driving pulse is a driving pulse error for simultaneously turning on FETs which should not be turned on simultaneously among the FETs of the corresponding driving unit; And outputting a driving pulse for turning off the corresponding FET instead of the driving pulse if the driving pulse error is determined as the result of the determination.