KR100364723B1 - Apparatus and method for driving plasma display panel - Google Patents

Abstract

The present invention relates to a plasma display panel driving apparatus and a method for detecting an abnormal control signal output or a power supply abnormality of a control unit to block an incorrect control signal output or to stabilize a driving circuit to prevent damage to the FET. A control unit for outputting control signals to the address electrode, the scan electrode, and the common electrode driving unit so that a screen corresponding to the input image data can be realized by a driving unit, a common electrode driving unit, and checking whether the logic for generating the control signal in the control unit is normal. And an AND gate for performing an AND operation on the status check signal, and outputting a result value, and a buffer connected to each of the AND gates to enable / disable according to the output of the AND gate, and to transmit the control signal to a corresponding driver. It can improve the life and reliability of the product.

Description

Plasma display panel driving device and method {APPARATUS AND METHOD FOR DRIVING PLASMA DISPLAY PANEL}

The present invention relates to a plasma display panel, and more particularly, to an apparatus and method for driving a plasma display panel.

In general, PDP is an image display device using gas discharge, and the image quality on the large screen is improved by the recent technology development.

PDPs are roughly classified into direct current driving methods that face large discharges and alternating current methods that perform surface discharges. AC type PDP has the advantages of less power consumption and longer life than DC type, and it discharges every half cycle by applying AC voltage across the dielectric. Subfield method and subframe ( Sub frame).

When representing 256 gray levels, the subfield method time-divisions one frame into eight subfields. Each subfield is time-divided into a reset period for initializing the full screen, an address period for writing data while scanning the full screen in a line-sequential manner, and a sustain period for maintaining the light emission state of cells in which data is written. Here, the reset period and the address period of each subfield are the same in each subfield, whereas each sustain period is a ratio of 2 ⁿ (n = 0,1,2,3,4,5,6,7) according to the luminance relative ratio. The time is allocated to increase. Each subfield implements a gray scale proportional to the corresponding sustain period, and the gray scales implemented in each subfield are combined to express 256 gray scales in one frame.

At this time, since the power consumption during the sustain discharge of the sustain period in the sub-field system has a large problem, an energy recovery circuit for recharging the voltage discharged from the panel to charge the panel.

As shown in FIG. 1, the PDP driving apparatus according to the related art scans an address electrode driver 1 to generate a corresponding driving pulse and drives a scan electrode by generating a corresponding driving pulse. The electrode driver 2, the common electrode driver 3 for driving the common electrode by generating a corresponding driving pulse, and the input R / G / B image data are subjected to signal processing through a process such as gamma correction and gain control. A controller 4 generating a control signal to generate driving pulses of the address electrode driver 1, the scan electrode driver 2, and the common electrode driver 3 so that the signal-processed image data is implemented on the PDP; 4, buffers 5, 6, and 7 for transmitting control signals to the address electrode driver 1, the scan electrode driver 2, and the common electrode driver 3 are included.

As shown in FIG. 2, the address electrode driver 1 of each electrode driver includes a first FET Q1, a second FET Q2, a capacitor C1, and a first and second diode D1 ( An energy recovery circuit composed of D2), a sustain circuit composed of a third FET Q3 and a fourth FET Q4, and a data driving IC 10.

The operation of the PDP driving apparatus configured as described above is as follows.

The controller 4 processes the input image and outputs a predetermined control signal through the buffers 5, 6 and 7 to each electrode driver so that the signal processed image data is implemented on the PDP screen.

The detailed operation according to the control signal of the controller 4 will be described using the address electrode driver 1 as an example. First, the controller 4 outputs an 'E / R-up' pulse to thereby operate the first FET Q1. The voltage level G applied to the data driving IC 10 is raised by turning on and causing the charged capacitor C1 to discharge the charging voltage when the previous PDP panel is discharged.

At this time, the controller 4 supplies the 'Sus-DN' pulse to keep the fourth FET Q4 turned on so that the address voltage is not supplied to the data driving IC 10.

Subsequently, the controller 4 outputs a 'Sus-up' pulse to turn on the third FET Q3 when 'G' reaches a predetermined level, thereby supplying an address voltage to the data driving IC 10 to supply 'G'. Is raised to an appropriate level and the state is maintained for a predetermined time.

The controller 4 cuts off the 'Sus-up' pulse to turn off the third FET Q3 and outputs the 'E / R-DN' pulse to turn on the second FET Q2 to discharge the voltage from the panel. This capacitor C1 is to be charged.

Subsequently, when the capacitor C1 is charged to a predetermined level or more, the controller 4 outputs a 'Sus-DN' pulse to turn on the fourth FET Q4 so that the power supply to the data driving IC 10 is cut off. do.

This process is repeated to drive the address electrodes.

In addition, the scan electrode driver 2 and the common electrode driver 3 have a similar configuration, that is, a pair of FETs connected in series is basically configured to drive all the electrodes on one panel.

In the case of the pair of FETs, a control signal is output so as not to be turned on at the same time. If a control signal for generating a control signal, that is, a control signal for simultaneously turning on a pair of FETs due to a malfunction of the controller, the FET may be damaged. .

The PDP driving apparatus according to the related art does not detect a control signal for simultaneously turning on the driving FET due to a malfunction of the control unit or a reason for a sudden power change when the power is turned off. There is a problem that causes damage.

Accordingly, the present invention has been made to solve the above-described problems, and by detecting a control signal output abnormality or a power supply abnormality of the control unit to block the wrong control signal output or to stabilize the driving circuit to prevent damage to the FET. It is an object of the present invention to provide a plasma display panel driving apparatus and method.

1 is a block diagram showing the configuration of a general PDP driving apparatus

FIG. 2 is a circuit diagram illustrating a configuration of an address electrode driver of FIG. 1. FIG.

3 is a block diagram showing the construction of a first embodiment of a PDP driving apparatus according to the present invention;

4 is a block diagram showing the configuration of a second embodiment of a PDP driving apparatus according to the present invention;

FIG. 5 is a waveform diagram illustrating an output form of the stabilization signal of FIG. 4. FIG.

6 is a block diagram showing the construction of a third embodiment of a PDP driving apparatus according to the present invention;

Explanation of symbols for main parts of the drawings

11, 21, 31: address electrode driver 12, 22, 32: scan electrode driver

13, 23, 33: common electrode driver 14, 25, 34: control unit

15: Endgate 16-18, 26-28, 35-37: Buffer

24: power off detection unit 41: abnormal signal detection unit

42: safety mode signal generator

The first embodiment of the plasma display panel driving apparatus according to the present invention controls each of the address electrode, the scan electrode, and the common electrode driver to implement a screen corresponding to the address electrode driver, the scan electrode driver, the common electrode driver, and the input image data. An AND gate for performing a logical multiplication operation on a control unit for outputting a signal and a status check signal for confirming whether the logic for generating the control signal within the control unit is normal, and outputting the result value, and enabling the output according to the AND gate It is characterized in that it is configured to include a buffer is / disabled each connected to transmit the control signal to the corresponding drive unit.

The second embodiment of the plasma display panel driving apparatus according to the present invention corresponds to an address electrode driver, a scan electrode driver, a common electrode driver, a power-off detector for detecting a power-off signal when the external input voltage is less than or equal to a set voltage, and input image data. Each control signal is output to the address electrode driver, the scan electrode driver, and the common electrode driver so that a screen is realized. When the power-off signal is input from the power off detector, the address electrode driver, the scan electrode driver, and the common electrode driver are turned off. It characterized in that it comprises a control unit for controlling.

The third embodiment of the plasma display panel driving apparatus according to the present invention inspects a control signal for driving an address electrode driver, a scan electrode driver, a common electrode driver, an internally generated address electrode driver, a scan electrode driver and a common electrode driver. And a control unit including an abnormal signal detecting unit for detecting an abnormal signal for simultaneously turning on the FET.

Hereinafter, the first to third embodiments of the plasma display panel driving apparatus and method according to the present invention will be described with reference to the accompanying drawings.

3 is a block diagram showing a configuration of a first embodiment of a PDP driving apparatus according to the present invention, FIG. 4 is a block diagram showing a configuration of a second embodiment of a PDP driving apparatus according to the present invention, and FIG. 5 is a stabilization signal of FIG. Fig. 6 is a block diagram showing the configuration of the third embodiment of the PDP driving apparatus according to the present invention.

First Embodiment

According to the first embodiment of the PDP driving apparatus according to the present invention, the address electrode driver 11 for driving the address electrode, the scan electrode driver 12 for driving the scan electrode, and the common electrode are shown in FIG. A controller for outputting control signals to the address electrode driver 11, the scan electrode driver 12, and the common electrode driver 13 so as to realize a screen corresponding to the common electrode driver 13 and the input image data; 14) and receives a control signal in the controller 14, that is, a plurality of status check signals output according to whether or not a field programmable gate array (FPGA) or an ASIC is in a normal state, and performs an AND operation. The output gate and the address electrode driver 11 are enabled / disabled according to the output of the AND gate 15 to transmit the control signal to the corresponding driver 11, 12, 13. Before scan And a buffer 16, 17, 18 connected to the pole driver 12 and the common electrode driver 13, respectively.

Referring to the operation of the present invention configured as described above are as follows.

The controller 14 processes the input image and outputs a control signal to each electrode driver 11, 12, 13 so that a screen corresponding to the image data is implemented through the PDP.

In addition, the AND gate 15 performs an AND operation on a status check signal for checking whether the logic for generating a control signal, such as an FPGA or an ASIC, is normal in the controller 14, and then outputs the result value to each buffer 16 ( It supplies to the enable end of 17) (18).

At this time, if the state of all the components in the control unit 14 is normal, all of the status check signals are 'high', so the AND gate 15 outputs 'high' and accordingly all the buffers 16, 17, 18 are enabled. Therefore, the control signal output from the control unit 14 is normally input to each of the driving units 11, 12 and 13, and normal PDP driving is performed.

Meanwhile, when any one of all the components in the controller 14 is abnormal, that is, when at least one of the status check signals is 'low', the AND gate 15 outputs 'low' and accordingly all buffers 16 ( 17 and 18 are disabled, so that the control signal output from the control unit 14 is not input to each of the driving units 11 and 12 and 13, thereby preventing damage to the FETs in each driving unit due to control signal output errors. .

Second Embodiment

According to the second embodiment of the PDP driving apparatus according to the present invention, as shown in FIG. 4, when the address electrode driver 21, the scan electrode driver 22, the common electrode driver 23, and the external input voltage are less than or equal to the set voltage. Each control signal is output to the address electrode driver 21, the scan electrode driver 22, and the common electrode driver 23 so that a power off detector 24 for outputting a power off signal and a screen corresponding to the input image data are implemented. The controller 25 and the controller may control the address electrode driver 21, the scan electrode driver 22, and the common electrode driver 23 to be turned off when a power-off signal is input from the power-off detector 24. And a buffer 26, 27, 28 for transmitting the control signal of the 25 to the corresponding drive parts 21, 22, 23.

Referring to the operation of the present invention configured as described above are as follows.

The controller 14 processes the input image and displays an E / R-up, E / R-DN, Sus-up, Sus-DN, or IC driving signal for driving an electrode so that a screen corresponding to the corresponding image data is implemented through the PDP. And so on.

Accordingly, each driver 21, 22, 23 drives the corresponding electrode to perform normal PDP driving.

On the other hand, the power off detection unit 24 compares the input voltage and the predetermined reference voltage, and outputs a 'low' if the input voltage is greater than the reference voltage, otherwise outputs a 'high'.

At this time, if the PDP uses 5V power supply, setting the reference voltage to about 3.5V is suitable for stable operation. When the input power voltage is higher than 3.5V in the state of setting the reference voltage as described above, it outputs 'low' to inform the controller 25 that the power supply is normal, and outputs 'high' when the input power supply voltage drops below 3.5V. The controller 25 is notified of a power failure, that is, power off.

Therefore, when the 'high' signal is output from the power-off detection unit 24, the controller 25 recognizes the power-off, and outputs and drives a stabilization signal of a characteristic level at which the corresponding component can be stabilized as shown in FIG. This is to prevent damage to the FET.

Third embodiment

As shown in FIG. 6, the PDP driving apparatus according to the present invention includes an address electrode driver 31, a scan electrode driver 32, a common electrode driver 33, an internally generated address electrode driver, The control unit 34 includes an abnormal signal detection unit 41 for inspecting a control signal for driving the scan electrode driver and the common electrode driver 31, 32, 33 and detecting an abnormal signal for turning on the FET simultaneously. In addition, the control unit 34 outputs the original control signal as it is, if the abnormal signal is not detected by the abnormal signal detecting unit 41, and turns off the corresponding FET when the abnormal signal is detected. It further comprises a safety mode signal generator 42 for outputting a mode signal.

Referring to the operation of the present invention configured as described above are as follows.

The controller 34 processes the input image and generates a control signal such that a screen corresponding to the image data is implemented through the PDP.

Subsequently, the abnormal signal detector 41 checks whether there is an error control signal among the control signals and outputs an abnormal signal if present.

Therefore, the safety mode signal generator 42 outputs a safety mode signal for turning off the FET of the driver instead of the abnormal signal, and otherwise outputs the original control signal to the driver as it is.

PDP driving apparatus and method according to the present invention prevents the output of the wrong control signal itself that can cause damage to the FET which is a key component for driving the PDP to prevent image degradation, failure, etc. due to the damage of the FET product life cycle And there is an effect that can improve the reliability.

Claims (5)

Address electrode driver, Scan electrode driving unit, Common electrode driver, A controller which outputs each control signal to the address electrode, the scan electrode, and the common electrode driver so that a screen corresponding to the input image data is realized; An AND gate which performs an AND operation on a status check signal for checking whether the logic for generating the control signal in the controller is normal, and outputs a result value; And a buffer configured to be enabled / disabled according to the output of the AND gate, and respectively connected to transmit the control signal to a corresponding driver. Address electrode driver, Scan electrode driving unit, Common electrode driver, A power-off detector for detecting a power-off signal when the external input voltage is less than or equal to the set voltage; Each control signal is output to the address electrode driver, the scan electrode driver, and the common electrode driver so that a screen corresponding to the input image data is output. When a power-off signal is input from the power-off detector, the address electrode driver, the scan electrode driver, and the common electrode are common. And a controller for controlling the electrode driver to be turned off. Address electrode driver, Scan electrode driving unit, Common electrode driver, And a control unit including an abnormal signal detection unit for inspecting a control signal for driving an address electrode driver, a scan electrode driver, and a common electrode driver generated therein and detecting an abnormal signal for simultaneously turning on the FET. Plasma display panel drive device. The method of claim 3, wherein The control unit And a safety mode signal generator for outputting an original control signal as it is, and outputting a safety mode signal for turning off the corresponding FET when the abnormal signal is detected. Plasma display panel drive device. In the method of driving a plasma display panel driving apparatus having an address electrode driver, a scan electrode driver, a common electrode driver, and a controller using a field effect transistor (FET) as a driving element, Generating a control signal to be output to the address electrode driver, the scan electrode driver, and the common electrode driver such that a screen corresponding to the input image is realized by the controller; Determining whether the detected control signal is an error when a control signal for turning on the FET which should not be turned on at the same time is detected in the generated control signal; And if the control signal is determined to be an error, outputting a control signal for turning off the corresponding FET instead of the control signal.