KR20010095866A - Immediate frequency processing apparatus for communication system - Google Patents

Abstract

PURPOSE: An apparatus for processing an intermediate frequency in a switching system is provided to flexibly cope with many communication methods by processing a digital signal outputted from a CDMA base station while maintaining the signal as it is, so as to easily vary control parameters for RF transmission. CONSTITUTION: An apparatus for processing an intermediate frequency in a switching system consists of a digital signal processing part(300), a memory(400), a timing control and frequency processing part(500), a PLL(Phase Locked Loop)(600), and a digital/analog converter(700). The digital signal processing part(300) receives a digital signal though the timing control and frequency processing part(500), increases a sampling rate by executing phase equalization using the program data stored in the memory(400), and compensates a phase error. The memory(400) stores the program data for the digital signal processing of the digital signal processing part(300). The timing control and frequency processing part(500) adjusts the timing of the digital signal by a phase-locked signal and outputs it to the digital signal processing part(300). Also the timing control and frequency processing part(500) receives the output signal of the digital signal processing part(300), interpolates the signal, and amplifies the frequency at a required level. The PLL(600) outputs the phase-locked signal to control the digital signal input and output of the timing control and frequency processing part(500). The digital/analog converter(700) converts the output signal of the timing control and frequency processing part(500) into an analog signal.

Description

Intermediate frequency processing device of communication system {IMMEDIATE FREQUENCY PROCESSING APPARATUS FOR COMMUNICATION SYSTEM}

The present invention relates to an intermediate frequency processing apparatus of a communication system, and more particularly, to an intermediate frequency processing apparatus of a communication system capable of digitalizing an analog signal processing apparatus on a transmission path of a CDM base station.

In general, the hardware system of the CDMA Base Station can be divided into the digital processing part and the RF part of the baseband. Currently, the RF part including the intermediate frequency processing part is composed of analog devices.

Recently, in order to improve the flexibility of a communication system, research on an SDR (Software Defined Radio) system for digitally implementing the intermediate frequency processing part has been increasingly active.

Here, the conventional intermediate frequency processing apparatus will be described with reference to the accompanying drawings.

1 is a block diagram showing a configuration of an intermediate frequency processing apparatus of a conventional communication system. A serial / parallel converter 1 for receiving digital data serially from a baseband signal processor and converting them in parallel as shown in FIG. Wow; A digital / analog converter (2) which receives the digital data of the serial / parallel converter (1) and converts the digital data into analog data; A first amplifier (3) for amplifying the analog data output from the digital / analog converter (2) to a predetermined level; A phase equalizer 4 which receives an amplified signal of the first amplifier 3 and equalizes the phase of the amplified signal; A first filter 5 for low pass filtering the output signal of the phase equalizer 4; A mixer (6) for receiving and mixing the filtered signal of the first filter (5) to adjust the frequency of the signal up; A second filter 7 for low pass filtering the output signal of the mixer 6; The operation of the conventional apparatus, which is composed of a second amplifier 8 for amplifying the output signal of the second filter 7 to a predetermined level, will be described.

First, the serial / parallel converter 1 receives digital data (I / Q) serially from the baseband signal processor and converts them in parallel and outputs them, and the digital / analog converter 2 performs the serial / parallel conversion. The digital data of the sub-unit 1 is inputted and converted into analog data.

Thereafter, the first amplifier 3 amplifies and outputs the analog data outputted from the digital / analog converter 2 to a predetermined level, and the phase equalizer 4 of the first amplifier 3 The amplified signal is input to equalize the phase of the amplified signal.

Thereafter, the first filter 5 receives the output signal of the phase equalizer 4 and performs low pass filtering to the mixer 6, so that the mixer 6 receives the first filter 5. The filtered signal of is input and mixed to adjust the frequency of the signal.

At this time, the second filter 7 receives the output signal of the mixer 6 and performs low pass filtering to remove the noise included in the mixer 6 and amplify the noise by a predetermined level through the second amplifying unit 8. The RF unit then transmits the intermediate frequency signal by processing the intermediate frequency signal as an RF signal.

However, the conventional apparatus operating as described above takes a lot of analog components and converts them to analog signals in the intermediate frequency processing step, thereby increasing the circuit area and processing them as analog signals. Due to the large reception and the inability to control the parameters for the phase equalization and the filter, there is a problem in that it cannot flexibly respond to changes in the communication system.

Accordingly, the present invention devised in view of the above-described problems allows the digital signal output from the CDMA BASE STATION to be easily processed while maintaining the digital signal output from the CDMA BASE STATION in order to flexibly respond to various communication methods. It is an object of the present invention to provide an intermediate frequency processing apparatus of a communication system.

1 is a block diagram showing a configuration for an intermediate frequency processing apparatus of a conventional communication system.

Figure 2 is a schematic diagram showing the configuration of the intermediate frequency processing apparatus of the present invention communication system.

Figure 3 is a detailed view showing the configuration of the intermediate frequency processing apparatus of the present invention communication system.

4 is a block diagram showing the configuration of an interpolator in FIG.

5 is a block diagram showing the configuration of a mixer in FIG.

***** Description of the symbols for the main parts of the drawings *****

300: digital signal processing unit 301, 303, 304, 503: interpolator

302: phase equalizer 400: memory

500: Timing control and frequency processor 501,502: Buffer

504: Mixer 600: Fiel

700: digital / analog converter

In order to achieve the above object, the present invention receives a digital signal through a timing control and frequency processing unit to be described later, and digitalizes the digital signal to compensate for the phase error while increasing the sampling rate by performing phase equalization and interpolation of the digital signal. A processing unit; And a timing control and a frequency processor for adjusting the timing of the digital signal and outputting the digital signal to the digital signal processor, interpolating the output signal of the digital signal processor, and amplifying the frequency by a predetermined level.

The digital signal processor may include a memory configured to store program data for digital signal processing.

The timing control and frequency processing unit is characterized in that it comprises a control interface means for controlling the internal parameters for frequency processing and interpolation.

In order to achieve the above object, the present invention receives a digital signal through a timing control and a frequency processing unit to be described later to increase the sampling rate by performing phase equalization and interpolation of the digital signal by program data stored in a memory to be described later. And a digital signal processor for compensating for the phase error; A memory for storing program data for digital signal processing of the digital signal processor; A timing control and frequency processor which adjusts the timing of the digital signal according to a phase synchronization signal, outputs the digital signal to the digital signal processor, receives an output signal of the digital signal processor, interpolates it, and then amplifies a predetermined level of the frequency; PEL for outputting a phase synchronization signal for controlling the digital signal input and output of the timing control and frequency processing unit; And a digital / analog converter configured to receive an output signal of the timing control and frequency processing unit and convert the output signal into an analog signal.

Hereinafter, with reference to the accompanying drawings, the operation and effects of the intermediate frequency processing apparatus of the communication system according to the present invention will be described in detail.

Figure 2 is a block diagram showing a schematic configuration of an intermediate frequency processing apparatus of the present invention, as shown in the digital signal (I / Q) is received through the timing control and frequency processing unit 200 to be described later A digital signal processor 100 for increasing the sampling rate and compensating for the phase error by performing phase equalization and interpolation of the digital signal I / Q; Timing control to adjust the timing of the digital signal (I / Q) to output to the digital signal processing unit 100, and to receive the output signal of the digital signal processing unit 100, interpolate it, and then amplify the frequency to a predetermined level. It consists of a frequency processing unit 200.

Figure 3 is a block diagram showing a detailed configuration of the intermediate frequency processing apparatus of the present invention, as shown in the digital signal (I / Q) is received through the timing control and frequency processing unit 500 to be described later A digital signal processor 300 for increasing the sampling rate and compensating for the phase error by performing phase equalization and interpolation of the digital signal by program data stored in the memory 400 to be described later; A memory 400 in which program data for digital signal processing of the digital signal processor 300 is stored; The timing of the digital signal (I / Q) is controlled by the phase synchronization signal to be output to the digital signal processor 300, and the output signal of the digital signal processor 300 is interpolated, and then the frequency is set to a predetermined level. A timing control and frequency processor 500 for amplifying; PEL (600) for outputting a phase synchronization signal for controlling the digital signal (I / Q) input and output of the timing control and frequency processor 500; A digital / analog converter 700 receives the output signal of the timing control and frequency processor 500 and converts the output signal into an analog signal.

The digital signal processor 300 includes a first interpolator 301 which receives digital data (I / Q) and interpolates it to double the sampling rate; A phase equalizer 302 which receives an output signal of the first interpolator 301 and performs phase equalization for a transmission signal path; The output signal of the phase equalizer 302 is input to interpolate the second and third interpolators 303 and 304 to sequentially double the sampling rate.

The timing control and frequency processor 500 may include a first buffer 501 which receives digital signals I / Q in parallel and buffers them by a phase synchronization signal; A second buffer 502 which receives the digital signal I / Q from the digital signal processor 300 and buffers the digital signal I / Q by using the phase synchronization signal; An interpolator 503 for receiving an output signal of the second buffer 502 and interpolating the output signal to increase a data sampling rate; A mixer 504 that receives the output signal of the interpolator 503 and raises the frequency of the signal, will be described with reference to FIG. 3.

First, the digital signal processor 300 receives the digital signal I / Q through a timing control and frequency processor 500 to be described later, and equalizes the phase of the digital signal by program data stored in the memory 400 to be described later. And increasing the sampling rate by interpolating and compensating for the phase error. That is, the first interpolator 301 receives digital data (I / Q) and interpolates it to double the sampling rate. The phase equalizer 302 receives the output signal of the first interpolator 301 and performs phase equalization on the transmission signal path, and the second and third interpolators 303 and 304 are the phase lamps. The output signal of the video unit 302 is input, interpolated, and the sampling rate is sequentially doubled and output.

In this case, the memory 400 stores program data for processing a digital signal (I / Q).

Thereafter, the timing control and frequency processor 500 receives the digital data from the baseband and adjusts the timing of the digital signal I / Q by using the phase synchronization signal of the PLL 600, thereby adjusting the timing of the digital signal I / Q. In addition to receiving the output signal of the digital signal processing unit 300 and interpolates it, and then outputs by amplifying the frequency a predetermined level, that is,

The first buffer 501 receives the digital signals I / Q in parallel and buffers them by the phase synchronization signal, and outputs the second buffers 502 from the digital signal processing unit 300. ) Is buffered by the phase synchronization signal, interpolated through the interpolator 503 to increase the data sampling rate, and then the frequency is adjusted upward through the mixer 504.

Thereafter, the digital / analog converter 700 converts the output signal of the timing control and frequency processing unit 500 into an analog signal and outputs the analog signal. The RF unit processes the analog signal by a predetermined signal to process an RF signal or an intermediate frequency signal. Send it out.

Here, the detailed operation of each said functional block is demonstrated.

First, the interpolators 301, 303, 304, and 504 are connected to the first adder A1 for adding the first and fourth digital signals Xn and Xn-3 as shown in FIG. 4. And a second adder A2 for adding the second and third digital signals Xn-1 and Xn-2, and an adder signal of the first adder A1, and add a first filter coefficient to the adder signal. a first multiplier M1 that multiplies h0), a second multiplier M2 that receives an add signal of the second adder A2, and multiplies the add signal by a second filter coefficient h1, and the second multiplier A third adder A3 that receives the multiplication signals of the first and second multipliers A1 and A2 and adds the multiplication signals of the first and second multipliers A1 and A2, and shifts the received signals according to the scaling factor. First and second interpolators 10 each including a scaler S, a multiplexer MUX that receives an output signal of the scaler S and the third digital signal Xn-2, and alternately selects and outputs the output signal. ), (11), and the interpolators 301, 303, 304, 504 Perform the same operation as in the following equation.

here, Filter factor

The length of the shock response

That is, the input samples (Xn, Xn-3) and (Xn-1, Xn-2) are bundled together and added to the respective adders A1 and A2, and the outputs of the adders A1 and A2 are respectively added. After adding to multipliers M1 and M2 corresponding to filter coefficients h0 and h1, the result is added again by adder A3, and the addition value is shifted or left to match the scaling factor of scaler S. Output by shifting.

Thereafter, the multiplexer MUX alternately selects and outputs the output signal of the scaler S and the digital signal Xn-2.

In addition, the phase equalizer 302 performs an operation according to the following equation.

here, , Filter coefficients in the form of IIR filters

Input data

Output data

In addition, the mixer 504 receives a digital signal I as shown in FIG. 5 and a first multiplier M3 for multiplying the mixing coefficient and a second multiplier for receiving the digital signal Q and multiplying the digital signal Q. A multiplier M4 and a first adder A4, which receives the output signals of the first and second multipliers M3 and M4 and adds them, are represented by the following equation.

here, Input signal

Output Sampling Rate

Operator to select the real part of the value of: x

In this case, the equation is expressed differently as follows.

Therefore, the mixer 504 is simply implemented as a field programmable gate array (FPGA) as shown in FIG. 5, whereby the actual output of the mixer 504 is .... Q, I, -Q, -I, Q Outputs the sequence of, I, -Q, -I ... and switches the I / Q signals alternately to change the sign.

In other words, the present invention improves the performance of the analog component of the wireless communication system and the performance of the mobile communication system by implementing the intermediate frequency processing so that the digital signal (I / Q) output from the CDMA base station can be processed as it is. .

That is, as described in detail above, the present invention can be implemented while maintaining the digital signal output from the CDMA BASE STATION as it is, thereby reducing the circuit area and reducing the influence on noise. It is possible to flexibly cope and also to improve linearity by easily changing control parameters for RF transmission.

Claims (11)

A digital signal processor which receives a digital signal through a timing control and frequency processor to be described later, phase-equalizes and interpolates the digital signal, increases a sampling rate, and compensates for a phase error; And controlling the timing of the digital signal and outputting the digital signal processor to the digital signal processor, interpolating the output signal of the digital signal processor, and amplifying a predetermined level of the frequency. Intermediate frequency processor of the system. The intermediate frequency processing apparatus of claim 1, wherein the digital signal processor comprises a memory in which program data for digital signal processing is stored. The intermediate frequency processing apparatus according to claim 1, wherein the timing control and frequency processing unit comprises control interface means for controlling internal parameters for frequency processing and interpolation. Digital signal processing unit which receives digital signal through timing control and frequency processing unit which will be described later, and equalizes and interpolates the digital signal by program data stored in memory to be described later to increase sampling rate and compensate for phase error. ; A memory for storing program data for digital signal processing of the digital signal processor; A timing control and frequency processor which adjusts the timing of the digital signal according to a phase synchronization signal, outputs the digital signal to the digital signal processor, receives an output signal of the digital signal processor, interpolates it, and then amplifies a predetermined level of the frequency; PEL for outputting a phase synchronization signal for controlling the digital signal input and output of the timing control and frequency processing unit; And a digital / analog converter configured to receive an output signal of the timing control and frequency processing unit and convert the output signal into an analog signal. 5. The digital signal processing apparatus of claim 4, wherein the digital signal processor comprises: a first interpolator for receiving digital data and interpolating the data to double the sampling rate; A phase equalizer which receives the output signal of the first interpolator and performs phase equalization on a transmission signal path; And a second and a third interpolator configured to receive the output signal of the phase equalizer and interpolate the second signal to sequentially improve the sampling rate. 5. The apparatus of claim 4, wherein the timing control and frequency processing unit comprises: a first buffer which receives the digital signals in parallel and buffers them by the phase synchronization signal; A second buffer which receives the digital signal from the digital signal processor and buffers the digital signal by the phase synchronization signal to output the buffer; An interpolator for receiving an output signal of the second buffer and interpolating the output signal to increase a data sampling rate; And a mixer configured to receive an output signal of the interpolator and increase a frequency of the signal. The intermediate frequency processing apparatus of claim 5, wherein the phase equalizer performs an operation according to the following equation. (Equation 2) here, , Filter coefficients in the form of IIR filters Input data Output data 7. The mixer of claim 6, wherein the mixer comprises: a first multiplier that receives a digital signal and multiplies it with a mixing coefficient; a second multiplier that receives a digital signal and multiplies it with a mixing coefficient; and an output signal of the first and second multipliers. Intermediate frequency processing apparatus of a communication system, characterized in that configured as a first adder for receiving and adding it. 7. The interpolator of claim 5 or 6, wherein the interpolator includes a first adder for adding first and fourth digital signals, a second adder for adding second and third digital signals, and an adder signal for the first adder. A first multiplier that receives an input signal and multiplies the first filter coefficient by the first signal; a second multiplier that receives the add signal of the second adder and multiplies the add signal by a second filter coefficient; and the first and second A third adder which receives a multiplier signal of a multiplier and adds the multiplier, a scaler that receives an add signal of the third adder and shifts the multiplier according to a scaling factor, receives an output signal of the scaler and the third digital signal An intermediate frequency processing apparatus of a communication system, comprising: first and second interpolators each consisting of multiplexers which alternately select and output the multiplexers. 10. The intermediate frequency processing apparatus of claim 8, wherein the mixer performs an operation according to the following equation. (Equation 3) here, Input signal Output Sampling Rate Operator to select the real part of the value of: x 10. The intermediate frequency processing apparatus of claim 9, wherein the interpolation unit performs an operation according to the following equation. (Equation 1) here, Filter factor The length of the shock response