KR20010090171A - Driving circuit of sense amp - Google Patents

Abstract

PURPOSE: A driving circuit of a sense amplifier is provided, which improves operation speed by removing parasitic delay during a read operation of a memory device. CONSTITUTION: A decoder(X-decoder) part(21) decodes an external address input signal(AXi), and a word line driving part(22) drives a plurality of word lines(WL0-WLi) by the decoded signal. A memory cell part(23) comprises a plurality of capacitors and transistors whose gates are connected to the word line and sources or drains are connected to a pair of bit lines(BLT,BLB). A voltage detector part(24) generates a sensing enable trigger signal by sensing the amount of develop of the bit line pair by being connected to the bit line pair of the memory cell part. And, a sense amplifier control part(25) outputs a sense amplifier enable control signal(SAEo) by receiving the sensing enable trigger signal of the voltage detector part and an external bank active signal(BAi) and a memory block selection signal(MSi). A sense amplifier driving part(26) outputs a sense amplifier enable signal by receiving the SAEo signal, and a sense amplifier part(27) is operated by the sense amplifier enable signal of the sense amplifier driving part.

Description

Driving circuit of sense amp

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier circuit, and more particularly, to a driving circuit of a sense amplifier suitable for improving the operation speed by eliminating parasitic delays during a read operation of a memory device.

In general, when a word line is turned on in a memory device, data is developed into a bit line, and when the level of the bit line is stabilized, the sense amplifier is enabled. Sensing data of a bit line.

In this case, a delay time of a certain time is provided between the word line and the sense amplifier for stability of the operation. As a result, there is a limitation in the high speed operation during the read operation of the memory device.

Hereinafter, a driving circuit of a conventional sense amplifier will be described with reference to the accompanying drawings.

1 is a block diagram showing a driving circuit of a conventional sense amplifier.

As shown in FIG. 1, a decoder (X-decoder) unit 11 which receives and decodes an address input signal AXi as an input, and a plurality of word lines WL0, WL1,..., WLi are formed by the decoded signal. A memory cell unit including a word line driver 12 for driving and a plurality of transistors and capacitors each having a gate connected to the word line and a source or a drain connected to a bit line pair BLT and BLB; 13) and a sense amplifier control (S / A) that receives an external bank active signal BAi and a memory block selection signal MSi as inputs and outputs a sense amplifier enable control signal SAEi. a control unit 14, a sense amplifier enable delay unit 15 for delaying and outputting the SAEi signal of the sense amplifier control unit 14 by a predetermined time, and an output signal of the sense amplifier enable delay unit 15 (SAEo) is input to sense amplifier enable signal Consists of a sense amplifier unit (17) for operation by the sense amplifier enable signal for the sense amplifier driving unit 16 and the sense amplifier driving unit 16 for output.

Herein, the configurations of the memory cell unit 13 and the sense amplifier unit 17 will be described in detail.

First, the memory cell unit 13 may include transistors MC1 and MC2 having drains or sources connected to bit lines BLT and bit bar lines BLB having a predetermined interval, and gates connected to word lines WL, respectively; Each of the transistors MC1 and MC2 includes a capacitor C1 and C2 connected between a drain or a source and a ground terminal.

The sense amplifier unit 17 includes a first NMOS having a drain or a source connected to the sense amplifier enable signals CSP and CSN, respectively, and a gate connected to the bit line BLT or the bit bar line BLB in series. A transistor N1, a first PMOS transistor P1, a second NMOS transistor N2, and a second PMOS transistor P2 are formed.

On the other hand, the sense amplifier enable signal CSP is commonly applied to the drains or sources of the first and second PMOS transistors P1 and P2, and to the sources or drains of the first and second NMOS transistors N1 and N2. A sense amplifier enable signal CSN is commonly applied, a bit line BLT is commonly connected to a drain or a source of the first NMOS transistor N1 and the first PMOS transistor P1, and a second NMOS transistor is commonly used. The bit bar line BLB is connected to N2 and the drain or source of the second PMOS transistor P2 in common.

2 is a flowchart illustrating an operation signal of a driving circuit of a conventional sense amplifier.

As shown in FIG. 2, the AXi signal, which is an address signal, operates the word line WL through the decoder 11 and the word line driver 12. In addition, SAEi, a sense amplifier enable signal, is operated by a BAi signal, which is a bank active signal, and an MSi signal, which selects a memory block.

Next, the word line WL is turned on to read data of the memory cell unit 13, and is delayed by a predetermined time (tD) through the sense amplifier enable delay unit 15 until the sense amplifier is operated. This delay period is for WL to be turned on and to transfer the data of the memory cell unit 13 to the bit line stably.

Meanwhile, the SAEi signal, which is the sense amplifier enable signal, generates a SAEo signal delayed for a predetermined time over the sense amplifier enable delay unit 15, and the SAEo signal generates the CSP / CSN signal, which is the signal of the sense amplifier driver 16. Generate.

In response to the CSP / CSN signal, the sense amplifier unit 17 operates and finally senses data of the memory cell unit 13 to perform a read operation.

However, the driving circuit of the conventional sense amplifier as described above has the following problems.

In other words, during the read operation of the memory device, a delay is added to the sense amplifier enable controller to control the word line on-sense amplifier enable timing (CSP / CSN) for a stable operation of the memory device. Secure a stable section as).

Therefore, a delay of an arbitrary tD occurs to add parasitic delay elements, thereby limiting the high speed operation of the memory device.

An object of the present invention is to provide a driving circuit of a sense amplifier to improve the operation speed by eliminating parasitic delays during read operation of a memory device.

1 is a block diagram showing a driving circuit of a conventional sense amplifier.

2 is a flowchart illustrating an operation signal of a driving circuit of a conventional sense amplifier.

3 is a block diagram showing a driving circuit of a sense amplifier according to the present invention.

4 is a flowchart illustrating a driving circuit operation signal of a sense amplifier according to the present invention.

Explanation of symbols for the main parts of the drawings

21: decoder 22: word line driver

23: memory cell portion 24: voltage detector

25: sense amplifier control unit 26: sense amplifier drive unit

27: sense amplifier unit

The driving circuit of the sense amplifier according to the present invention for achieving the above object is a memory cell consisting of a plurality of transistors and capacitors each connected to a source or drain connected to a bit line pair, the gate is connected to a word line, and the memory cell A sense amplifier circuit for receiving and sensing bit line data of a bit and performing read operation, comprising: a decoder unit for receiving an external address input signal as an input, decoding the same, and outputting a plurality of word lines after receiving the decoded signal from the decoder unit; A word detector for driving a voltage line, a voltage detector connected to the bit line and the bit bar line to sense a level of the level up of the pair of bit lines, and outputting a sensing amplifier enable trigger signal; a sensing enable trigger signal and an external signal of the voltage detector; Bank active signal and memory block selection signal And a sense amplifier controller for receiving a sense amplifier enable control signal and receiving a sense amplifier enable control signal of the sense amplifier controller as an input and outputting a sense amplifier enable signal to drive the sense amplifier unit. It is characterized by.

Hereinafter, a driving circuit of a sense amplifier according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram showing a driving circuit of a sense amplifier according to the present invention.

As shown in FIG. 3, a decoder (X-decoder) 21 for receiving and decoding an external address input signal AXi as an input and a plurality of word lines WL0, WL1,..., WLi by the decoded signal. Memory cell including a word line driver 22 driving a plurality of transistors and a capacitor having a gate connected to the word line and a source or a drain connected to a bit line pair BLT and BLB, respectively. A sensing enable trigger (SV) is connected to the unit 23 and the bit line pairs BLT and BLB of the memory cell unit 23 to sense the development amount ΔV of the bit line pairs BLT and BLB. a voltage detector 24 generating a sensing enable trigger signal, a sensing enable trigger signal of the voltage detector 24, an external bank active signal BAi, and a memory block ) Sense Amplifier Enable Control Signal (SAEo) A sense amplifier control unit 25 for outputting, a sense amplifier driver 26 for receiving a SAEo signal from the sense amplifier control unit 25 as an input and outputting a sense amplifier enable signal, and the sense amplifier And a sense amplifier 27 that operates by the sense amplifier enable signal of the driver 26.

Herein, the configurations of the memory cell unit 23 and the sense amplifier unit 27 will be described in more detail.

First, each of the memory cell units 23 includes transistors MC1 and MC2 having drains or sources connected to bit lines BLT and bit bar lines BLB at regular intervals, and gates connected to word lines. And capacitors C1 and C2 connected between the drain or source of the MC1 and MC2 and the ground terminal.

The sense amplifier unit 27 includes a first NMOS having a drain or a source connected to the sense amplifier enable signals CSP and CSN, respectively, and a gate connected to the bit line BLT or the bit bar line BLB in series. A transistor N1, a first PMOS transistor P1, a second NMOS transistor N2, and a second PMOS transistor P2 are formed.

On the other hand, the sense amplifier enable signal CSP is commonly applied to the drains or sources of the first and second PMOS transistors P1 and P2, and to the sources or drains of the first and second NMOS transistors N1 and N2. A sense amplifier enable signal CSN is commonly applied, a bit line BLT is commonly connected to a drain or a source of the first NMOS transistor N1 and the first PMOS transistor P1, and a second NMOS transistor is commonly used. The bit bar line BLB is connected to N2 and the drain or source of the second PMOS transistor P2 in common.

4 is a flowchart illustrating a driving circuit operation signal of a sense amplifier according to the present invention.

As shown in FIG. 4, the AXi signal, which is an address (Adress) signal, operates the word line WL through the decoder unit 21 and the word line driver 22.

In addition, the sense amplifier controller 25 is enabled by the BAi signal that is the bank active signal and the MSi signal that selects the memory block, and the voltage detector 24 connected to the bit line pairs BLT and BLB of the memory cell unit 23. The sensing amount ΔV of the bit line pair is sensed to generate a SAETRIG signal, which is a sensing enable trigger signal, and the sense amplifier controller 25 is operated by the SAETRIG.

When the BAi, MSi, and SAETRIG signals are input to the sense amplifier controller 25, the SAEo signals are outputted by the signals, and the SA signals operate by operating the CSP / CSN, the sense amplifier enable signal, in the memory cell unit 23. The bit line data is sensed to perform a read operation of the memory cell unit 23.

As described above, the driving circuit of the sense amplifier according to the present invention has the following effects.

First, when the word line is turned on and the data of the memory cell is applied to the bit line by charge sharing, the sensed amplifier driver is operated by sensing the amount of the bit line developed signal to operate the data of the memory. Sensing can automatically achieve stable operation of memory devices.

Second, since parasitic delays can be eliminated during read operation of the memory device, the operating speed of the memory device can be improved.

Claims (1)

In a sense amplifier circuit for sensing and performing a read operation by receiving a sense of the bit line data of the memory cell consisting of a plurality of transistors and capacitors connected to a source line or a drain connected to a word line and a gate line, respectively; , A decoder to receive an external address input signal as an input, decode and output the same; A word line driver for receiving a decoded signal from the decoder to drive a plurality of word lines; A voltage detector connected to the bit line and the bit bar line to sense a development amount of a pair of bit lines and output a sensing amplifier enable trigger signal; A sense amplifier controller configured to receive a sensing enable trigger signal of the voltage detector, an external bank active signal, and a memory block selection signal as inputs, and output a sense amplifier enable control signal; And a sense amplifier driving unit which receives the sense amplifier enable control signal of the sense amplifier control unit as an input and outputs a sense amplifier enable signal to drive the sense amplifier unit.