KR100498186B1 - Pseudo SRAM with page active circuit for preventing malfunction of data reading - Google Patents

Abstract

A row driver for detecting a transition of the address signal and enabling the word line signal; A global data bus line and global data for a page address transition detection unit for detecting a page address transition signal and outputting a page address transition detection signal, the page address transition detection signal inputted thereafter, and a page address transition detection signal inputted thereafter; A column drive section including a page active signal generation section for generating a page active signal having a pulse section for sufficiently precharging the bus bar line, and a column signal control section for enabling a column selection signal with respect to the input of the page active signal; A pseudo S RAM is provided.

Description

Pseudo SRAM with page active circuit for preventing malfunction of data reading

The present invention relates to a pseudo S-RAM having a page active circuit for preventing a malfunction of a data read of the pseudo S-RAM. More particularly, the present invention relates to a pseudo S-RAM having a skew between page addresses during a page read operation of the pseudo S-RAM. The present invention relates to a pseudo S-RAM having a page active circuit for preventing a malfunction of a data read generated when a page address is briefly transitioned due to skew or a wrong input.

Hereinafter, the data read operation of the pseudo S RAM will be described.

FIG. 1 shows a read timing diagram of a pseudo S RAM having an eight page (A0 to A7) mode for explaining the data read operation of the pseudo S RAM.

As shown in FIG. 1, the address signals (address 3 to 20) when the chip select signal / CS is low, the write enable signal / WE is high, and the output enable signal / OE is low. ) And the page address signal (page address 0 to 2) to perform a data read operation. Here, the page address signals (page address 0 to 2) are included in the column address signals as the page address signals, and the address signals (address 3 to 20) are the column address signals and the row address signals except for the page address signals. When the address signals address 3 to 20 including the row address signal transition, the address signal transition detection circuit in the row path is detected to generate a row active signal row_atv, and the row active signal row_atv is The word line signal WL is generated to enable the word line corresponding to the row address. In addition, when the page address signals (page addresses 0 to 2) transition, the page address signal transition detection circuit in the column path is detected and generates a page active signal page_atv, and the page active signal page_atv is a column. The data Dout is output by enabling the selection signal Yi.

Thereafter, only the page address signals (page addresses 0 to 2) are changed while the word line signal WL is enabled to generate eight different column selection signals Yi to proceed with the eight-page read operation.

As described above, the first read operation is performed by enabling the word line, which is the row address, and the bit line, which is the column address, but the page read operation is performed with the operation of the column address with the word line, which is the row address, enabled. As described above, the page read operation is performed only by the transition of the page address signals (page address 0 to 2). As shown in FIG. 1, the page lead cycle tPRC and the page address access time tPAA are read cycles of about 25 ns. The data Dout1 to Dout7 can be output faster than 70ns of the tRC and the address access time tAA.

As described above, the page lead cycle tPRC is about 25 ns, so that the page address signal (page address 0 to 2) should transition after at least 25 ns. However, when a page address skew occurs or an incomplete page address read signal is input, an incorrect data read operation is performed as described below.

Fig. 2 shows a page read simulation timing diagram of a conventional pseudo S-RAM in which a malfunction occurs in the data read operation when the page address is shortly transitioned.

As shown in Fig. 2, when the page address signals (page address 0 to 2) are shortly transitioned like the address A1, any success or failure of the read for the shortly changed invalid address A1 is any. It doesn't matter, but the read for the next valid address A2 should be done properly. However, as described below, the problem is caused by not performing properly.

When the page address signal (page address 0 to 2) corresponding to the addresses A0 to A3 transitions, the page address transition detection signal atdsum_pg is enabled in the column path, and the page address transition detection signal atdsum_pg ) Enables the page active signal page_atv, and the page active signal page_atv enables the column selection signals Yi0, Yi1, Yi2, and Yi3. In this case, for example, when the cell data corresponding to the addresses A0, A1, A2 and A3 are high, low, high and low, the page address signal corresponding to the addresses A0 to A3 (page address 0). Data to be output by enabling the column select signal Yi in accordance with the transition of ˜2) should be read high, low, high and low.

However, in the above-described case, the address A1 is shortly transitioned due to the skew of the page address or the input of the wrong read, thereby enabling the column selection signals Yi1 and Yi2 too close, thereby enabling the global data bus lines GDBline, GDBBline) is not precharged enough. As described above, the data read by the column select signal Yi2 outputs incorrect data Dout because the global data bus lines GDBline and GDBBline are not sufficiently precharged. Output incorrectly).

As described above, the reason why the global data bus lines GDBline and GDBBline are not sufficiently precharged will be described below with reference to FIG. 3. FIG. 3 is a simulation timing diagram illustrating a case in which global data bus lines are incompletely precharged in FIG. 2.

As shown in FIG. 3, the global data bus line precharge signal gdb_pcg is initially low, and after the global data bus lines GDBline and GDBBline are precharged, before the column selection signal Yi1 is enabled. The precharge must be stopped with a high margin in advance. This is because the voltage difference between the global data bus lines GDBline and GDBBline does not occur when the precharging continues while the column select signal Yi1 is enabled.

When the global data bus line precharge signal gdb_pcg becomes high and the precharge of the global data bus lines GDBline and GDBBline stops, and the column selection signal Yi1 is enabled, the global data bus lines Cell data is loaded on (GDBline, GDBBline) so that the potential difference between the global data bus lines (GDBline, GDBBline) increases. In this case, when the global data bus lines GDBline and GDBBline have a voltage difference by a predetermined potential difference (B in Fig. 3), the data bus line sense amplification signal dbsa_stb is enabled to detect the potential difference and then the global I / Output data to O (GIO) line. After the column selection signal Yi1 is disabled, the global data bus line precharge signal gdb_pcg goes low after a predetermined margin, and precharges the global data bus lines GDBline and GDBBline. do. Thereafter, before the column select signal Yi2 is enabled, the precharge is stopped again by going high with a predetermined margin.

However, as shown in FIG. 3, the global data bus line precharge signal gdb_pcg is “low” because the section (ⓓ in FIG. 3) to precharge the global data bus lines GDBline and GDBBline is too short. By not being able to pre-charge the global data bus lines (GDBline, GDBBline), it will output incorrect data to the global I / O (GIO).

That is, when the page address changes too short, as described above, different column selection signals Yi1 and column selection signals Yi2 are enabled too close to precharge the global data bus lines GDBline and GDBBline. Since the period ⓓ is too short or not generated, the global data bus lines GDBline and GDBBline may not be precharged incompletely or precharged to output incorrect data.

Accordingly, an object of the present invention is to prevent incomplete precharge between global data bus lines that occurs when a page address is shortly transitioned due to skew or incorrect read input between page addresses during a page read operation of a pseudo S-RAM. It is to provide a pseudo S RAM that can.

Another object of the present invention is to provide a pseudo S-RAM which can prevent the reading of incorrect data that occurs when the page address is shortly shifted due to skew or incorrect read input between page addresses during the page read operation of the pseudo S-RAM. To provide.

In the above-described conventional pseudo SRAM, incomplete precharge between global data bus lines that occurs when the page address is shortly transitioned due to skew or incorrect read input between the page addresses during the page read operation is prevented. In order to be able to perform a read operation of data, the pseudo S RAM according to the present invention is as follows.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a row driver for enabling a word line signal by detecting a transition of an address signal; A global data bus line and global data for a page address transition detection unit for detecting a page address transition signal and outputting a page address transition detection signal, the page address transition detection signal inputted thereafter, and a page address transition detection signal inputted thereafter; A column drive section including a page active signal generation section for generating a page active signal having a pulse section for sufficiently precharging the bus bar line, and a column signal control section for enabling a column selection signal with respect to the input of the page active signal; A pseudo S RAM is provided.

In the pseudo S-RAM, the page active signal generation unit outputs a first page output signal having a first or second reference level with respect to the input page address transition detection signal and the first feedback signal input. Control unit; A next page signal controller configured to output a second output signal having a first or second reference level with respect to the input of the second feedback signal and the third feedback signal; Logic means for outputting a third output signal of a second reference level when the first output signal of the page address transition detection signal controller and the second output signal of the next page signal controller are signals of a first reference level; A column reset signal / page active signal generator for outputting a page active signal having a pulse interval of a first reference level and the first feedback signal when the third output signal of the logic means is a second reference level; And a next page signal configured to output the second feedback signal in which the page active signal is delayed by a second delay time and the third feedback signal in which the page active signal is delayed by a third delay time, to the input of the first feedback signal. It is preferable to include a page active delay signal generator.

The page address transition detection signal controller may enable the input of the page address transition detection signal of the first reference level to the input of the first feedback signal having the first reference level. First switching means for outputting a signal having a second reference level, disabling the input of the page address detection detection signal to the input of the first feedback signal having a second reference level, and outputting a signal having a first reference level; First latch means for latching and outputting the output signal of the switching means; And outputs a signal having a second reference level after outputting a signal having a first reference level for a first delay time with respect to the signal having the first reference level of the first latching means, and outputting a signal having a second reference level. It is preferable to include a first delay means for outputting a signal having a first reference level to a signal having a second reference level of the latch means.

In the pseudo S-RAM, the next page signal controller is the third feedback signal with respect to the input of the second feedback signal having the first reference level while the power-up signal having the first reference level is input. Disabling the output signal of the first reference level and enabling the input of the third feedback signal with respect to the input of the second feedback signal having the second reference level to output the signal of the second reference level Switching means; It is preferable to include a second latch means for latching and outputting the output signal of the switching means.

Further, in the pseudo S-RAM, the column reset signal / page active signal generator generates a pulse having a pulse section of the first reference level when the third output signal of the logic means is a second reference level. ; First inverter means for inverting the signal output from the pulse generator to output the first feedback signal; And second inverter means for inverting the signal output from the first inverter means to output the page active signal.

In addition, the pseudo S-RAM, the next page signal / page active delay signal generation unit third inverter means for inverting the input of the first feedback signal input; Second delay means for delaying the signal output from the third inverter means by a second delay time to output the second feedback signal; And third delay means for outputting the third feedback signal by delaying the signal output from the second delay means by a third delay time.

In the pseudo S-RAM, the first reference level and the second reference level are preferably high and low signals, respectively.

In the pseudo S-RAM, the first, second and third feedback signals are preferably column reset signals, page active delay signals, and next page signals.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 4 is a timing diagram of page read simulation of a pseudo S RAM according to an exemplary embodiment of the present invention for preventing a malfunction of data reads when a page address is shortly shifted. FIG. 5 is a malfunction of data reads in FIG. 4. This is a simulation timing diagram that improves the precharge operation to prevent the problem.

As shown in Figs. 4 and 5, in the case of the page read operation of the pseudo S RAM according to the preferred embodiment of the present invention, when the page address signals (page address 0 to 2) are shortly transitioned like the address A1. In order for the read operation for the next valid address A2 to operate normally, the global data bus line precharge signal gdb_pcg should precharge the global data bus lines GDBline and GDBBline (see FIG. 5). Ⓓ) is set to allow margin.

That is, as shown in FIG. 3, when the page address signals (page address 0 to 2) corresponding to the addresses A0 to A3 are transitioned, the page address transition detection signal atdsum_pg is enabled in the column path. The page address transition detection signal atdsum_pg enables the page active signal page_atv, and the page active signal page_atv enables the column selection signals Yi0, Yi1, Yi2, and Yi3. At this time, as shown in FIG. 5, the global data bus line precharge signal gdb_pcg is initially low, and after the global data bus lines GDBline and GDBBline are precharged, the column selection signal Yi1 is set to IN. It stops precharge by going high with a margin before it is enabled. Thereafter, the column select signal Yi1 is enabled, and thus the potential difference between the global data bus lines GDBline and GDBBline increases. As such, when a voltage difference occurs between the global data bus lines GDBline and GDBBline by a predetermined potential difference (B in FIG. 5), the data bus line sense amplification signal dbsa_stb is enabled to detect the potential difference and then the global I Output data to / O (GIO) line. After the column selection signal Yi1 is disabled, the global data bus line precharge signal gdb_pcg goes low after a predetermined margin, and precharges the global data bus lines GDBline and GDBBline. do. Thereafter, before the column select signal Yi2 is enabled, the precharge is stopped again by a high margin with a predetermined margin.

As described above, the global data bus line precharge signal gdb_pcg is maintained to be “low” during the precharge period (ⓓ in FIG. 5) to sufficiently precharge the global data bus lines GDBline and GDBBline.

Therefore, even if the page address changes too short, a sufficient period ⓓ for precharging the global data bus lines GDBline and GDBBline can be obtained to sufficiently precharge the global data bus lines GDBline and GDBBline. Can be. In this way, the global data bus lines GDBline and GDBBline are sufficiently precharged, so that the data read by the column select signal Yi2 normally outputs the data Dout. Therefore, as shown in FIG. 4, for example, when the cell data corresponding to the addresses A0, A1, A2, and A3 are high, low, high, and low, pages corresponding to the addresses A0 to A3. Data to be output by enabling the column selection signal Yi in response to the transition of the address signals page address 0 to 2 may be normally output to high, low, high and low through the global I / O (GIO).

As described above, even if the page address changes too short, sufficient interval ⓓ to precharge the global data bus lines GDBline and GDBBline is sufficient to precharge the global data bus lines GDBline and GDBBline. The configuration of the circuit which can be made will be described below.

6 is a block diagram of a page read operation unit of a pseudo S RAM according to an exemplary embodiment of the present invention.

As shown in FIG. 6, the page read operation unit 10 of the pseudo S RAM according to an exemplary embodiment of the present invention may include an address buffer 100 and a page address signal to which address signals address 3 to 20 are input. A page driver buffer 200 to which ˜2) is input, and a row driver for inputting signals output from the address buffer 100 and the page address buffer 200 to generate enable signals for word lines and column lines, respectively. It consists of a 300 and the column driving unit 400. Here, the row driver 300 includes an address transition detector 310, a low active signal generator 320, and a low signal controller 330, and the column driver 400 includes a page address transition detector 410 and a page active. The signal generator 420 and the column signal controller 430 are provided. The configuration of the page read operation unit 10 and the read operation of the page mode will be described in detail as follows.

After the address signals address 3 to 20 are inputted to the address buffer 100, the address signals add 3 to 20 are output to the address transition detection unit 310, and the low address signal add 7 among the address signals add 3 to 20 is output. 20 and the column address signals add3 to 6 are outputted to the row signal controller 330 and the column signal controller 430, respectively. The address transition detection unit 310 detects any one of the input address signals add3 to 20 and generates an address transition detection signal atdsum and outputs it to the low active signal generation unit 320. The low active signal generator 320 generates a low active signal row_atv based on the input address transition detection signal atdsum and outputs it to the low signal controller 330, and also generates an address signal add_stb and an address buffer. Output to (100). As such, the low active signal row_atv output from the low active signal generator 320 and the low address signals add7 to 20 output from the address buffer 100 are transferred to the low signal controller 330 of the row driver 300. An input is enabled to enable the word line WL.

In the state where the word line WL is enabled as described above, the column address signals add3 to 6 of the address signals add3 to 20 output from the address buffer 100 are the column signal control unit 430 of the column driver 400. Will be printed). In addition, the page address signals (page address 0 to 2) are input to the page address buffer 200 and then output to the page address transition detection unit 410 and the column signal control unit 430. The page address transition detection unit 410 detects any one of the input page address signals add0 to 2 and generates a page address transition detection signal atdsum_pg and outputs it to the page active signal generation unit 420. . The page active signal generator 420 generates a page active signal page_atv based on the input page address transition detection signal atdsum_pg and outputs it to the column signal controller 430. In this way, the column address signals add3 to 6 output from the address buffer 100, the page address signals add0 to 2 output from the page address buffer 200, and the page active signal generation unit 420 are output. The page active signal page_atv is input to the column signal controller 430 of the column driver 400 to enable the column line Yi.

As described above, the page address signals (page address 0 to 2) are transitioned in the state where the word line WL is enabled, and eight different column lines Yi are enabled to quickly output data of a cell. .

In the page read operation of the page read operation part of the pseudo S RAM, when the page address is shortly transitioned due to skew or incorrect read input between the page addresses during the page read operation, the global data bus lines are generated. The page active signal generator 420 of FIG. 6 to prevent incomplete precharge will be described in detail below.

7 is a page active circuit diagram of a page read operation unit of a pseudo S RAM according to an exemplary embodiment of the present invention. 8A and 8B are waveform diagrams showing a circuit diagram of the pulse generator of FIG. 7 and input / output thereof, and FIGS. 9A and 9B are waveform diagrams showing a circuit diagram of the first delay circuit portion of FIG. 7 and input / output thereof. 10A and 10B are waveform diagrams illustrating a circuit diagram of the second delay circuit unit of FIG. 7 and input / output thereof, and FIGS. 11A and 11B are waveform diagrams illustrating a circuit diagram of the third delay circuit unit of FIG. 7 and input / output thereof. .

As shown in FIG. 7, the page active signal generator 420 includes a next page signal controller 421 for controlling an input next page signal page_next, a column reset signal reset_col, and a page address transition detection signal atdsum_pg. Logically combines the signals output from the page address transition detection signal controller 422, the next page signal controller 421, and the page address transition detection signal controller 422 by controlling the page address transition detection signal atdsum_pg by the A column reset signal / page active signal generator 423 which receives a signal output from the NAND gate ND1 and the NAND gate ND1 and outputs a column reset signal and a page active signal page_atv, and an input column reset And a next page signal / page active delay signal generator 424 for outputting the next page signal page_next and the page active delay signal page_atv_d by the signal reset_col. .

Here, the next page signal controller 421 includes an inverter INV4 to which the next page signal page_next is input, a NAND gate ND0 to which a signal output from the inverter INV4 and a power up signal pwrup are input, and a NAND gate. Inverter INV5 for inverting the signal output from ND0, a drain connected to a power supply terminal, and a drain from a source of PMOS transistor P2 and PMOS transistor P2 whose output from inverter INV5 is input to the gate. A NMOS transistor N2 and a drain connected to a source of an NMOS transistor N2 and an output of an inverter INV5 connected to a gate thereof, a page active delay signal page_atv_d is input to a gate, and a source is grounded. (N3), a latch composed of an inverter (INV6) and an inverter (INV8) located between the contacts of the PMOS transistor (P2) and the NMOS transistor (N2) and the input terminal of the inverter (INV7) that outputs a signal to the NAND gate (ND1). Roy (421a) Eojinda.

On the other hand, the page address transition detection signal control unit 422 has a drain connected to a power supply terminal, a PMOS transistor P0 having a column reset signal reset_col input to a gate, a drain connected to a power supply terminal, and a power-up signal pwrup connected to a power supply terminal. PMOS transistor P1 and column reset signal reset_col input to the gate are input to the gate, and NMOS transistors N0 and NMOS transistors N0 having drains connected to the sources of PMOS transistor P0 and PMOS transistor P1. The drain is connected between the drain of the NMOS transistor N1, the inverter INV1, the NMOS transistor N0, and the inverter INV1 having the drain connected to the source of the source and the page address transition detection signal atdsum_pg input to the gate. A latch 422a comprising an INV0 and an inverter INV2, and a first delay circuit 422b connected to an output terminal of the inverter INV1 and outputting a signal to the NAND gate ND1.

The column reset signal / page active signal generator 423 is connected to the pulse generator 423a to which the signal output from the NAND gate ND1 is input and the output terminal of the pulse generator 423a to receive the column reset signal reset_col. The inverter INV9 outputs, the inverter INV10 connected to the output terminal of the pulse generator 423a, and the inverter INV11 connected to the output terminal of the inverter INV10 and outputs the page active signal page_atv.

The next page signal / page active delay signal generator 424 is connected to an output terminal of the inverter INV3 and the inverter INV3 to which the column reset signal reset_col is input and outputs a next page signal page_next. It consists of three delay circuits 424a and 424b. In this case, the page active delay signal page_atv_d is output at the contact between the second delay circuit 424a and the third delay circuit 424b.

Meanwhile, as shown in FIG. 8A, the pulse generator 423a includes a delay path composed of MOS capacitors and an odd number of inverters connected thereto, and a NOR gate NOR0. Here, the output of the NAND gate ND1 is directly input to one input terminal of the NOR gate NOR0, and the signal input from the NAND gate ND1 is input to the type force terminal of the NOR gate NOR0. It is input via a delay path consisting of MOS capacitors and an odd number of inverters connected thereto.

That is, as shown in FIG. 8B, when the input is "low", the pulse generator 423a outputs the "high" section immediately by the NOR gate NOR0, and then the input "low" signal is received. Via a delay path consisting of an odd number of MOS capacitors and an odd number of inverters connected thereto, the signal is delayed by a predetermined delay time and inputted to the NOR gate NOR0, thereby outputting a "low section". On the contrary, when the input of the pulse generator 423a is "high", it is output as "low" by the NOR gate NOR0.

In addition, as shown in FIG. 9A, the first delay circuit 422b of the page address transition detection signal controller 422 has a MOS capacitor connected to an even number of inverters and one input terminal thereof connected thereto, and a one input signal is connected to the type force stage. A delay path comprising a plurality of NAND gates applied and connected to an output terminal, and a NAND gate ND2 to which a type force signal and an output signal of the delay path are input.

That is, as shown in FIG. 9B, the first delay circuit 422b outputs "high" by the NAND gate ND2 when the input is "low", whereas the first delay circuit 422b outputs the "high" when the input is "high". The MOS capacitor charged to " low " in the delay path of 422b becomes " high " for a predetermined delay time (i section) and then outputs to " low ".

Also, as shown in FIGS. 10A and 11A, the second delay circuit 424a and the third delay circuit 424b of the next page signal / page active delay signal generator 424 may be disposed between a pair of inverters. A plurality of delay paths to which the MOS capacitors are connected are provided. Accordingly, as shown in FIGS. 10B and 11B, the second delay circuit 424a and the third delay circuit 424b connect the input signals as shown in FIGS. 10A and 11A to the second delay circuit 424a and the third. The delay is delayed by a predetermined delay time (a section) in proportion to the number of delay paths of the delay circuit 424b.

Hereinafter, an operation of the page active circuit of the page read operation unit of the pseudo S RAM according to an exemplary embodiment of the present invention will be described.

12 is a simulation timing diagram for the page active circuit (420 in FIG. 7) of the pseudo S RAM according to the preferred embodiment of the present invention.

First, when the first power-up signal pwrup is low, as illustrated in FIG. 12, the PMOS transistor P1 and the PMOS transistor P2 are turned on to latch the node A to a high level, and the node B is latched high. Latch (Node B) low. At this time, since the Node B is low, the column reset signal reset_col generated through the NAND gate ND1, the pulse generator 423a, and the inverter INV9 is latched high, and the page active signal ( page_atv) is latched low to disable. The column reset signal reset_col latched high is input to the PMOS transistor P0 and the NMOS transistor N0 of the page address transition detection signal controller 422 to keep the NMOS transistor N0 on. In addition, the column reset signal reset_col latched high at this time is input to the inverter INV3 of the next page signal / page active delay signal generator 424 and passes through the second delay circuit 424a, thereby providing a page active delay signal. Create (page_atv_d) low and output it. The page active delay signal page_atv_d outputted as described above is input to the NMOS transistor N3 of the next page signal controller 421 to turn off the NMOS transistor N3. In this state, the next next page signal page_next of the row output from the third delay circuit 424b of the next page signal / page active delay signal generator 424 is inputted to the inverter INV4 and is connected to the NAND gate ND0. Keep the input high.

After that, when the power-up signal pwrup becomes high, the PMOS transistor P2 is turned off and the NMOS transistor N2 is turned on. However, since the page active delay signal page_atv_d is kept low, the NMOS transistor N3 is turned off to keep the node A continuously high. At this time, the Node B is low, the column reset signal reset_col is high, the page active signal page_atv, the page active delay signal page_atv_d, and the next page signal page_next are all low.

In this state, when the page address signals (page address 0 to 2) transition, the page address transition detection unit (see 410 in FIG. 6) detects this and generates the enabled page address transition detection signal (atdsum_pg) to generate the page address transition detection signal. Input to the NMOS transistor N1 of the control unit 422. The page address transition detection signal atdsum_pg of the input enable turns on the NMOS transistor N1. At this time, since the NMOS transistor N0 and the NMOS transistor N1 are on, the node C becomes low, and is subsequently inputted through the inverter INV0 and the inverter INV1 to the first delay circuit 422b. In this case, as shown in FIGS. 9A and 9B, a low signal is input to the first delay circuit 422b, thereby outputting the node B (FIG. 12) high by the NAND gate ND2. On the other hand, at this time, since Node A is kept high, the output of NAND gate ND1 becomes low and is input to pulse generator 423a. In this case, as shown in FIGS. 8A and 8B, when the low signal is input to the pulse generator 423a, the low signal input to the pulse generator 423a and the delay path of the pulse generator 423a The high signal at is first inputted to the NOR gate NOR0 and output high, and then a predetermined delay time is set on the low signal inputted to the pulse generator 423a and the delay path of the pulse generator 423a. The high signal delayed by ⓕ section is input to the NOR gate (NOR0) to output a low signal. In this way, the pulse generator 423a generates and outputs a pulse having a pulse width corresponding to a predetermined delay time (? Section) by the delay path of the pulse generator 423a.

As described above, the pulse signal generated by the pulse generator 423a enables the column reset signal reset_col to pass low through the inverter INV9, and the inverter INV10 and the inverter ( The page active signal page_atv is enabled high after the INV11. Thus, the column reset signal reset_col having the low pulse section resets the node C to high by turning off the NMOS transistor N0 and turning on the PMOS transistor P0 in the low pulse section. The high reset signal continuously keeps Node B low via inverter INV0, inverter INV1, and first delay circuit 422b. At this time, since the input of the first delay circuit 422b is high, the first delay circuit 422b outputs a low value after being delayed by a predetermined delay time (i section; see FIG. 9B) due to the delay path of the first delay circuit 422b. Therefore, even if the input thereof is high, the first delay circuit 422b outputs a low value after being delayed by a predetermined delay time (sector; see FIG. 9B) by the delay path of the first delay circuit 422b, thereby resetting the column. The signal reset_col and the page active signal page_atv may be generated to generate pulses having a predetermined pulse width. Here, the pulse width of the page active signal page_atv is the pulse width of the column selection signal Yi (see Fig. 6). That is, the reason for this delay is that when the Node B becomes low due to the column reset signal reset_col, the column reset signal reset_col and the page active signal page_atv do not have a desired pulse width. This is because the pulse width may be too narrow. Meanwhile, the low pulse of the column reset signal reset_col input to the next page signal / page active delay signal generator 424 is passed through the second delay circuit 424a including the inverter INV3, an even number of inverters, and a MOS transistor. As a result, the page active delay signal page_atv_d is generated with a high pulse and output. The high pulse page active delay signal page_atv_d outputs the node A to low by turning on the NMOS transistor N3 of the next page signal controller 421.

As described above, when the page address signals (page address 0 to 2) are transitioned and the page address transition detection signal atdsum_pg is enabled, the column reset signal reset_col and the page active signal page_atv are low and high pulses, respectively. And reset Node A and Node B to low. As such, when the first page active signal page_atv is enabled, Node A and Node B go low. Meanwhile, in order for the second page active signal page_atv to be enabled, both Node A and Node B must be high. Therefore, the time when the second page active signal page_atv is enabled is when the other goes high later, even if either one of Node A and Node B goes high first.

On the other hand, while the column reset signal reset_col becomes high again and the NMOS transistor N0 is turned on, the page address transition detection signal atdsum_pg of the enable inputted to the NMOS transistor N1 is the page address transition detection signal. The node B, which is an output terminal of the controller 422, is output high. In this state, the next page signal control unit 421 controls the page active delay signal page_atv_d and the next page signal page_next generated by the next page signal / page active delay signal generation unit 424 so that the node A (Node By outputting A) high, the page active signal page_atv can be enabled high again. Accordingly, the second page active signal page_atv is high even if Node B becomes high first, so that Node A, which is controlled by the page active delay signal page_atv_d and the next page signal page_next, is output high. Is enabled when For example, even when Node B is high, the next page signal page_next output from the third delay circuit 424b of the next page signal / page active delay signal generator 424 is made high and the PMOS transistor ( When P2) is turned on, Node A may go high to enable the page active signal page_atv. That is, the next page signal controller 421 and the control logic prevent the page active signal page_atv from being enabled until Node A becomes high even if Node B is quickly enabled. have.

Therefore, even if the page active signal page_atv is enabled even after a short interval (a section in Fig. 12) of the page address transition detection signal atdsum_pg, the global data bus line GDBline and the global data bus bar line GDBBline do not exist. The low pulse section of the page active signal page_atv, which is the precharge time, may be maintained at a time when sufficient precharge is possible (section ⓑ in FIG. 12 or section ⓓ in FIG. 5) and then enabled with high pulse. Here, the precharge time of the global data bus line GDBline and the global data bus bar line GDBBline is an even number of inverters in the third delay circuit 424b of the next page signal / page active delay signal generator 424. This can be determined by adjusting the number of MOS transistors.

As described above, the first page active signal page_atv is enabled by Node B, but the next page active signal page_atv is enabled by Node A, thereby providing a global data bus line. The precharge time of (GDBline) and global data bus barline (GDBBline) is not the low pulse section of the page address detection detection signal (atdsum_pg), but the low pulse section of the page active signal page_atv (Fig. 12). Ⓑ).

Therefore, the page active signal is not enabled each time the page address transition detection signal is enabled, and the next page signal controller outputs the next page signal output from the third delay circuit in the next page signal / page active delay signal generator. And a page active signal having a pulse section capable of sufficiently precharging the global data bus line and the global data bus bar line by logically controlling the NAND gate and the column reset signal / page active signal generator for the controlled signal. Can be generated.

By securing enough time to fully precharge the global data bus line and the global data bus line, even when the page address changes short due to skew or incorrect input between the page addresses during page read operation of the pseudo S-RAM, Output of data may be possible.

1 is a read timing diagram of an eight page mode for a pseudo S RAM for explaining a data read operation of the pseudo S RAM;

2 is a page read simulation timing diagram of a conventional pseudo S-RAM in which a malfunction occurs in a data read operation when the page address changes shortly.

3 is a simulation timing diagram illustrating a case in which global data bus lines are incompletely precharged in FIG. 2; FIG.

4 is a page read simulation timing diagram of a pseudo S-RAM according to a preferred embodiment of the present invention for preventing a malfunction of data reads in the case of a short page address transition;

FIG. 5 is a simulation timing diagram of improving the operation of the precharge to prevent malfunction of the data read in FIG. 4; FIG.

6 is a block diagram of a page read operation unit of a pseudo S RAM according to an exemplary embodiment of the present invention;

7 is a page active circuit diagram of a page read operation unit of a pseudo S RAM according to an exemplary embodiment of the present invention;

FIG. 8A is a circuit diagram of the pulse generator of FIG. 7; FIG.

8B is a waveform diagram illustrating input and output of the pulse generator of FIG. 7;

FIG. 9A is a circuit diagram of the first delay circuit unit of FIG. 7; FIG.

FIG. 9B is a waveform diagram illustrating input and output of the first delay circuit unit of FIG. 7; FIG.

FIG. 10A is a circuit diagram of the second delay circuit unit of FIG. 7; FIG.

FIG. 10B is a waveform diagram illustrating input and output of the second delay circuit unit of FIG. 7; FIG.

FIG. 11A is a circuit diagram of the third delay circuit unit of FIG. 7; FIG.

FIG. 11B is a waveform diagram illustrating input and output of the third delay circuit unit of FIG. 7; FIG. And

12 is a simulation timing diagram for a page active circuit of a pseudo S-RAM according to a preferred embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: page read block diagram 100: address buffer

200: page address buffer 300: row driver

310: address transition detector 320: low active signal generator

330: low signal control unit 400: column drive unit

410: page address transition detection unit 420: page active signal generation unit

421: Next page signal controller 421a: Latch

422: page address transition detection signal control unit 422a: latch

422b: first delay circuit

423: column reset signal / page active signal generator 423a: pulse generator

424: Next page signal / page active delay signal generator

424a: second delay circuit 424b: third delay circuit

430: column signal control unit / CS: chip selection signal

/ WE: write enable signal / OE: output enable signal

Dout: Data tRC: Lead Cycle

tPRC: Page Lead Cycle tAA: Address Access Time

tPAA: Page address access time address 3 to 20: Address signal

atdsum_pg: Page address transition detection signal

gdb_pcg: global data bus line precharge signal

dbsa_stb: sense amplification signal

Page address 0 to 2: Page address signal page_atv: Page active signal

page_atv_d: Page active delay signal page_next: Next page signal reset_col: Column reset signal low_atv: Low active signal GDBline: Global data bus line

GDBBline: Global Data Bus Barline GIO: Global I / O

WL: Word line signal Yi: Column (bit line) selection signal

Claims (8)

In pseudo-S-RAM, A row driver for detecting a transition of the address signal and enabling the word line signal; A page address transition detection unit for detecting a transition of the page address signal and outputting a page address transition detection signal; A page address transition detection signal controller for outputting a first output signal having a first or second reference level with respect to the input page address transition detection signal and the first feedback signal input; A next page signal controller configured to output a second output signal having a first or second reference level with respect to the input of the second feedback signal and the third feedback signal; Logic means for outputting a third output signal of a second reference level when the first output signal of the page address transition detection signal controller and the second output signal of the next page signal controller are signals of a first reference level; A column reset signal / page active signal generator for outputting a page active signal having a pulse interval of a first reference level and the first feedback signal when the third output signal of the logic means is a second reference level; And A next page signal for outputting the second feedback signal delayed by the page active signal by a second delay time and the third feedback signal delayed by the page active signal by a third delay time, to the input of the first feedback signal; A page active signal generator having a page active delay signal generator, and And a column driver having a column signal controller for enabling a column selection signal to be input to the page active signal. The method of claim 1, wherein the page address transition detection signal control unit Enabling the input of the page address detection detection signal of the first reference level to the input of the first feedback signal having the first reference level to output a signal of the second reference level, wherein the second having the second reference level First switching means for disabling the input of the page address transition detection signal with respect to the input of the first feedback signal and outputting a signal having a first reference level; First latch means for latching and outputting the output signal of the switching means; And And outputs a signal having a second reference level after outputting a signal having a first reference level for a first delay time with respect to the signal having the first reference level of the first latching means, and outputting a signal having a second reference level. And first delay means for outputting a signal having a first reference level to a signal having a second reference level of the means. 4. The next page signal controller of claim 1, In the state where the power-up signal having the first reference level is input, the third feedback signal is disabled with respect to the input of the second feedback signal having the first reference level to output the signal of the first reference level. Second switching means for outputting a signal of a second reference level by enabling the input of the third feedback signal to the input of the second feedback signal having a reference level; And a second latch means for latching and outputting an output signal of the switching means. The method of claim 1, wherein the column reset signal / page active signal generation unit A pulse generator for generating a pulse having a pulse section of a first reference level when the third output signal of the logic means is a second reference level; First inverter means for inverting the signal output from the pulse generator to output the first feedback signal; And And second inverter means for inverting the signal output from the first inverter means to output the page active signal. The apparatus of claim 1, wherein the next page signal / page active delay signal generator Third inverter means for inverting the input of the input first feedback signal; Second delay means for delaying the signal output from the third inverter means by a second delay time to output the second feedback signal; And And third delay means for delaying the signal output from the second delay means by a third delay time to output the third feedback signal. The pseudo SRAM of claim 1, wherein the first reference level and the second reference level are high and low signals, respectively. The pseudo S-RAM according to claim 1, wherein the first, second, and third feedback signals are column reset signals, page active delay signals, and next page signals, respectively. delete