KR20010077267A - A Method of Isolation for Semiconductor Devices Fabrication - Google Patents

Abstract

PURPOSE: An isolation method for manufacturing a semiconductor device is provided to increase efficiency of an isolation process and to prevent problems such as a dent, by forming a field insulation layer having desired width and depth through a simplified process as compared with a conventional shallow trench isolation(STI) process. CONSTITUTION: An insulation layer is formed on a semiconductor substrate(10). The insulation layer is patterned to form a field insulation layer. A hole is formed in a portion corresponding to an active region so that the semiconductor substrate is exposed to a bottom surface of the hole. A polysilicon layer(46) is deposited on a front surface of the substrate to fill the hole, and a planarization process is performed to expose an upper portion of the field insulation layer.

Description

A Method of Isolation for Semiconductor Devices Fabrication

The present invention relates to a device isolation method for manufacturing a semiconductor device, and more particularly, to a method of forming a field separator and an active region separated from a semiconductor substrate.

A semiconductor device is formed by forming a film made of a conductor, a non-conductor, and a semiconductor on a semiconductor substrate, and forming and combining a large number of electrical and electronic devices and wirings through processing such as patterning. Therefore, in order to form a large number of devices and wirings in a narrow space, and to perform their respective functions, each device must be formed to be accurately separated from other devices while being connected to the outside through the wirings.

Various region separation methods are used as a method of forming individual devices in each region by electrically separating each region of the substrate constituting the semiconductor device from other regions. There are many LOCOS processes and variations thereof that have been used in the past. In these methods, a silicon nitride film is partially formed and patterned on the substrate, and then the substrate in which the silicon nitride film is removed is thermally oxidized and used as an insulating film for device isolation.

However, in these methods, there was a bird's beak phenomenon in which silicon was oxidized for insulation to form an oxide film, which was sharply expanded to the periphery of the silicon nitride film region by the expansion pressure, thereby reducing the range of the active region. As device integration has progressed, the Buzz Big phenomenon has been a major deterrent to device integration. Recently used is the STI (Shallow Trench Isolation) method. In this method, a trench is formed in a semiconductor substrate and an insulating film is filled in the trench to be used as a field separator. By using the STI method, the field insulating film is suitable for device isolation and has a clear shape, thereby widening the active area as compared with the field separator of the conventional LOCOS method.

The STI method basically forms a silicon nitride film on a semiconductor substrate, patterns it, forms a trench on the substrate using an etching pattern of a silicon nitride film, fills the CVD oxide film in the formed trench, and forms an oxide film on the silicon nitride mask. The silicon nitride layer pattern, which is used as an etch mask, is finally removed by wet removal, exposing the active region.

However, the field insulating film formed only by the above-described method has a problem in that the trench forming the trench is damaged and oxygen diffuses into the substrate while the oxide film is filled, thereby recovering the etching surface damage by surface thermal oxidation and forming a silicon nitride film lining. The method of filling the oxide film is used. In addition, in the case of using a silicon nitride lining, a large portion of the lining is etched in the step of removing the trench forming silicon nitride pattern to cause a dent phenomenon, and the dent causes an insulation problem in a subsequent process. This is often done more.

These subsidiary processes transform the STI method into a cumbersome and inefficient process. Therefore, there is a need for a simpler and more effective device isolation method.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a device separation method which is simpler and more effective than the conventional STI method while maximizing the active area.

1 to 5 are process cross-sectional views illustrating steps of a process according to an embodiment of the present invention.

※ Explanation of code for main part of drawing

10 substrate 12 insulating film

14: organic antireflection film 21: photoresist pattern

22: insulating film pattern 46: polysilicon layer

56: polysilicon pattern

According to an aspect of the present invention, there is provided a method of forming an insulating film on a semiconductor substrate, forming a field insulating film by patterning the insulating film, and forming a hole in a portion corresponding to an active region to expose the semiconductor substrate on the bottom of the hole. And depositing polysilicon on the entire surface of the process substrate to fill the hole and to planarize to expose the upper portion of the field insulating film.

In the present invention, in order to form a feed insulating film through a patterning operation, it is preferable to first use an organic antireflection film on the insulating film. This is because the organic anti-reflection film is removed together in the process of removing the photoresist pattern used in the patterning process so that no separate removal process is required.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. 1 to 5 are process cross-sectional views illustrating steps of a process according to an embodiment of the present invention.

FIG. 1 shows a state in which an insulating film 12 is formed on an initial semiconductor substrate 10 and an organic antireflection film 14 is formed thereon. As the insulating film 12, USG (Undoped Silicate Glass) film was formed by CVD (Chemical Vapor Deposition) at a high temperature of about 800 ° C. The thickness of the insulating film 12 may be formed by calculating the required thickness of the field insulating film to be formed.

FIG. 2 shows a state in which the photoresist pattern 21 is first formed for the patterning operation of the insulating film 12 in the state of FIG. 1. First, a photoresist pattern 21 is formed through a process of forming a photoresist film, exposing and developing using a photomask. The portion covered by the photoresist pattern 21 is a portion where the field insulating film is to be formed and the active region is exposed.

FIG. 3 illustrates a state in which an insulating film pattern 32 made of an insulating film is formed by performing an insulating film etching with the photoresist pattern 21 using an etching mask in the state of FIG. 2. At this time, the organic anti-reflection film 14 exposed before the insulating film is removed. Etching is performed until the surface of the semiconductor substrate before the insulating film is exposed, and it is preferable to perform some overetching to expose the clean substrate surface. The portion from which the insulating film 12 is removed forms a hole. The insulating film pattern 22 formed at this time becomes a field insulating film, and the hole portion becomes an active region when viewed in plan view.

FIG. 4 completely removes the photoresist pattern 21 through ashing, wet stripping, or a combination thereof in the state of FIG. 3, and stacks a polysilicon layer 46 on the entire surface of the substrate 10 in the hole formed in FIG. It shows the state which filled polysilicon. In this process, it is preferable that the polysilicon layer 46 is also stacked on the insulating film pattern 22, and a sufficient thickness is stacked to form a flat top surface.

FIG. 5 illustrates a state in which the polysilicon accumulated in the upper portion of the insulating layer pattern 22 is removed by the entire etching in the state of FIG. 4, and the polysilicon pattern 56 fills only the hole space of FIG. 3. In general, the chemical mechanical polishing (CMP) process is used to planarize a silicon oxide film or a tungsten metal film and is not suitable for polysilicon planarization, so that the planarization process is performed using an etch back.

Since the active regions planarized by the etch back are somewhat rough, it may be necessary to add a separate CMP process and perform cleaning before forming the gate insulating film.

In order to increase the conductivity, the polysilicon layer formed in the active region is preferably subjected to an operation including high temperature annealing and containing impurities such as hydrogen for healing a dangling bond.

According to the present invention, it is possible to increase the efficiency of the device isolation process by forming a field insulating film having a desired width and depth through a simple process compared to the conventional STI process. And problems such as dents such as STI can be prevented.

Claims (3)

Forming an insulating film on the semiconductor substrate, Patterning the insulating film to form a field insulating film, and forming a hole in a portion corresponding to an active region to expose a semiconductor substrate on the bottom of the hole; Stacking polysilicon over the entire surface of the process substrate, and planarizing to expose the upper portion of the field insulating film. The method of claim 1, And forming an organic antireflection film over the insulating film before patterning the field insulating film. The method of claim 1, And the etching back method is used in the planarization step.