KR20010074331A - Method for manufacturing of semiconductor device - Google Patents
Method for manufacturing of semiconductor device Download PDFInfo
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- KR20010074331A KR20010074331A KR1020000003218A KR20000003218A KR20010074331A KR 20010074331 A KR20010074331 A KR 20010074331A KR 1020000003218 A KR1020000003218 A KR 1020000003218A KR 20000003218 A KR20000003218 A KR 20000003218A KR 20010074331 A KR20010074331 A KR 20010074331A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 82
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims description 21
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 43
- 239000010937 tungsten Substances 0.000 claims abstract description 43
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 18
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 8
- 239000012495 reaction gas Substances 0.000 claims abstract description 6
- 230000002265 prevention Effects 0.000 claims description 23
- 238000009413 insulation Methods 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 9
- 239000011651 chromium Substances 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 230000008018 melting Effects 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 2
- 229910020751 SixGe1-x Inorganic materials 0.000 claims description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 238000002955 isolation Methods 0.000 abstract 5
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 238000010438 heat treatment Methods 0.000 description 9
- -1 tungsten nitride Chemical class 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 텅스텐막을 반도체막 위에 바로 증착하고 캡절연막을 질소가 포함된 분위기에서 증착함으로서 반도체막과 텅스텐 사이의 반응방지막을 형성하는데 적당한 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for forming a reaction prevention film between a semiconductor film and tungsten by depositing a tungsten film directly on the semiconductor film and depositing a cap insulating film in an atmosphere containing nitrogen. It is about.
일반적으로 텅스텐/반도체 게이트(W/Si gate) 제조 공정은 실리콘과 텅스텐 사이에 반응방지막을 증착하여 텅스텐과 반도체의 반응을 억제한다. 이유는 텅스텐과 반도체는 600℃ 이상의 온도에서는 서로 반응하여 텅스텐 실리사이드가 형성되기 쉽고, 이 때 형성되는 텅스텐 실리사이드는 텅스텐에 비해서 전기 저항이 10배이상 높아서 고집적 회로의 게이트 전극 물질로 사용하기가 어렵다. 또 실리사이드가 형성 될 때 반도체막의 파괴가 발생하여 게이트 전극의 구조를 허물어 뜨리는데 이것을 방지하기 위해 반응방지막이 필요하다.In general, a tungsten / semiconductor gate (W / Si gate) manufacturing process deposits a reaction barrier between silicon and tungsten to suppress the reaction of tungsten with the semiconductor. The reason is that tungsten and semiconductor are easily reacted with each other at a temperature of 600 ° C. or higher, and tungsten silicide formed is difficult to use as a gate electrode material of a highly integrated circuit because the electrical resistance is 10 times higher than that of tungsten. In addition, when the silicide is formed, breakage of the semiconductor film occurs, which destroys the structure of the gate electrode. A reaction prevention film is necessary to prevent this.
상기의 반응방지막으로 주로 사용되는 대표적인 물질로는 실리콘(Si) 및 텅스텐(W)과 반응하지 않는 천이금속과 고융점 금속인 티타튬(Ti), 몰리뷰덴(Mo), 텅스텐(W), 크롬(Cr), 주석(Sb), 탄탈륨(Ta)등의 질화물이며, 전기전도성이 있는 산화물도 적용될 수 있다.Representative materials mainly used as the reaction prevention film is a transition metal that does not react with silicon (Si) and tungsten (W) and high melting point metals such as titanium (Ti), molybdenum (Mo), tungsten (W), Nitrides such as chromium (Cr), tin (Sb), and tantalum (Ta) may also be applied to oxides having electrical conductivity.
이하 첨부된 도면을 참고하여 종래의 반도체 소자의 제조 방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 1h는 종래의 반도체 소자의 제조 방법을 나타낸 공정 단면도이다.1A to 1H are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.
도 1a와 같이 반도체 기판(11) 위에 게이트 절연막(13)을 형성하고, 도 1b와 같이 게이트 절연막(13) 위에 반도체막(14)을 증착한다.A gate insulating film 13 is formed on the semiconductor substrate 11 as shown in FIG. 1A, and a semiconductor film 14 is deposited on the gate insulating film 13 as shown in FIG. 1B.
여기서 반도체막으로는 폴리 실리콘 등을 사용한다.Here, polysilicon or the like is used as the semiconductor film.
도 1c와 같이 반도체막(14) 위에 이후에 형성될 텅스텐과의 반응을 방지하기 위해 CVD법으로 반응방지막(15)을 형성하고, 도 1d와 같이 반응방지막(15) 위에 텅스텐막(16)을 형성한다.In order to prevent a reaction with tungsten to be formed later on the semiconductor film 14 as shown in FIG. 1C, a reaction prevention film 15 is formed by a CVD method, and a tungsten film 16 is formed on the reaction prevention film 15 as shown in FIG. 1D. Form.
도 1e와 같이 텅스텐막(16) 위에 캡절연막(17)을 형성한다.As shown in FIG. 1E, a cap insulation layer 17 is formed on the tungsten layer 16.
도 1f와 같이 캡절연막(17) 위에 포토레지스트(18)를 도포 한 후, 게이트 전극을 정의하기 위해 노광 및 현상 공정을 이용하여 포토레지스트(18)를 패터닝한다.After the photoresist 18 is coated on the cap insulating layer 17 as shown in FIG. 1F, the photoresist 18 is patterned by using an exposure and development process to define a gate electrode.
도 1g와 같이 패터닝된 포토레지스트(18)를 마스크로 이용한 식각 공정을 통하여 캡절연막(17), 텅스텐막(16), 반응방지막(15), 반도체막(14)을 선택적으로 제거하여 게이트 전극을 형성하고, 포토레지스트(18)를 제거한다.As shown in FIG. 1G, the cap insulation layer 17, the tungsten layer 16, the reaction prevention layer 15, and the semiconductor layer 14 are selectively removed through an etching process using the patterned photoresist 18 as a mask. And the photoresist 18 is removed.
도 1h와 같이, 게이트 전극 양측의 반도체 기판(11) 표면 내에 반도체 기판(11)과 다른 타입의 이온을 주입하여 소오스(12a)와 드레인(12b) 영역을 형성한다.As shown in FIG. 1H, different types of ions from the semiconductor substrate 11 are implanted into the surfaces of the semiconductor substrate 11 on both sides of the gate electrode to form the source 12a and drain 12b regions.
또 다른 실시예로서, 상기의 기술에서처럼 반응방지막을 별도의 공정을 통해 형성하지 않고 텅스텐 질화막을 반도체막 위에 증착하고 고온에서 열처리하는 방법이다.As another embodiment, a tungsten nitride film is deposited on a semiconductor film and heat-treated at a high temperature without forming a reaction prevention film through a separate process as in the above technique.
도 2a 내지 2h는 종래의 반도체 소자 제조 방법을 나타낸 다른 실시예이다.2A to 2H illustrate another example of a conventional semiconductor device manufacturing method.
도 2a와 같이 반도체 기판(21) 위에 게이트 절연막(23)을 형성하고 도 2b와 같이 게이트 절연막(23) 위에 반도체막(24)을 증착시킨다. 반도체막으로는 보통 폴리 실리콘을 사용한다.A gate insulating film 23 is formed on the semiconductor substrate 21 as shown in FIG. 2A, and a semiconductor film 24 is deposited on the gate insulating film 23 as shown in FIG. 2B. Polysilicon is usually used as the semiconductor film.
도 2c와 같이 반도체막(24) 위에 텅스텐 질화막(25)을 증착하고 1000℃이상의 고온에서 열처리를 수행하여 도 2d와 같이 텅스텐 질화막(25)과 반도체막(24) 사이에 실리콘 질화물의 반응방지막(28)을 생기게 하는 동시에 열처리 중에 고온에서 불안정상태인 텅스텐 질화막(25)이 텅스텐막(25a)으로 변화하며, 동시에 텅스텐 질화막(25)에 포함되어 있던 질소와 실리콘이 결합하여 텅스텐과 실리콘 계면에 반응방지막(28)인 실리콘 질화물이 형성된다. 이렇게 형성된 실리콘 질화물은 1000℃이상의 고온까지도 실리콘과 텅스텐의 반응을 잘 억제한다.As shown in FIG. 2C, a tungsten nitride film 25 is deposited on the semiconductor film 24 and subjected to heat treatment at a high temperature of 1000 ° C. or higher, thereby preventing the reaction of silicon nitride between the tungsten nitride film 25 and the semiconductor film 24 as shown in FIG. 28) and the unstable tungsten nitride film 25 changes to the tungsten film 25a during heat treatment, and at the same time, nitrogen and silicon contained in the tungsten nitride film 25 combine to react at the tungsten and silicon interface. Silicon nitride, which is the prevention film 28, is formed. Thus formed silicon nitride inhibits the reaction of silicon and tungsten well even at a high temperature of more than 1000 ℃.
도 2e와 같이 텅스텐막(25a) 위에 캡절연막(26)을 형성한다.As shown in FIG. 2E, a cap insulating film 26 is formed on the tungsten film 25a.
도 2f와 같이 캡절연막(26)위에 포토레지스트(27)를 도포한 후, 노광 및 현상 공정을 통해 포토레지스트(27)를 패터닝하여 게이트 영역을 정의한다.As shown in FIG. 2F, the photoresist 27 is coated on the cap insulating layer 26, and then the photoresist 27 is patterned through an exposure and development process to define a gate region.
도 2g와 같이 패터닝된 포토레지스트(27)를 마스크로 이용한 식각 공정을 통하여 캡절연막(26), 텅스텐막(25a), 반응방지막(28), 반도체막(24)을 선택적으로 제거하여 게이트 전극을 형성하고, 포토레지스트(27)를 제거한다.As shown in FIG. 2G, the cap insulation layer 26, the tungsten layer 25a, the reaction prevention layer 28, and the semiconductor layer 24 are selectively removed through an etching process using the patterned photoresist 27 as a mask. And the photoresist 27 is removed.
도 2h와 같이 게이트 전극 양측의 반도체 기판(21) 표면 내에 반도체 기판과 다른 타입의 이온을 주입하여 소오스(22a)와 드레인(22b) 영역을 형성한다.As shown in FIG. 2H, ions of a different type from the semiconductor substrate are implanted into the surfaces of the semiconductor substrate 21 on both sides of the gate electrode to form the source 22a and drain 22b regions.
그러나 이와 같은 종래의 반도체 소자의 제조 방법에 있어서 다음과 같은 문제점이 있다.However, such a conventional method of manufacturing a semiconductor device has the following problems.
종래의 실시예인 텅스텐/반응방지막/반도체 게이트로 만드는 경우는 첫째, 텅스텐과 반도체 막의 사이에 반응방지막의 증착 단계가 추가되어 공정이 복잡해지고 비용이 증가한다.In the case of making a tungsten / anti-reaction film / semiconductor gate, which is a conventional embodiment, firstly, a deposition step of an anti-reaction film is added between tungsten and a semiconductor film, thereby increasing the complexity and cost of the process.
둘째, 반응방지막의 형성에 따라 상부에 형성되는 텅스텐의 전기적 특성, 특히 전기 전도성이 낮아져 나쁜 영향을 받는다.Second, according to the formation of the reaction prevention film, the electrical properties of the tungsten formed on top, in particular, the electrical conductivity is lowered, which is badly affected.
셋째, 반응방지막의 저항이 텅스텐보다 크기 때문에 게이트 전극의 전기저항을 증가시킨다.Third, since the resistance of the reaction prevention film is larger than tungsten, the electrical resistance of the gate electrode is increased.
한편, 또 다른 실시예인 디누네이션 텅스텐/반도체 게이트로 만드는 경우는 첫째, 반응방지막을 형성하는 열처리 공정이 추가되고, 열처리전의 게이트 전극의 저항이 매우 높다.On the other hand, in the case of making a dentured tungsten / semiconductor gate as another embodiment, first, a heat treatment process for forming a reaction prevention film is added, and the resistance of the gate electrode before heat treatment is very high.
둘째, 열처리가 1000℃이상의 고온에서 진행되기 때문에 하지층에 주는 열적스트레스(thermal stress)가 크다.Second, because the heat treatment proceeds at a high temperature of more than 1000 ℃ thermal stress (thermal stress) to the underlying layer is large.
셋째, 고온 열처리 중에 하부 반도체 기판의 불순물 분포를 변화시킬 가능성이 있기 때문에 이로 인하여 반도체 소자의 동작 특성을 저하시킬 수 있다.Third, since there is a possibility that the impurity distribution of the lower semiconductor substrate is changed during the high temperature heat treatment, the operation characteristics of the semiconductor device can be lowered.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 공정을 단순화시킴과 동시에 열적 안정성이 우수하고 전기저항이 낮은 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above problems, and the object of the present invention is to provide a method of manufacturing a semiconductor device which simplifies the process and has excellent thermal stability and low electrical resistance.
도 1a 내지 1h는 종래 기술에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도.1A to 1H are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2a 내지 2h는 종래 다른 실시예에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도.2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another conventional embodiment.
도 3a 내지 3g는 본 발명에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도.3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도 4는 본 발명의 반도체 소자의 제조 방법에 따른 소자의 SEM사진.Figure 4 is a SEM photograph of the device according to the method of manufacturing a semiconductor device of the present invention.
도 5는 본 발명의 반도체 소자의 제조 방법에 따른 게이트 라인의 면저항을 나타낸 그래프.5 is a graph showing the sheet resistance of the gate line according to the method of manufacturing a semiconductor device of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
31 : 반도체 기판 32a : 소오스31 semiconductor substrate 32a source
32b : 드레인 33 : 게이트 절연막32b: drain 33: gate insulating film
34 : 반도체막 35 : 텅스텐막34 semiconductor film 35 tungsten film
36 : 캡절연막 37 : 포토레지스트36: cap insulation film 37: photoresist
38 : 반응방지막38: reaction prevention film
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 제조방법은 반도체 기판상에 게이트 절연막을 형성하는 단계와, 상기 게이트 절연막상에 반도체막을 증착하는 단계와, 상기 반도체막상에 금속막을 증착하는 단계와, 상기 금속막상에 캡절연막을 증착함과 동시에 상기 반도체막과 금속막 사이에 반응방지막을 형성하는 단계와, 상기 캡절연막, 금속막, 반응방지막, 반도체막을 선택적으로 제거하여 게이트 전극을 형성하는 단계와, 상기 게이트 전극 양측의 반도체 기판 표면내에 소오스와 드레인 영역을 형성하는 단계를 포함하여 형성함을 특징으로 한다.A semiconductor device manufacturing method according to the present invention for achieving the above object comprises the steps of forming a gate insulating film on a semiconductor substrate, depositing a semiconductor film on the gate insulating film, and depositing a metal film on the semiconductor film And forming a reaction prevention film between the semiconductor film and the metal film at the same time as depositing a cap insulation film on the metal film, and selectively removing the cap insulation film, the metal film, the reaction prevention film, and the semiconductor film to form a gate electrode. And forming a source and a drain region in the surface of the semiconductor substrate on both sides of the gate electrode.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 제조 방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 3g는 본 발명에 의한 텅스텐/반도체 게이트 제조 방법에 관한 것이다.3A to 3G relate to a tungsten / semiconductor gate manufacturing method according to the present invention.
도 3a와 같이 반도체 기판(31) 위에 게이트 절연막(33)을 형성한 후 도 3b와 같이 게이트 절연막(33) 위에 반도체막(34)을 증착한다.After the gate insulating film 33 is formed on the semiconductor substrate 31 as shown in FIG. 3A, the semiconductor film 34 is deposited on the gate insulating film 33 as shown in FIG. 3B.
상기 반도체막은 실리콘(Si), 게르마늄(Ge), 실리콘 게르마늄 화합물(SixGe1-x)중 어느 하나를 사용한다.The semiconductor film may be formed of any one of silicon (Si), germanium (Ge), and silicon germanium compound (SixGe1-x).
도 3c와 같이 상기 반도체막(34) 위에 텅스텐막(35)을 증착한다.As shown in FIG. 3C, a tungsten film 35 is deposited on the semiconductor film 34.
여기서 텅스텐막 대신에 고융점 금속인 몰리뷰덴(Mo), 티타늄(Ti), 크롬(Cr), 주석(Sb), 탄탈륨(Ta)등을 증착 시킬 수 있다.Instead of the tungsten film, molybdenum (Mo), titanium (Ti), chromium (Cr), tin (Sb), and tantalum (Ta), which are high melting point metals, may be deposited.
도 3d와 같이 상기 텅스텐막(35)이 형성된 반도체 기판(31)을 질소가 포함된반응가스 분위기로 텅스텐막(35)위에 캡절연막(36)을 증착함과 동시에 상기 반도체막(34)과 텅스텐막(35) 사이에 반응방지막(38)을 형성한다.As shown in FIG. 3D, the cap insulation layer 36 is deposited on the tungsten layer 35 in a reaction gas atmosphere containing nitrogen in the semiconductor substrate 31 on which the tungsten layer 35 is formed. An anti-reaction film 38 is formed between the films 35.
여기서 캡절연막(36)은 600℃이상의 온도에서 증착하며 SiN 증착 공정의 초기에 반응가스에 포함된 질소에 의해서 텅스텐막(35)과 반도체막(34)사이에 실리콘(Si)-질소(N) 결합을 가지는 반응 방지막(38)이 형성된다. 따라서 이 공정으로 캡절연막(36) 및 반응 방지막(38)을 동시에 얻을 수 있다.Here, the cap insulating film 36 is deposited at a temperature of 600 ° C. or higher, and silicon (Si) -nitrogen (N) is formed between the tungsten film 35 and the semiconductor film 34 by nitrogen included in the reaction gas at the beginning of the SiN deposition process. A reaction prevention film 38 having a bond is formed. Therefore, the cap insulation film 36 and the reaction prevention film 38 can be obtained simultaneously by this process.
도 3e와 같이, 상기 캡절연막(36)위에 포토레지스트(37)를 도포 한 후 게이트 전극을 패턴닝하기 위해 노광 및 현상 공정을 이용하여 포토레지스트(37)를 패터닝한다.As shown in FIG. 3E, after the photoresist 37 is coated on the cap insulating layer 36, the photoresist 37 is patterned by using an exposure and development process to pattern the gate electrode.
도 3f와 같이 패터닝된 포토레지스트(37)를 마스크로 이용한 식각 공정을 통하여 캡절연막(36), 텅스텐막(35), 반응방지막(38), 반도체막(34)을 선택적으로 제거하여 게이트 전극을 형성하고, 포토레지스트(37)를 제거한다.As shown in FIG. 3F, the cap insulation layer 36, the tungsten layer 35, the reaction prevention layer 38, and the semiconductor layer 34 are selectively removed through an etching process using the patterned photoresist 37 as a mask. And the photoresist 37 is removed.
도 3g와 같이 게이트 전극 양측에 반도체 기판(31)과 다른 타입의 이온을 주입하여 소오스(32a)와 드레인(32b) 영역을 형성하면 본 발명의 제조 공정이 완료된다.As illustrated in FIG. 3G, when the semiconductor substrate 31 and the other type of ions are implanted on both sides of the gate electrode to form the source 32a and drain 32b regions, the manufacturing process of the present invention is completed.
한편, 도 4는 본 발명의 반도체 소자 제조 방법에 따른 소자의 SEM사진으로서 텅스텐/반도체막 위에 700℃에서 SiCl2H2와 NH3가스를 반응가스로 하여 300Å의 두께로 SiN막을 증착한 사진이다.4 is a SEM photograph of a device according to the method of manufacturing a semiconductor device of the present invention, in which a SiN film is deposited at a thickness of 300 kPa on a tungsten / semiconductor film using SiCl 2 H 2 and NH 3 gas at 700 ° C. as a reaction gas. .
여기서 텅스텐과 반도체막 간의 반응이 억제된 것을 확인 할 수 있다.Here, it can be seen that the reaction between tungsten and the semiconductor film is suppressed.
그리고, 도 5는 본 발명의 반도체 소자 제조 방법에 따른 게이트 라인의 면저항을 나타낸 그래프로서 본 발명을 이용하여 소자를 형성한 후 후속으로 900℃에서 30분 동안 열처리를 거친 0.15㎛선폭의 게이트 전극 저항을 보여준다.5 is a graph showing the sheet resistance of the gate line according to the method of manufacturing a semiconductor device of the present invention, after forming the device using the present invention, and subsequently performing a heat treatment at 900 ° C. for 30 minutes for a gate electrode resistance of 0.15 μm line width. Shows.
도 5에서와 같이, 게이트 전극이 아주 안정된 저항을 확보함을 알 수 있다.As shown in FIG. 5, it can be seen that the gate electrode secures a very stable resistance.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자 제조 방법에 있어서 다음과 같은 효과가 있다.As described above, the semiconductor device manufacturing method according to the present invention has the following effects.
첫째, 별도의 반응방지막 형성 공정을 생략함으로서 공정 단순화 및 제조 비용을 절감시킬 수 있다.First, by eliminating a separate reaction prevention film forming process can simplify the process and reduce the manufacturing cost.
둘째, 기존의 텅스텐/반도체 게이트(W/Si gate) 전극의 전기 저항 보다 낮은 저항을 확보 할 수 있고, 이것을 이용해 게이트 전극의 두께를 감소시킬 수 있다.Second, it is possible to secure a resistance lower than the electrical resistance of the conventional tungsten / semiconductor gate (W / Si gate) electrode, it can be used to reduce the thickness of the gate electrode.
셋째, 열처리 온도가 낮기 때문에 종래의 디누데이션 텅스텐/반도체 게이트보다 하지층에 가하는 열적 스트레스(thermal stress)를 최소화할 수 있다.Third, since the heat treatment temperature is low, it is possible to minimize the thermal stress applied to the underlying layer than the conventional denudementation tungsten / semiconductor gate.
넷째, 열처리 온도가 낮기 때문에 종래의 디누데이션 텅스텐/반도체 게이트에서 문제가 되는 반도체 기판의 불순물 분포 변화로 인한 소자 동작 특성의 열화를 방지 할 수 있다.Fourth, since the heat treatment temperature is low, it is possible to prevent deterioration of device operation characteristics due to a change in the impurity distribution of the semiconductor substrate, which is a problem in the conventional deunidation tungsten / semiconductor gate.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100399930B1 (en) * | 2001-12-31 | 2003-09-29 | 주식회사 하이닉스반도체 | Method of forming gate for semiconductor device |
| KR100937992B1 (en) * | 2003-01-13 | 2010-01-21 | 주식회사 하이닉스반도체 | Gate electrode and method of fabricating semiconductor device having the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100399930B1 (en) * | 2001-12-31 | 2003-09-29 | 주식회사 하이닉스반도체 | Method of forming gate for semiconductor device |
| KR100937992B1 (en) * | 2003-01-13 | 2010-01-21 | 주식회사 하이닉스반도체 | Gate electrode and method of fabricating semiconductor device having the same |
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