KR100291516B1 - Gate electrode formation method of semiconductor device - Google Patents
Gate electrode formation method of semiconductor device Download PDFInfo
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- KR100291516B1 KR100291516B1 KR1019980058928A KR19980058928A KR100291516B1 KR 100291516 B1 KR100291516 B1 KR 100291516B1 KR 1019980058928 A KR1019980058928 A KR 1019980058928A KR 19980058928 A KR19980058928 A KR 19980058928A KR 100291516 B1 KR100291516 B1 KR 100291516B1
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- film
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- tungsten
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 230000015572 biosynthetic process Effects 0.000 title 1
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 30
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000010405 reoxidation reaction Methods 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 230000006866 deterioration Effects 0.000 claims abstract description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 29
- 229910052721 tungsten Inorganic materials 0.000 claims description 29
- 239000010937 tungsten Substances 0.000 claims description 29
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 23
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 23
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- 239000010941 cobalt Substances 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 5
- 239000011651 chromium Substances 0.000 claims description 4
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 2
- 229910019001 CoSi Inorganic materials 0.000 claims description 2
- TWDJIKFUVRYBJF-UHFFFAOYSA-N Cyanthoate Chemical compound CCOP(=O)(OCC)SCC(=O)NC(C)(C)C#N TWDJIKFUVRYBJF-UHFFFAOYSA-N 0.000 claims description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- 229910008484 TiSi Inorganic materials 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims description 2
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 6
- 239000007789 gas Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
- H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
- H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
Abstract
본 발명은 반도체 소자의 게이트 전극 형성방법에 관한 것으로, 보다 상세하게는, 고집적화에 유리하게 적용시킬 수 있는 반도체 소자의 게이트 전극 형성방법에 관한 것이다. 본 발명의 반도체 소자의 게이트 전극 형성방법은, 실리콘 기판 상에 게이트 산화막과 금속막 및 제1금속실리사이드막을 순차적으로 형성하는 단계; 상기 제1금속실리사이드막 및 금속막을 식각하여 이층 구조의 게이트 전극을 형성하는 단계; 상기 게이트 전극을 포함한 실리콘 기판의 전면 상에 소정 두께로 제2금속실리사이드막을 증착하는 단계; 상기 제2금속실리사이드막을 블랭킷 식각하여 게이트 전극의 측벽에 스페이서를 형성하는 단계; 및 상기 게이트 전극을 형성하기 위한 식각 공정에서 발생된 게이트 산화막의 열화를 회복시키기 위하여, 게이트 재산화 공정을 실시하는 단계를 포함하여 이루어진다.The present invention relates to a method of forming a gate electrode of a semiconductor device, and more particularly, to a method of forming a gate electrode of a semiconductor device that can be advantageously applied to high integration. A method of forming a gate electrode of a semiconductor device of the present invention includes the steps of sequentially forming a gate oxide film, a metal film and a first metal silicide film on a silicon substrate; Etching the first metal silicide layer and the metal layer to form a gate electrode having a two-layer structure; Depositing a second metal silicide layer on a front surface of the silicon substrate including the gate electrode at a predetermined thickness; Blanket etching the second metal silicide layer to form spacers on sidewalls of the gate electrode; And performing a gate reoxidation process to recover deterioration of the gate oxide film generated in the etching process for forming the gate electrode.
Description
본 발명은 반도체 소자의 게이트 전극 형성방법에 관한 것으로, 보다 상세하게는, 고집적화에 유리하게 적용시킬 수 있는 반도체 소자의 게이트 전극 형성방법에 관한 것이다.The present invention relates to a method of forming a gate electrode of a semiconductor device, and more particularly, to a method of forming a gate electrode of a semiconductor device that can be advantageously applied to high integration.
모스팻(MOSFET)의 게이트 전극은 일반적으로 도핑된 다결정실리콘이나, 또는, 전극의 비저항을 낮추기 위하여 텅스텐 실리사이드(WSix)과 다결정실리콘의 이층 구조를 사용하고 있다.The gate electrode of MOSFET is generally doped polycrystalline silicon, or in order to reduce the resistivity of the electrode, a bilayer structure of tungsten silicide (WSi x ) and polycrystalline silicon is used.
도 1a 내지 도 1c는 다결정실리콘막과 텅스텐실리사이드막의 이층 구조로 게이트 전극을 형성하는 종래 기술에 따른 게이트 전극 형성방법을 설명하기 위한 공정 단면도로서, 이를 설명하면 다음과 같다.1A through 1C are cross-sectional views illustrating a method of forming a gate electrode according to the related art, in which a gate electrode is formed in a two-layer structure of a polysilicon film and a tungsten silicide film.
우선, 도 1a에 도시된 바와 같이, 활성영역을 한정하는 소자분리막이 형성된 실리콘 기판(1) 상에 게이트 산화막(2), 다결정실리콘막(3) 및 텅스텐막(4)을 순차적으로 형성하고, 공지된 사진식각 공정으로 상기 텅스텐막(4) 및 다결정실리콘막(3)을 패터닝한다.First, as shown in FIG. 1A, a gate oxide film 2, a polycrystalline silicon film 3, and a tungsten film 4 are sequentially formed on a silicon substrate 1 on which a device isolation film defining an active region is formed. The tungsten film 4 and the polysilicon film 3 are patterned by a known photolithography process.
그런 다음, 텅스텐막(4)과 다결정실리콘막(3)이 반응되도록, 열처리 공정을 수행한다. 이때, 열처리 공정이 수행되는 동안, 텅스텐막(4)과 다결정실리콘막(3)의 계면에서 텅스텐과 실리콘간의 반응이 일어나게 됨으로써, 도 1b에 도시된 바와 같이, 텅스텐 실리사이드막(5)이 형성된다.Then, a heat treatment process is performed such that the tungsten film 4 and the polycrystalline silicon film 3 react. At this time, during the heat treatment process, a reaction between tungsten and silicon occurs at the interface between the tungsten film 4 and the polysilicon film 3, thereby forming a tungsten silicide film 5 as shown in FIG. 1B. .
이후, 도 1c에 도시된 바와 같이, 반응하지 않고 잔류된 텅스텐막을 제거하여 다결정실리콘막(3)과 텅스텐실리사이드막(5)의 이층 구조로된 게이트 전극(10)을 형성한다.Thereafter, as shown in FIG. 1C, the tungsten film remaining without reaction is removed to form a gate electrode 10 having a two-layer structure of the polycrystalline silicon film 3 and the tungsten silicide film 5.
그러나, 다결정실리콘막과 텅스텐 실리사이드막의 이층 구조로 게이트 전극을 형성하는 종래 기술은 다음과 같은 문제점이 있다.However, the prior art of forming a gate electrode in a two-layer structure of a polysilicon film and a tungsten silicide film has the following problems.
텅스텐 실리사이드의 비저항은 대략 100μΩ-㎝ 정도로서, 다결정실리콘에 비해서는 낮은 비저항을 갖지만, 여전히 큰 비저항을 갖고 있기 때문에, 고집적 반도체 소자, 예컨데, 1G 이상의 고속으로 동작하는 소자를 얻기 위해서는 게이트 전극의 저항을 더욱 감소시켜야 한다.Tungsten silicide has a specific resistance of about 100 μm-cm, which is lower than that of polysilicon, but still has a large specific resistance. Thus, in order to obtain a highly integrated semiconductor device, for example, a device operating at high speed of 1G or more, the resistance of the gate electrode is increased. Should be further reduced.
한편, 종래에는 비저항이 약 10μΩ-㎝인 텅스텐 등의 금속 재료로 게이트 전극을 형성하려는 연구가 진행되고 있다. 그러나, 이 경우에는 게이트 산화막 상에 텅스텐 또는 텅스텐/다결정실리콘을 증착한 후, 상기 금속막들을 식각하여 게이트 전극을 형성하게 되는데, 상기한 식각 공정 동안에 게이트 산화막의 열화가 발생되기 때문에 상기 게이트 산화막의 열화를 보상하기 위하여 후속에서 게이트 재산화(Gate Re-oxidation) 공정을 수행해야 한다. 그런데, 게이트 재산화 공정이 진행되는 동안, 텅스텐막이 산화되어 부도체로 전환됨으로써, 게이트 전극의 기능이 소실되는 문제점이 있다.On the other hand, in the past, research is being conducted to form the gate electrode from a metal material such as tungsten having a specific resistance of about 10 mu Ω-cm. However, in this case, after depositing tungsten or tungsten / polysilicon on the gate oxide layer, the metal layers are etched to form a gate electrode, and the gate oxide layer is deteriorated during the etching process. In order to compensate for the degradation, a gate re-oxidation process must be performed subsequently. By the way, while the gate reoxidation process is in progress, the tungsten film is oxidized and converted into a non-conductor, so that the function of the gate electrode is lost.
따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은, 게이트 재산화 공정시에 텅스텐막이 산화되는 것을 방지함으로써, 낮은 비저항의 게이트 전극을 형성할 수 있는 반도체 소자의 게이트 전극 형성방법을 제공하는 데, 그 목적이 있다.Accordingly, the present invention devised to solve the above problems provides a method of forming a gate electrode of a semiconductor device capable of forming a low specific resistance gate electrode by preventing the tungsten film from being oxidized during the gate reoxidation process. There is a purpose.
도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 공정 단면도.1A to 1C are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device according to the prior art.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device in accordance with an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 실리콘 기판 12 : 소자분리막11 silicon substrate 12 device isolation film
13 : 게이트 산화막 14 : 텅스텐막13 gate oxide film 14 tungsten film
15 : 제1텅스텐실리사이드막 16 : 제2텅스텐실리사이드막15: first tungsten silicide film 16: second tungsten silicide film
16a : 스페이서 20 : 게이트 전극16a: spacer 20: gate electrode
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 게이트 전극 형성방법은, 실리콘 기판 상에 게이트 산화막과 금속막 및 제1금속실리사이드막을 순차적으로 형성하는 단계; 상기 제1금속실리사이드막 및 금속막을 식각하여 이층 구조의 게이트 전극을 형성하는 단계; 상기 게이트 전극을 포함한 실리콘 기판의 전면 상에 소정 두께로 제2금속실리사이드막을 증착하는 단계; 상기 제2금속실리사이드막을 블랭킷 식각하여 게이트 전극의 측벽에 스페이서를 형성하는 단계; 및 상기 게이트 전극을 형성하기 위한 식각 공정에서 발생된 게이트 산화막의 열화를 회복시키기 위하여, 게이트 재산화 공정을 실시하는 단계를 포함하여 이루어진다.A method of forming a gate electrode of a semiconductor device of the present invention for achieving the above object comprises the steps of sequentially forming a gate oxide film, a metal film and a first metal silicide film on a silicon substrate; Etching the first metal silicide layer and the metal layer to form a gate electrode having a two-layer structure; Depositing a second metal silicide layer on a front surface of the silicon substrate including the gate electrode at a predetermined thickness; Blanket etching the second metal silicide layer to form spacers on sidewalls of the gate electrode; And performing a gate reoxidation process to recover deterioration of the gate oxide film generated in the etching process for forming the gate electrode.
본 발명에 따르면, 텅스텐막의 표면을 실리사이드막으로 둘러쌓기 때문에, 게이트 재산화 공정시에 텅스텐막이 산화되는 것을 방지할 수 있으며, 이에 따라, 텅스텐막/텅스텐실리사이드막의 이층 구조를 갖는 게이트 전극의 신뢰성을 향상시킬 수 있다.According to the present invention, since the surface of the tungsten film is surrounded by the silicide film, the tungsten film can be prevented from being oxidized during the gate reoxidation process, thereby improving the reliability of the gate electrode having the two-layer structure of the tungsten film / tungsten silicide film. Can be improved.
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 공정 단면도로서, 이를 설명하면 다음과 같다.2A through 2D are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device according to an exemplary embodiment of the present invention.
우선, 도 2a에 도시된 바와 같이, 트랜치형의 소자분리막들(12)이 구비된 실리콘 기판(11) 상에 산화 공정을 통해 게이트 산화막(13)을 성장시키고, 상기 게이트 산화막(13) 상에 CVD 또는 PVD 공정으로 텅스텐막(14)과 제1텅스텐실리사이드막(15)을 순차적으로 증착한다. 이때, 텅스텐막(14)은 200∼2,000Å 정도로 증착하며, 제1텅스텐실리사이드막(15)은 WF6가스와 SiH4, Si2H6, DCS 중의 하나의 가스를 반응시켜 50∼1,000Å 정도로 증착한다.First, as shown in FIG. 2A, the gate oxide layer 13 is grown on the silicon substrate 11 having the trench type device isolation layers 12 by an oxidation process, and then on the gate oxide layer 13. The tungsten film 14 and the first tungsten silicide film 15 are sequentially deposited by CVD or PVD. At this time, the tungsten film 14 is deposited at about 200 to 2,000 mW, and the first tungsten silicide film 15 is reacted at about 50 to 1,000 mW by reacting one gas of WF 6 gas with SiH 4 , Si 2 H 6 , or DCS. Deposit.
여기서, 텅스텐막 대신에 티타늄질화막(TiN), 몰리브덴막(Mo), 타탄륨막(Ta), 알루미늄막(Al), 크롬막(Cr), 코발트막(Co) 또는 백금막(Pt) 등의 전기전도성이 우수한 금속막들 중에서 선택되는 하나의 금속막을 형성하는 것도 가능하다.Here, instead of the tungsten film, the titanium nitride film (TiN), molybdenum film (Mo), tartan film (Ta), aluminum film (Al), chromium film (Cr), cobalt film (Co) or platinum film (Pt) It is also possible to form one metal film selected from metal films having excellent conductivity.
또한, 텅스텐실리사이드막 대신에 티타늄실리사이드막(TiSix) 또는 코발트실리사이드막(CoSix)을 사용하는 것도 가능하며, 아울러, 실리사이드막을 증착하는 대신에 텅스텐막의 표면을 SiH4, Si2H6, DCS 중의 하나의 가스로 어닐링하여 텅스텐실리사이드막을 형성하는 것도 가능하다.It is also possible to use a titanium silicide film (TiSi x ) or a cobalt silicide film (CoSi x ) instead of a tungsten silicide film, and instead of depositing the silicide film, the surface of the tungsten film may be SiH 4 , Si 2 H 6 , DCS. It is also possible to form a tungsten silicide film by annealing with one of these gases.
계속해서, 도 2b에 도시된 바와 같이, 공지된 사진식각 공정으로 제1텅스텐실리사이드막(15) 및 텅스텐(14)을 식각하여 이층 구조의 게이트 전극(20)을 형성한다.Subsequently, as illustrated in FIG. 2B, the first tungsten silicide layer 15 and the tungsten 14 are etched by a known photolithography process to form a gate electrode 20 having a two-layer structure.
그런 다음, 도 2c에 도시된 바와 같이, 이층 구조의 게이트 전극(20)을 포함한 실리콘 기판(11)의 전면 상에 제2텅스텐실리사이드막을 증착한다. 여기서, 텅스텐실리사이드막 대신에 전술한 바와 같이 티타늄실리사이드막 도는 코발트실리사이드막으로 형성하는 것도 가능하다.Next, as shown in FIG. 2C, a second tungsten silicide film is deposited on the entire surface of the silicon substrate 11 including the gate electrode 20 having a two-layer structure. Instead of the tungsten silicide film, it is also possible to form a titanium silicide film or a cobalt silicide film as described above.
다음으로, 도 2d에 도시된 바와 같이, 제2텅스텐실리사이드막에 대한 블랭킷 식각 공정을 수행하여 이층 구조로된 게이트 전극(20)의 측벽에 텅스텐실리사이드 재질의 스페이서(16a)를 형성한다. 이어서, 게이트 전극(20)을 형성하기 위한 식각 공정에서 발생되는 게이트 산화막(12)의 열화를 보상하기 위하여, 게이트 재산화 공정을 수행한다.Next, as shown in FIG. 2D, a blanket etching process is performed on the second tungsten silicide layer to form a spacer 16a of tungsten silicide on the sidewall of the gate electrode 20 having a two-layer structure. Subsequently, a gate reoxidation process is performed to compensate for deterioration of the gate oxide film 12 generated in the etching process for forming the gate electrode 20.
이때, 게이트 전극(20)의 텅스텐막(14)은 제1텅스텐실리사이드막(15), 및 텅스텐실리사이드 재질의 스페이서(16)에 의해 감싸져 있기 때문에, 상기한 게이트 재산화 공정시에 산화되지 않는다. 이에 따라, 텅스텐막(14)은 게이트 전극의 기능을 안정되게 수행할 수 있기 때문에 게이트 전극의 신뢰성은 향상되고, 아울러, 낮은 비저항을 갖는 것으로 인하여, 고속 동작이 가능하게 된다.At this time, since the tungsten film 14 of the gate electrode 20 is surrounded by the first tungsten silicide film 15 and the spacer 16 made of tungsten silicide, the tungsten film 14 is not oxidized during the gate reoxidation process. . Accordingly, since the tungsten film 14 can perform the function of the gate electrode stably, the reliability of the gate electrode is improved and at the same time, it has a low specific resistance, thereby enabling high speed operation.
이후, 도시하지는 않았으나, 텅스텐실리사이드 재질의 스페이서를 제거한 상태에서, 1차 이온주입 공정을 통해 실리콘 기판에 저농도 불순물 영역을 형성하고, 그런 다음, 이층 구조로된 게이트 전극의 측벽에 산화막 또는 질화막 재질의 스페이서를 형성하고, 이어서, 2차 이온주입 공정을 통해 상기 게이트 전극의 양측에 고농도의 소오스/드레인 영역을 형성하여 모스 트랜지스터를 완성한다.Subsequently, although not shown, a low concentration impurity region is formed on the silicon substrate through a primary ion implantation process in a state where the spacer of tungsten silicide is removed, and then an oxide film or a nitride film is formed on the sidewall of the gate electrode having a two-layer structure. A spacer is formed, and then a high concentration source / drain region is formed on both sides of the gate electrode through a secondary ion implantation process to complete the MOS transistor.
이상에서와 같이, 본 발명의 실시예에서는 텅스텐/텅스텐실리사이드의 이층 구조로 게이트 전극을 형성함에 있어서, 텅스텐막의 표면을 실리사이드막으로 보호함으로써, 게이트 재산화 공정시에 텅스텐막이 산화되는 것을 방지할 수 있다.As described above, in the embodiment of the present invention, in forming the gate electrode with a two-layer structure of tungsten / tungsten silicide, the surface of the tungsten film is protected by the silicide film, thereby preventing the tungsten film from being oxidized during the gate reoxidation process. have.
따라서, 텅스텐막의 산화를 방지할 수 있는 것에 기인하여, 게이트 전극의 신뢰성을 향상시킬 수 있고, 특히, 텅스텐막이 낮은 비저항을 갖는 것으로 인하여 고속 동작이 가능하기 때문에, 고집적 및 고속 반도체 소자의 제조에 매우 유리하게 적용시킬 수 있다.Therefore, due to being able to prevent the oxidation of the tungsten film, the reliability of the gate electrode can be improved, and in particular, since the tungsten film has a low specific resistance and can be operated at high speed, it is very suitable for manufacturing high integration and high speed semiconductor devices. It can be advantageously applied.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (8)
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